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[176.184.32.47]) by smtp.gmail.com with ESMTPSA id o22-20020a9d5c16000000b006dc0802ddf5sm381666otk.5.2024.01.09.06.48.34 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 09 Jan 2024 06:48:35 -0800 (PST) Message-ID: Date: Tue, 9 Jan 2024 15:48:31 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC PATCH-for-9.0] hw/display/qxl: Directly use VGACommonState::vram_size Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, =?UTF-8?Q?Marc-Andr=C3=A9_Lureau?= Cc: Gerd Hoffmann , Paolo Bonzini References: <20231124192216.96413-1-philmd@linaro.org> In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::331; envelope-from=philmd@linaro.org; helo=mail-ot1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org +Marc-André On 4/1/24 17:45, Philippe Mathieu-Daudé wrote: > +Paolo > > On 24/11/23 20:22, Philippe Mathieu-Daudé wrote: >> PCIQXLDevice::vram_size seems to be some shadow of >> VGACommonState::vram_size. Just use the latter. >> >> Signed-off-by: Philippe Mathieu-Daudé >> --- >> RFC: I don't understand this field otherwise. >> --- >>   hw/display/qxl.h |  1 - >>   hw/display/qxl.c | 17 ++++++++--------- >>   2 files changed, 8 insertions(+), 10 deletions(-) >> >> diff --git a/hw/display/qxl.h b/hw/display/qxl.h >> index fdac14edad..47463bd485 100644 >> --- a/hw/display/qxl.h >> +++ b/hw/display/qxl.h >> @@ -102,7 +102,6 @@ struct PCIQXLDevice { >>       uint16_t           max_outputs; >>       /* vram pci bar */ >> -    uint64_t           vram_size; >>       MemoryRegion       vram_bar; >>       uint64_t           vram32_size; >>       MemoryRegion       vram32_bar; >> diff --git a/hw/display/qxl.c b/hw/display/qxl.c >> index 7bb00d68f5..0e1c4efc0c 100644 >> --- a/hw/display/qxl.c >> +++ b/hw/display/qxl.c >> @@ -2067,20 +2067,19 @@ static void qxl_init_ramsize(PCIQXLDevice *qxl) >>       /* vram (surfaces, 64bit, bar 4+5) */ >>       if (qxl->vram_size_mb != -1) { >> -        qxl->vram_size = (uint64_t)qxl->vram_size_mb * MiB; >> +        qxl->vga.vram_size = (uint64_t)qxl->vram_size_mb * MiB; >>       } >> -    if (qxl->vram_size < qxl->vram32_size) { >> -        qxl->vram_size = qxl->vram32_size; >> +    if (qxl->vga.vram_size < qxl->vram32_size) { >> +        qxl->vga.vram_size = qxl->vram32_size; >>       } >>       if (qxl->revision == 1) { >>           qxl->vram32_size = 4096; >> -        qxl->vram_size = 4096; >> +        qxl->vga.vram_size = 4096; >>       } >>       qxl->vgamem_size = pow2ceil(qxl->vgamem_size); >>       qxl->vga.vram_size = pow2ceil(qxl->vga.vram_size); >>       qxl->vram32_size = pow2ceil(qxl->vram32_size); >> -    qxl->vram_size = pow2ceil(qxl->vram_size); >>   } >>   static void qxl_realize_common(PCIQXLDevice *qxl, Error **errp) >> @@ -2135,7 +2134,7 @@ static void qxl_realize_common(PCIQXLDevice >> *qxl, Error **errp) >>       qxl->guest_surfaces.cmds = g_new0(QXLPHYSICAL, >> qxl->ssd.num_surfaces); >>       memory_region_init_ram(&qxl->vram_bar, OBJECT(qxl), "qxl.vram", >> -                           qxl->vram_size, &error_fatal); >> +                           qxl->vga.vram_size, &error_fatal); >>       memory_region_init_alias(&qxl->vram32_bar, OBJECT(qxl), >> "qxl.vram32", >>                                &qxl->vram_bar, 0, qxl->vram32_size); >> @@ -2159,7 +2158,7 @@ static void qxl_realize_common(PCIQXLDevice >> *qxl, Error **errp) >>       pci_register_bar(&qxl->pci, QXL_VRAM_RANGE_INDEX, >>                        PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vram32_bar); >> -    if (qxl->vram32_size < qxl->vram_size) { >> +    if (qxl->vram32_size < qxl->vga.vram_size) { >>           /* >>            * Make the 64bit vram bar show up only in case it is >>            * configured to be larger than the 32bit vram bar. >> @@ -2177,8 +2176,8 @@ static void qxl_realize_common(PCIQXLDevice >> *qxl, Error **errp) >>       dprint(qxl, 1, "vram/32: %" PRIx64 " MB [region 1]\n", >>              qxl->vram32_size / MiB); >>       dprint(qxl, 1, "vram/64: %" PRIx64 " MB %s\n", >> -           qxl->vram_size / MiB, >> -           qxl->vram32_size < qxl->vram_size ? "[region 4]" : >> "[unmapped]"); >> +           qxl->vga.vram_size / MiB, >> +           qxl->vram32_size < qxl->vga.vram_size ? "[region 4]" : >> "[unmapped]"); >>       qxl->ssd.qxl.base.sif = &qxl_interface.base; >>       if (qemu_spice_add_display_interface(&qxl->ssd.qxl, >> qxl->vga.con) != 0) { >