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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id v10-20020a62ac0a000000b005dea362ed18sm1435839pfe.27.2023.02.23.15.01.17 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 23 Feb 2023 15:01:18 -0800 (PST) Message-ID: Date: Thu, 23 Feb 2023 13:01:15 -1000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.7.1 Subject: Re: [RFC PATCH] target/arm: properly document FEAT_CRC32 Content-Language: en-US To: =?UTF-8?Q?Alex_Benn=c3=a9e?= , qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell References: <20230222110104.3996971-1-alex.bennee@linaro.org> From: Richard Henderson In-Reply-To: <20230222110104.3996971-1-alex.bennee@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::442; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x442.google.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.09, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 2/22/23 01:01, Alex Bennée wrote: > This is a mandatory feature for Armv8.1 architectures but we don't > state the feature clearly in our emulation list. While checking verify > our cortex-a76 model matches up with the current TRM by breaking out > the long form isar into a more modern readable FIELD_DP code. > > Signed-off-by: Alex Bennée > --- > docs/system/arm/emulation.rst | 1 + > target/arm/cpu64.c | 29 ++++++++++++++++++++++++++--- > target/arm/cpu_tcg.c | 2 +- > 3 files changed, 28 insertions(+), 4 deletions(-) > > diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst > index 2062d71261..2c4fde5eef 100644 > --- a/docs/system/arm/emulation.rst > +++ b/docs/system/arm/emulation.rst > @@ -14,6 +14,7 @@ the following architecture extensions: > - FEAT_BBM at level 2 (Translation table break-before-make levels) > - FEAT_BF16 (AArch64 BFloat16 instructions) > - FEAT_BTI (Branch Target Identification) > +- FEAT_CRC32 (CRC32 instruction) > - FEAT_CSV2 (Cache speculation variant 2) > - FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1) > - FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2) > diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c > index 4066950da1..12e1a532ab 100644 > --- a/target/arm/cpu64.c > +++ b/target/arm/cpu64.c > @@ -912,6 +912,8 @@ static void aarch64_a72_initfn(Object *obj) > static void aarch64_a76_initfn(Object *obj) > { > ARMCPU *cpu = ARM_CPU(obj); > + uint64_t t; > + uint32_t u; > > cpu->dtb_compatible = "arm,cortex-a76"; > set_feature(&cpu->env, ARM_FEATURE_V8); > @@ -928,7 +930,18 @@ static void aarch64_a76_initfn(Object *obj) > cpu->ctr = 0x8444C004; > cpu->dcz_blocksize = 4; > cpu->isar.id_aa64dfr0 = 0x0000000010305408ull; > - cpu->isar.id_aa64isar0 = 0x0000100010211120ull; > + > + /* per r4p1 of the Cryptographic Extension TRM */ > + t = cpu->isar.id_aa64isar0; > + t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* FEAT_PMULL */ > + t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); /* FEAT_SHA1 */ > + t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 1); /* FEAT_SHA512 */ > + t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1); /* FEAT_CRC32 */ > + t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); /* FEAT_LSE */ > + t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); /* FEAT_RDM */ > + t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1); /* FEAT_DotProd */ > + cpu->isar.id_aa64isar0 = t; Ok, so, this might be helpful for grepping, but it's not helpful for reading the documentation, which on page B2-137 uses hex. r~