From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: BALATON Zoltan <balaton@eik.bme.hu>
Cc: qemu-devel@nongnu.org, Bernhard Beschow <shentey@gmail.com>,
"Michael S. Tsirkin" <mst@redhat.com>,
Ani Sinha <anisinha@redhat.com>,
Richard Henderson <richard.henderson@linaro.org>,
Igor Mammedov <imammedo@redhat.com>,
Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>,
Laurent Vivier <lvivier@redhat.com>,
Thomas Huth <thuth@redhat.com>,
Marcel Apfelbaum <marcel.apfelbaum@gmail.com>,
Eduardo Habkost <eduardo@habkost.net>,
Paolo Bonzini <pbonzini@redhat.com>
Subject: Re: [PATCH 09/14] hw/southbridge/ich9: Add a AHCI function
Date: Tue, 20 Feb 2024 07:01:39 +0100 [thread overview]
Message-ID: <de2caec4-c77b-4e1d-ad49-e1af3c515442@linaro.org> (raw)
In-Reply-To: <6cf6d2f4-5f24-fcb9-16c4-ab66d7b5e724@eik.bme.hu>
On 19/2/24 19:31, BALATON Zoltan wrote:
> On Mon, 19 Feb 2024, Philippe Mathieu-Daudé wrote:
>> Instantiate TYPE_ICH9_AHCI in TYPE_ICH9_SOUTHBRIDGE.
>>
>> Since the PC machines can disable SATA (see the
>> PC_MACHINE_SATA dynamic property), add the 'sata-enabled'
>> property to disable it.
>>
>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>> ---
>> MAINTAINERS | 2 ++
>> include/hw/southbridge/ich9.h | 4 ----
>> hw/i386/pc_q35.c | 25 ++++---------------------
>> hw/southbridge/ich9.c | 35 +++++++++++++++++++++++++++++++++++
>> hw/i386/Kconfig | 1 -
>> hw/southbridge/Kconfig | 1 +
>> 6 files changed, 42 insertions(+), 26 deletions(-)
>> diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
>> index 2f15af540f..060358d449 100644
>> --- a/hw/i386/pc_q35.c
>> +++ b/hw/i386/pc_q35.c
>> @@ -61,9 +61,6 @@
>> #include "hw/acpi/acpi.h"
>> #include "target/i386/cpu.h"
>>
>> -/* ICH9 AHCI has 6 ports */
>> -#define MAX_SATA_PORTS 6
>> -
>> struct ehci_companions {
>> const char *name;
>> int func;
>> @@ -129,7 +126,7 @@ static void pc_q35_init(MachineState *machine)
>> PCIDevice *lpc;
>> Object *lpc_obj;
>> DeviceState *lpc_dev;
>> - BusState *idebus[MAX_SATA_PORTS];
>> + BusState *idebus[2] = { };
[*]
>> ISADevice *rtc_state;
>> MemoryRegion *system_memory = get_system_memory();
>> MemoryRegion *system_io = get_system_io();
>> @@ -138,7 +135,6 @@ static void pc_q35_init(MachineState *machine)
>> ISABus *isa_bus;
>> int i;
>> ram_addr_t lowmem;
>> - DriveInfo *hd[MAX_SATA_PORTS];
>> MachineClass *mc = MACHINE_GET_CLASS(machine);
>> bool acpi_pcihp;
>> bool keep_pci_slot_hpc;
>> @@ -239,6 +235,7 @@ static void pc_q35_init(MachineState *machine)
>> object_property_set_link(OBJECT(ich9), "mch-pcie-bus",
>> OBJECT(host_bus), &error_abort);
>> qdev_prop_set_bit(ich9, "d2p-enabled", false);
>> + qdev_prop_set_bit(ich9, "sata-enabled", pcms->sata_enabled);
>> qdev_realize_and_unref(ich9, NULL, &error_fatal);
>>
>> /* irq lines */
>> @@ -302,22 +299,8 @@ static void pc_q35_init(MachineState *machine)
>> 0xff0104);
>>
>> if (pcms->sata_enabled) {
>
> Shouldn't this condition be inverted if you only leave the else leg?
idebus[] is NULL-initialized in [*] so we can remove the else
ladder.
>
> Regards,.
> BALATON Zoltan
>
>> - PCIDevice *pdev;
>> - AHCIPCIState *ich9;
>> -
>> - /* ahci and SATA device, for q35 1 ahci controller is
>> built-in */
>> - pdev = pci_create_simple_multifunction(host_bus,
>> - PCI_DEVFN(ICH9_SATA1_DEV,
>> -
>> ICH9_SATA1_FUNC),
>> - "ich9-ahci");
>> - ich9 = ICH9_AHCI(pdev);
>> - idebus[0] = qdev_get_child_bus(DEVICE(pdev), "ide.0");
>> - idebus[1] = qdev_get_child_bus(DEVICE(pdev), "ide.1");
>> - g_assert(MAX_SATA_PORTS == ich9->ahci.ports);
>> - ide_drive_get(hd, ich9->ahci.ports);
>> - ahci_ide_create_devs(&ich9->ahci, hd);
>> - } else {
>> - idebus[0] = idebus[1] = NULL;
>> + idebus[0] = qdev_get_child_bus(ich9, "ide.0");
>> + idebus[1] = qdev_get_child_bus(ich9, "ide.1");
>> }
next prev parent reply other threads:[~2024-02-20 6:02 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-19 16:38 [PATCH 00/14] hw/southbridge: Extract ICH9 QOM container model Philippe Mathieu-Daudé
2024-02-19 16:38 ` [PATCH 01/14] MAINTAINERS: Add 'ICH9 South Bridge' section Philippe Mathieu-Daudé
2024-02-19 16:38 ` [PATCH 02/14] hw/i386/q35: Add local 'lpc_obj' variable Philippe Mathieu-Daudé
2024-02-19 16:38 ` [PATCH 03/14] hw/acpi/ich9: Restrict definitions from 'hw/southbridge/ich9.h' Philippe Mathieu-Daudé
2024-02-19 16:38 ` [PATCH 04/14] hw/acpi/ich9_tco: Include 'ich9' in names Philippe Mathieu-Daudé
2024-02-19 16:38 ` [PATCH 05/14] hw/acpi/ich9_tco: Restrict ich9_generate_smi() declaration Philippe Mathieu-Daudé
2024-02-20 6:32 ` Philippe Mathieu-Daudé
2024-02-26 9:53 ` Philippe Mathieu-Daudé
2024-02-19 16:38 ` [PATCH 06/14] hw/pci-bridge: Extract QOM ICH definitions to 'ich_dmi_pci.h' Philippe Mathieu-Daudé
2024-02-19 18:15 ` BALATON Zoltan
2024-02-19 18:24 ` BALATON Zoltan
2024-02-20 6:09 ` Philippe Mathieu-Daudé
2024-02-20 12:20 ` BALATON Zoltan
2024-02-20 12:55 ` Thomas Huth
2024-02-26 13:46 ` Philippe Mathieu-Daudé
2024-02-26 13:56 ` BALATON Zoltan
2024-02-20 19:25 ` Bernhard Beschow
2024-02-21 8:54 ` Philippe Mathieu-Daudé
2024-02-19 16:38 ` [PATCH 07/14] hw/southbridge/ich9: Introduce TYPE_ICH9_SOUTHBRIDGE stub Philippe Mathieu-Daudé
2024-02-19 16:38 ` [PATCH 08/14] hw/southbridge/ich9: Add the DMI-to-PCI bridge Philippe Mathieu-Daudé
2024-02-19 16:38 ` [PATCH 09/14] hw/southbridge/ich9: Add a AHCI function Philippe Mathieu-Daudé
2024-02-19 18:31 ` BALATON Zoltan
2024-02-20 6:01 ` Philippe Mathieu-Daudé [this message]
2024-02-19 16:38 ` [PATCH 10/14] hw/i2c/smbus: Extract QOM ICH9 definitions to 'smbus_ich9.h' Philippe Mathieu-Daudé
2024-02-19 16:38 ` [PATCH 11/14] hw/southbridge/ich9: Add the SMBus function Philippe Mathieu-Daudé
2024-02-19 16:38 ` [PATCH 12/14] hw/southbridge/ich9: Add the USB EHCI/UHCI functions Philippe Mathieu-Daudé
2024-02-19 16:38 ` [PATCH 13/14] hw/southbridge/ich9: Extract LPC definitions to 'hw/isa/ich9_lpc.h' Philippe Mathieu-Daudé
2024-02-19 16:38 ` [PATCH 14/14] hw/southbridge/ich9: Add the LPC / ISA bridge function Philippe Mathieu-Daudé
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