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[37.158.132.66]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-42c9628ebacsm12232945f8f.30.2025.11.17.01.48.06 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 17 Nov 2025 01:48:07 -0800 (PST) Message-ID: Date: Mon, 17 Nov 2025 10:48:05 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH RFC v2 01/10] target/arm: explicitly disable MTE4 for max To: Gabriel Brookman , qemu-devel@nongnu.org Cc: Peter Maydell , Gustavo Romero , qemu-arm@nongnu.org References: <20251116-feat-mte4-v2-0-9a7122b7fa76@gmail.com> <20251116-feat-mte4-v2-1-9a7122b7fa76@gmail.com> From: Richard Henderson Content-Language: en-US In-Reply-To: <20251116-feat-mte4-v2-1-9a7122b7fa76@gmail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 11/17/25 02:40, Gabriel Brookman wrote: > Previously, the bits used to advertise the various MTE4 features were > not explicitly set for -cpu max. This commit calls out these bits and > explicitly unsets them. At the end of the patch series, a second commit > will explicitly set all of them. > > Signed-off-by: Gabriel Brookman > --- > target/arm/tcg/cpu64.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c > index 6871956382..ca9557f4cf 100644 > --- a/target/arm/tcg/cpu64.c > +++ b/target/arm/tcg/cpu64.c > @@ -1281,8 +1281,16 @@ void aarch64_max_tcg_initfn(Object *obj) > t = FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_3 */ > t = FIELD_DP64(t, ID_AA64PFR1, NMI, 1); /* FEAT_NMI */ > t = FIELD_DP64(t, ID_AA64PFR1, GCS, 1); /* FEAT_GCS */ > + t = FIELD_DP64(t, ID_AA64PFR1, > + MTEX, 0); /* FEAT_MTE_NO_ADDRESS_TAGS + FEAT_MTE_CANONICAL_TAGS */ > SET_IDREG(isar, ID_AA64PFR1, t); > > + t = GET_IDREG(isar, ID_AA64PFR2); > + t = FIELD_DP64(t, ID_AA64PFR2, MTEFAR, 0); /* FEAT_MTE_TAGGED_FAR */ > + t = FIELD_DP64(t, ID_AA64PFR2, MTESTOREONLY, 0); /* FEAT_MTE_STORE_ONLY */ > + t = FIELD_DP64(t, ID_AA64PFR2, MTEPERM, 0); /* FEAT_MTE_PERM */ > + SET_IDREG(isar, ID_AA64PFR2, t); > + > t = GET_IDREG(isar, ID_AA64MMFR0); > t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 6); /* FEAT_LPA: 52 bits */ > t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16, 1); /* 16k pages supported */ > They weren't explicitly set, but the whole ARMCPU structure, including the isar field, was zeroed upon object creation. So I don't really see the point in this patch. r~