From: Richard Henderson <richard.henderson@linaro.org>
To: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>, qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com,
alistair.francis@wdc.com, dbarboza@ventanamicro.com,
liwei1518@gmail.com, bmeng.cn@gmail.com
Subject: Re: [PATCH 1/1] target/riscv: Remove redundant insn length check for zama16b
Date: Tue, 23 Jul 2024 12:11:27 +1000 [thread overview]
Message-ID: <dea63117-cabd-4669-bffd-e8c0cb8d9147@linaro.org> (raw)
In-Reply-To: <20240723013012.1443-1-zhiwei_liu@linux.alibaba.com>
On 7/23/24 11:30, LIU Zhiwei wrote:
> Both trans_fld/fsd/flw/fsw and gen_load/store will never be a
> translation function for compressed instructions, thus we can
> remove instruction length check for them.
>
> Suggested-by: Alistair Francis <alistair.francis@wdc.com>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
That is both false (trans_fld is used from trans_c_fld), and not the takeaway you should
have gotten (the operation of "fld" should not depend on the encoding).
Perhaps FLD/FSD should depend on the ISA (RV32 vs RV64), but perhaps not. I cannot tell
because I don't see a specification for Zama16b in
https://wiki.riscv.org/display/HOME/RISC-V+Specification+Status
r~
next prev parent reply other threads:[~2024-07-23 2:12 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-23 1:30 [PATCH 1/1] target/riscv: Remove redundant insn length check for zama16b LIU Zhiwei
2024-07-23 2:11 ` Richard Henderson [this message]
2024-07-23 3:50 ` Alistair Francis
2024-07-23 5:29 ` LIU Zhiwei
2024-07-23 5:59 ` Richard Henderson
2024-07-24 6:32 ` LIU Zhiwei
2024-07-25 2:45 ` Richard Henderson
2024-07-25 1:50 ` LIU Zhiwei
2024-07-31 9:38 ` Alistair Francis
2024-07-31 11:21 ` LIU Zhiwei
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