From: WANG Xuerui <i.qemu@xen0n.name>
To: Richard Henderson <richard.henderson@linaro.org>, qemu-devel@nongnu.org
Cc: Alistair.Francis@wdc.com, f4bug@amsat.org
Subject: Re: [PATCH 3/8] accel/tcg: Support TCG_TARGET_SIGNED_ADDR32 for softmmu
Date: Mon, 11 Oct 2021 12:30:05 +0800 [thread overview]
Message-ID: <ded6a5f0-dfcd-d908-afce-491b0273e531@xen0n.name> (raw)
In-Reply-To: <20211010174401.141339-4-richard.henderson@linaro.org>
Hi Richard,
On 2021/10/11 01:43, Richard Henderson wrote:
> When TCG_TARGET_SIGNED_ADDR32 is set, adjust the tlb addend to
> allow the 32-bit guest address to be sign extended within the
> 64-bit host register instead of zero extended.
>
> This will simplify tcg hosts like MIPS, RISC-V, and LoongArch,
> which naturally sign-extend 32-bit values, in contrast to x86_64
> and AArch64 which zero-extend them.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> accel/tcg/cputlb.c | 12 +++++++++++-
> 1 file changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
> index 761f726722..d12621c60e 100644
> --- a/accel/tcg/cputlb.c
> +++ b/accel/tcg/cputlb.c
> @@ -39,6 +39,7 @@
> #ifdef CONFIG_PLUGIN
> #include "qemu/plugin-memory.h"
> #endif
> +#include "tcg-target-sa32.h"
>
> /* DEBUG defines, enable DEBUG_TLB_LOG to log to the CPU_LOG_MMU target */
> /* #define DEBUG_TLB */
> @@ -92,6 +93,9 @@ static inline size_t sizeof_tlb(CPUTLBDescFast *fast)
>
> static inline uintptr_t g2h_tlbe(const CPUTLBEntry *tlb, target_ulong gaddr)
> {
> + if (TCG_TARGET_SIGNED_ADDR32 && TARGET_LONG_BITS == 32) {
It seems this branch's direction should always match that of the branch
added below, so if TARGET_LONG_BITS == TARGET_LONG_BITS == 32 this
invariant is broken? Or is this expected behavior?
> + return tlb->addend + (int32_t)gaddr;
> + }
> return tlb->addend + (uintptr_t)gaddr;
> }
>
> @@ -1234,7 +1238,13 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
> desc->iotlb[index].attrs = attrs;
>
> /* Now calculate the new entry */
> - tn.addend = addend - vaddr_page;
> +
> + if (TCG_TARGET_SIGNED_ADDR32 && TARGET_LONG_BITS < TCG_TARGET_REG_BITS) {
> + tn.addend = addend - (int32_t)vaddr_page;
> + } else {
> + tn.addend = addend - vaddr_page;
> + }
> +
> if (prot & PAGE_READ) {
> tn.addr_read = address;
> if (wp_flags & BP_MEM_READ) {
next prev parent reply other threads:[~2021-10-11 4:34 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-10 17:43 [PATCH 0/8] tcg: support 32-bit guest addresses as signed Richard Henderson
2021-10-10 17:43 ` [PATCH 1/8] tcg: Add TCG_TARGET_SIGNED_ADDR32 Richard Henderson
2021-10-11 4:21 ` WANG Xuerui
2021-10-11 9:55 ` Alex Bennée
2021-10-11 22:07 ` Philippe Mathieu-Daudé
2021-10-11 23:16 ` Alistair Francis
2021-10-10 17:43 ` [PATCH 2/8] accel/tcg: Split out g2h_tlbe Richard Henderson
2021-10-11 4:22 ` WANG Xuerui
2021-10-11 9:55 ` Alex Bennée
2021-10-11 21:48 ` Philippe Mathieu-Daudé
2021-10-11 23:19 ` Alistair Francis
2021-10-10 17:43 ` [PATCH 3/8] accel/tcg: Support TCG_TARGET_SIGNED_ADDR32 for softmmu Richard Henderson
2021-10-11 4:30 ` WANG Xuerui [this message]
2021-10-11 15:27 ` Richard Henderson
2021-10-10 17:43 ` [PATCH 4/8] accel/tcg: Add guest_base_signed_addr32 for user-only Richard Henderson
2021-10-11 22:06 ` Philippe Mathieu-Daudé
2021-10-13 7:07 ` Alistair Francis
2021-10-10 17:43 ` [PATCH 5/8] linux-user: Support TCG_TARGET_SIGNED_ADDR32 Richard Henderson
2021-10-11 10:22 ` Alex Bennée
2021-10-11 15:32 ` Richard Henderson
2021-10-10 17:43 ` [PATCH 6/8] tcg/aarch64: " Richard Henderson
2021-10-11 10:28 ` Alex Bennée
2021-10-11 15:24 ` Richard Henderson
2021-10-13 21:05 ` Richard Henderson
2021-10-10 17:44 ` [PATCH 7/8] target/mips: " Richard Henderson
2021-10-11 4:20 ` WANG Xuerui
2021-10-13 22:24 ` Richard Henderson
2021-10-10 17:44 ` [PATCH 8/8] target/riscv: " Richard Henderson
2021-10-11 22:00 ` Philippe Mathieu-Daudé
2021-10-13 7:08 ` Alistair Francis
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