* [PULL 0/6] loongarch-to-apply queue
@ 2025-10-09 12:35 Song Gao
2025-10-09 12:35 ` [PULL 1/6] bios-tables-test-allowed-diff.h: Allow LoongArch DSDT.* Song Gao
` (6 more replies)
0 siblings, 7 replies; 18+ messages in thread
From: Song Gao @ 2025-10-09 12:35 UTC (permalink / raw)
To: qemu-devel
The following changes since commit 37ad0e48e9fd58b170abbf31c18a994346f62ed7:
Merge tag 'pull-10.2-maintainer-071025-1' of https://gitlab.com/stsquad/qemu into staging (2025-10-07 08:46:28 -0700)
are available in the Git repository at:
https://github.com/gaosong715/qemu.git tags/pull-loongarch-20251009
for you to fetch changes up to fa6af7f6bf6dbc4c83595905d2572ad86358aa67:
target/loongarch: Define loongarch_exception_name() as static (2025-10-09 19:11:37 +0800)
----------------------------------------------------------------
pull-loongarch-20251009
----------------------------------------------------------------
Bibo Mao (3):
target/loongarch: Move TCG specified functions to tcg_cpu.c
target/loongarch: Move function do_raise_exception() to tcg_cpu.c
target/loongarch: Define loongarch_exception_name() as static
Huacai Chen (3):
bios-tables-test-allowed-diff.h: Allow LoongArch DSDT.*
hw/loongarch/virt: Align VIRT_GED_CPUHP_ADDR to 4 bytes
tests/data/acpi/loongarch64: Update expected DSDT.*
include/hw/loongarch/virt.h | 6 +-
target/loongarch/cpu.c | 318 +-----------------------
target/loongarch/internals.h | 4 +-
target/loongarch/tcg/meson.build | 1 +
target/loongarch/tcg/tcg_cpu.c | 322 +++++++++++++++++++++++++
target/loongarch/tcg/tcg_loongarch.h | 1 +
tests/data/acpi/loongarch64/virt/DSDT | Bin 4603 -> 4603 bytes
tests/data/acpi/loongarch64/virt/DSDT.memhp | Bin 5824 -> 5824 bytes
tests/data/acpi/loongarch64/virt/DSDT.numamem | Bin 4609 -> 4609 bytes
tests/data/acpi/loongarch64/virt/DSDT.topology | Bin 4905 -> 4905 bytes
10 files changed, 331 insertions(+), 321 deletions(-)
create mode 100644 target/loongarch/tcg/tcg_cpu.c
^ permalink raw reply [flat|nested] 18+ messages in thread* [PULL 1/6] bios-tables-test-allowed-diff.h: Allow LoongArch DSDT.* 2025-10-09 12:35 [PULL 0/6] loongarch-to-apply queue Song Gao @ 2025-10-09 12:35 ` Song Gao 2025-10-09 12:35 ` [PULL 2/6] hw/loongarch/virt: Align VIRT_GED_CPUHP_ADDR to 4 bytes Song Gao ` (5 subsequent siblings) 6 siblings, 0 replies; 18+ messages in thread From: Song Gao @ 2025-10-09 12:35 UTC (permalink / raw) To: qemu-devel; +Cc: Huacai Chen, maobibo From: Huacai Chen <chenhuacai@kernel.org> Signed-off-by: Huacai Chen <chenhuacai@kernel.org> Reviewed-by: <maobibo@loongson.cn> Message-ID: <20250923143542.2391576-2-chenhuacai@kernel.org> Signed-off-by: Song Gao <gaosong@loongson.cn> --- tests/qtest/bios-tables-test-allowed-diff.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h index dfb8523c8b..2ed837faee 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1 +1,5 @@ /* List of comma-separated changed AML files to ignore */ +"tests/data/acpi/loongarch64/virt/DSDT", +"tests/data/acpi/loongarch64/virt/DSDT.memhp", +"tests/data/acpi/loongarch64/virt/DSDT.numamem", +"tests/data/acpi/loongarch64/virt/DSDT.topology", -- 2.47.0 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PULL 2/6] hw/loongarch/virt: Align VIRT_GED_CPUHP_ADDR to 4 bytes 2025-10-09 12:35 [PULL 0/6] loongarch-to-apply queue Song Gao 2025-10-09 12:35 ` [PULL 1/6] bios-tables-test-allowed-diff.h: Allow LoongArch DSDT.* Song Gao @ 2025-10-09 12:35 ` Song Gao 2025-10-09 12:35 ` [PULL 3/6] tests/data/acpi/loongarch64: Update expected DSDT.* Song Gao ` (4 subsequent siblings) 6 siblings, 0 replies; 18+ messages in thread From: Song Gao @ 2025-10-09 12:35 UTC (permalink / raw) To: qemu-devel; +Cc: Huacai Chen, Nathan Chancellor, WANG Rui, Bibo Mao From: Huacai Chen <chenhuacai@loongson.cn> Now VIRT_GED_CPUHP_ADDR is not aligned to 4 bytes, but if Linux kernel is built with ACPI_MISALIGNMENT_NOT_SUPPORTED, it assumes the alignment, otherwise we get ACPI errors at boot phase: ACPI Error: AE_AML_ALIGNMENT, Returned by Handler for [SystemMemory] (20250404/evregion-301) ACPI Error: Aborting method \_SB.CPUS.CSTA due to previous error (AE_AML_ALIGNMENT) (20250404/psparse-529) ACPI Error: Aborting method \_SB.CPUS.C000._STA due to previous error (AE_AML_ALIGNMENT) (20250404/psparse-529) ACPI Error: Method execution failed \_SB.CPUS.C000._STA due to previous error (AE_AML_ALIGNMENT) (20250404/uteval-68) VIRT_GED_MEM_ADDR and VIRT_GED_REG_ADDR are already aligned now, but use QEMU_ALIGN_UP() to explicitly align them can make code more robust. Reported-by: Nathan Chancellor <nathan@kernel.org> Suggested-by: WANG Rui <wangrui@loongson.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn> Reviewed-by: Bibo Mao <maobibo@loongson.cn> Message-ID: <20250923143542.2391576-3-chenhuacai@kernel.org> Signed-off-by: Song Gao <gaosong@loongson.cn> --- include/hw/loongarch/virt.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h index cd97bdfb8d..76fa57cd07 100644 --- a/include/hw/loongarch/virt.h +++ b/include/hw/loongarch/virt.h @@ -49,9 +49,9 @@ #define VIRT_LOWMEM_SIZE 0x10000000 #define VIRT_HIGHMEM_BASE 0x80000000 #define VIRT_GED_EVT_ADDR 0x100e0000 -#define VIRT_GED_MEM_ADDR (VIRT_GED_EVT_ADDR + ACPI_GED_EVT_SEL_LEN) -#define VIRT_GED_REG_ADDR (VIRT_GED_MEM_ADDR + MEMORY_HOTPLUG_IO_LEN) -#define VIRT_GED_CPUHP_ADDR (VIRT_GED_REG_ADDR + ACPI_GED_REG_COUNT) +#define VIRT_GED_MEM_ADDR QEMU_ALIGN_UP(VIRT_GED_EVT_ADDR + ACPI_GED_EVT_SEL_LEN, 4) +#define VIRT_GED_REG_ADDR QEMU_ALIGN_UP(VIRT_GED_MEM_ADDR + MEMORY_HOTPLUG_IO_LEN, 4) +#define VIRT_GED_CPUHP_ADDR QEMU_ALIGN_UP(VIRT_GED_REG_ADDR + ACPI_GED_REG_COUNT, 4) #define COMMAND_LINE_SIZE 512 -- 2.47.0 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PULL 3/6] tests/data/acpi/loongarch64: Update expected DSDT.* 2025-10-09 12:35 [PULL 0/6] loongarch-to-apply queue Song Gao 2025-10-09 12:35 ` [PULL 1/6] bios-tables-test-allowed-diff.h: Allow LoongArch DSDT.* Song Gao 2025-10-09 12:35 ` [PULL 2/6] hw/loongarch/virt: Align VIRT_GED_CPUHP_ADDR to 4 bytes Song Gao @ 2025-10-09 12:35 ` Song Gao 2025-10-09 12:35 ` [PULL 4/6] target/loongarch: Move TCG specified functions to tcg_cpu.c Song Gao ` (3 subsequent siblings) 6 siblings, 0 replies; 18+ messages in thread From: Song Gao @ 2025-10-09 12:35 UTC (permalink / raw) To: qemu-devel; +Cc: Huacai Chen, Michael S . Tsirkin From: Huacai Chen <chenhuacai@kernel.org> DSDT diffs from "iasl -d": @@ -11,7 +11,7 @@ * Signature "DSDT" * Length 0x000011FB (4603) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0x5D + * Checksum 0x5B * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) @@ -1426,11 +1426,11 @@ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { Memory32Fixed (ReadWrite, - 0x100E001F, // Address Base + 0x100E0020, // Address Base 0x0000000C, // Address Length ) }) - OperationRegion (PRST, SystemMemory, 0x100E001F, 0x0C) + OperationRegion (PRST, SystemMemory, 0x100E0020, 0x0C) Field (PRST, ByteAcc, NoLock, WriteAsZeros) { Offset (0x04), Signed-off-by: Huacai Chen <chenhuacai@kernel.org> Acked-by: Michael S. Tsirkin <mst@redhat.com> Message-ID: <20250923143542.2391576-4-chenhuacai@kernel.org> Signed-off-by: Song Gao <gaosong@loongson.cn> --- tests/data/acpi/loongarch64/virt/DSDT | Bin 4603 -> 4603 bytes tests/data/acpi/loongarch64/virt/DSDT.memhp | Bin 5824 -> 5824 bytes tests/data/acpi/loongarch64/virt/DSDT.numamem | Bin 4609 -> 4609 bytes .../data/acpi/loongarch64/virt/DSDT.topology | Bin 4905 -> 4905 bytes tests/qtest/bios-tables-test-allowed-diff.h | 4 ---- 5 files changed, 4 deletions(-) diff --git a/tests/data/acpi/loongarch64/virt/DSDT b/tests/data/acpi/loongarch64/virt/DSDT index b31841aec6ed296f10ea1695a67ead38f45424d5..55aa34f988d6ef69293e91c5fe45bee0a02bc5f1 100644 GIT binary patch delta 44 zcmeyZ{9BpJCD<k8w;%%pWAsL@BfP>2415AS3=9mF4ABh%LBSymJPMm1@=CD)02#3h APXGV_ delta 44 zcmeyZ{9BpJCD<k8w;%%pW9&w*BfP@$415AS3=9mF4ABh%LBSymJo1|#@=CD)02$8< APXGV_ diff --git a/tests/data/acpi/loongarch64/virt/DSDT.memhp b/tests/data/acpi/loongarch64/virt/DSDT.memhp index e291200fc91caa3d93dcd6ec4736f7340f5e3f65..c0955eb60448cc5f4d38d410abc260ae54ea2e9a 100644 GIT binary patch delta 44 zcmX@0dq9`VCD<k8fEWV<W5PzRW+7n(20j5E1_p*ohUkWXpx_V&9)-;dgcMi+`vnS0 delta 44 zcmX@0dq9`VCD<k8fEWV<W70;hW+7pD20j5E1_p*ohUkWXpx_V&9{J4+gcMi+`y&cU diff --git a/tests/data/acpi/loongarch64/virt/DSDT.numamem b/tests/data/acpi/loongarch64/virt/DSDT.numamem index 07923ac39584c5a5e73c9556d251814ce10de6cc..61e47e7252155dcf9c76879c4f60f4b3eef63f86 100644 GIT binary patch delta 44 zcmZovX;k5I33dr#6k=dte72G62(PdL1D^m70|P@PLv%wxP;dwXkHY4Myb3G;-$V)Z delta 44 zcmZovX;k5I33dr#6k=dte6f-12(Pd_1D^m70|P@PLv%wxP;dwXkNoC`yb3G;-(m^% diff --git a/tests/data/acpi/loongarch64/virt/DSDT.topology b/tests/data/acpi/loongarch64/virt/DSDT.topology index 6dfbb495f88b74b87849b58473e46717bc588a56..b2afebc938ce45d798c8aa5f45a463f1617e257e 100644 GIT binary patch delta 44 zcmZ3fwo;ADCD<iIQ<#B)@!UqPBfP>2415AS3=9mF4ABh%LBSymJPMm1@_MiW0PuGT Ag8%>k delta 44 zcmZ3fwo;ADCD<iIQ<#B)@xn%~BfP@$415AS3=9mF4ABh%LBSymJo1|#@_MiW0PvLx Ag8%>k diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h index 2ed837faee..dfb8523c8b 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1,5 +1 @@ /* List of comma-separated changed AML files to ignore */ -"tests/data/acpi/loongarch64/virt/DSDT", -"tests/data/acpi/loongarch64/virt/DSDT.memhp", -"tests/data/acpi/loongarch64/virt/DSDT.numamem", -"tests/data/acpi/loongarch64/virt/DSDT.topology", -- 2.47.0 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PULL 4/6] target/loongarch: Move TCG specified functions to tcg_cpu.c 2025-10-09 12:35 [PULL 0/6] loongarch-to-apply queue Song Gao ` (2 preceding siblings ...) 2025-10-09 12:35 ` [PULL 3/6] tests/data/acpi/loongarch64: Update expected DSDT.* Song Gao @ 2025-10-09 12:35 ` Song Gao 2025-10-09 12:36 ` [PULL 5/6] target/loongarch: Move function do_raise_exception() " Song Gao ` (2 subsequent siblings) 6 siblings, 0 replies; 18+ messages in thread From: Song Gao @ 2025-10-09 12:35 UTC (permalink / raw) To: qemu-devel; +Cc: Bibo Mao, Richard Henderson From: Bibo Mao <maobibo@loongson.cn> New file target/loongarch/tcg/tcg_cpu.c is created, and move TCG specified functions to here from file target/loongarch/cpu.c It is only code movement and there is no any function change. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250929035338.2320419-2-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn> --- target/loongarch/cpu.c | 262 +------------------------- target/loongarch/internals.h | 2 + target/loongarch/tcg/meson.build | 1 + target/loongarch/tcg/tcg_cpu.c | 266 +++++++++++++++++++++++++++ target/loongarch/tcg/tcg_loongarch.h | 1 + 5 files changed, 272 insertions(+), 260 deletions(-) create mode 100644 target/loongarch/tcg/tcg_cpu.c diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 993602fb8c..245c6d3ab9 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -28,11 +28,6 @@ #ifdef CONFIG_KVM #include <linux/kvm.h> #endif -#ifdef CONFIG_TCG -#include "accel/tcg/cpu-ldst.h" -#include "accel/tcg/cpu-ops.h" -#include "tcg/tcg.h" -#endif #include "tcg/tcg_loongarch.h" const char * const regnames[32] = { @@ -140,18 +135,8 @@ void loongarch_cpu_set_irq(void *opaque, int irq, int level) } } -static inline bool cpu_loongarch_hw_interrupts_enabled(CPULoongArchState *env) -{ - bool ret = 0; - - ret = (FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE) && - !(FIELD_EX64(env->CSR_DBG, CSR_DBG, DST))); - - return ret; -} - /* Check if there is pending and not masked out interrupt */ -static inline bool cpu_loongarch_hw_interrupts_pending(CPULoongArchState *env) +bool cpu_loongarch_hw_interrupts_pending(CPULoongArchState *env) { uint32_t pending; uint32_t status; @@ -163,217 +148,8 @@ static inline bool cpu_loongarch_hw_interrupts_pending(CPULoongArchState *env) } #endif -#ifdef CONFIG_TCG -#ifndef CONFIG_USER_ONLY -static void loongarch_cpu_do_interrupt(CPUState *cs) -{ - CPULoongArchState *env = cpu_env(cs); - bool update_badinstr = 1; - int cause = -1; - bool tlbfill = FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR); - uint32_t vec_size = FIELD_EX64(env->CSR_ECFG, CSR_ECFG, VS); - - if (cs->exception_index != EXCCODE_INT) { - qemu_log_mask(CPU_LOG_INT, - "%s enter: pc " TARGET_FMT_lx " ERA " TARGET_FMT_lx - " TLBRERA " TARGET_FMT_lx " exception: %d (%s)\n", - __func__, env->pc, env->CSR_ERA, env->CSR_TLBRERA, - cs->exception_index, - loongarch_exception_name(cs->exception_index)); - } - - switch (cs->exception_index) { - case EXCCODE_DBP: - env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DCL, 1); - env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, ECODE, 0xC); - goto set_DERA; - set_DERA: - env->CSR_DERA = env->pc; - env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DST, 1); - set_pc(env, env->CSR_EENTRY + 0x480); - break; - case EXCCODE_INT: - if (FIELD_EX64(env->CSR_DBG, CSR_DBG, DST)) { - env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DEI, 1); - goto set_DERA; - } - QEMU_FALLTHROUGH; - case EXCCODE_PIF: - case EXCCODE_ADEF: - cause = cs->exception_index; - update_badinstr = 0; - break; - case EXCCODE_SYS: - case EXCCODE_BRK: - case EXCCODE_INE: - case EXCCODE_IPE: - case EXCCODE_FPD: - case EXCCODE_FPE: - case EXCCODE_SXD: - case EXCCODE_ASXD: - env->CSR_BADV = env->pc; - QEMU_FALLTHROUGH; - case EXCCODE_BCE: - case EXCCODE_ADEM: - case EXCCODE_PIL: - case EXCCODE_PIS: - case EXCCODE_PME: - case EXCCODE_PNR: - case EXCCODE_PNX: - case EXCCODE_PPI: - cause = cs->exception_index; - break; - default: - qemu_log("Error: exception(%d) has not been supported\n", - cs->exception_index); - abort(); - } - - if (update_badinstr) { - env->CSR_BADI = cpu_ldl_code(env, env->pc); - } - - /* Save PLV and IE */ - if (tlbfill) { - env->CSR_TLBRPRMD = FIELD_DP64(env->CSR_TLBRPRMD, CSR_TLBRPRMD, PPLV, - FIELD_EX64(env->CSR_CRMD, - CSR_CRMD, PLV)); - env->CSR_TLBRPRMD = FIELD_DP64(env->CSR_TLBRPRMD, CSR_TLBRPRMD, PIE, - FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE)); - /* set the DA mode */ - env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DA, 1); - env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PG, 0); - env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, - PC, (env->pc >> 2)); - } else { - env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ECODE, - EXCODE_MCODE(cause)); - env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ESUBCODE, - EXCODE_SUBCODE(cause)); - env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PPLV, - FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV)); - env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PIE, - FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE)); - env->CSR_ERA = env->pc; - } - - env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PLV, 0); - env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, IE, 0); - - if (vec_size) { - vec_size = (1 << vec_size) * 4; - } - - if (cs->exception_index == EXCCODE_INT) { - /* Interrupt */ - uint32_t vector = 0; - uint32_t pending = FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS); - pending &= FIELD_EX64(env->CSR_ECFG, CSR_ECFG, LIE); - - /* Find the highest-priority interrupt. */ - vector = 31 - clz32(pending); - set_pc(env, env->CSR_EENTRY + \ - (EXCCODE_EXTERNAL_INT + vector) * vec_size); - qemu_log_mask(CPU_LOG_INT, - "%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx - " cause %d\n" " A " TARGET_FMT_lx " D " - TARGET_FMT_lx " vector = %d ExC " TARGET_FMT_lx "ExS" - TARGET_FMT_lx "\n", - __func__, env->pc, env->CSR_ERA, - cause, env->CSR_BADV, env->CSR_DERA, vector, - env->CSR_ECFG, env->CSR_ESTAT); - } else { - if (tlbfill) { - set_pc(env, env->CSR_TLBRENTRY); - } else { - set_pc(env, env->CSR_EENTRY + EXCODE_MCODE(cause) * vec_size); - } - qemu_log_mask(CPU_LOG_INT, - "%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx - " cause %d%s\n, ESTAT " TARGET_FMT_lx - " EXCFG " TARGET_FMT_lx " BADVA " TARGET_FMT_lx - "BADI " TARGET_FMT_lx " SYS_NUM " TARGET_FMT_lu - " cpu %d asid " TARGET_FMT_lx "\n", __func__, env->pc, - tlbfill ? env->CSR_TLBRERA : env->CSR_ERA, - cause, tlbfill ? "(refill)" : "", env->CSR_ESTAT, - env->CSR_ECFG, - tlbfill ? env->CSR_TLBRBADV : env->CSR_BADV, - env->CSR_BADI, env->gpr[11], cs->cpu_index, - env->CSR_ASID); - } - cs->exception_index = -1; -} - -static void loongarch_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, - vaddr addr, unsigned size, - MMUAccessType access_type, - int mmu_idx, MemTxAttrs attrs, - MemTxResult response, - uintptr_t retaddr) -{ - CPULoongArchState *env = cpu_env(cs); - - if (access_type == MMU_INST_FETCH) { - do_raise_exception(env, EXCCODE_ADEF, retaddr); - } else { - do_raise_exception(env, EXCCODE_ADEM, retaddr); - } -} - -static bool loongarch_cpu_exec_interrupt(CPUState *cs, int interrupt_request) -{ - if (interrupt_request & CPU_INTERRUPT_HARD) { - CPULoongArchState *env = cpu_env(cs); - - if (cpu_loongarch_hw_interrupts_enabled(env) && - cpu_loongarch_hw_interrupts_pending(env)) { - /* Raise it */ - cs->exception_index = EXCCODE_INT; - loongarch_cpu_do_interrupt(cs); - return true; - } - } - return false; -} - -static vaddr loongarch_pointer_wrap(CPUState *cs, int mmu_idx, - vaddr result, vaddr base) -{ - return is_va32(cpu_env(cs)) ? (uint32_t)result : result; -} -#endif - -static TCGTBCPUState loongarch_get_tb_cpu_state(CPUState *cs) -{ - CPULoongArchState *env = cpu_env(cs); - uint32_t flags; - - flags = env->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK); - flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, FPE) * HW_FLAGS_EUEN_FPE; - flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, SXE) * HW_FLAGS_EUEN_SXE; - flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, ASXE) * HW_FLAGS_EUEN_ASXE; - flags |= is_va32(env) * HW_FLAGS_VA32; - - return (TCGTBCPUState){ .pc = env->pc, .flags = flags }; -} - -static void loongarch_cpu_synchronize_from_tb(CPUState *cs, - const TranslationBlock *tb) -{ - tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL)); - set_pc(cpu_env(cs), tb->pc); -} - -static void loongarch_restore_state_to_opc(CPUState *cs, - const TranslationBlock *tb, - const uint64_t *data) -{ - set_pc(cpu_env(cs), data[0]); -} -#endif /* CONFIG_TCG */ - #ifndef CONFIG_USER_ONLY -static bool loongarch_cpu_has_work(CPUState *cs) +bool loongarch_cpu_has_work(CPUState *cs) { bool has_work = false; @@ -386,16 +162,6 @@ static bool loongarch_cpu_has_work(CPUState *cs) } #endif /* !CONFIG_USER_ONLY */ -static int loongarch_cpu_mmu_index(CPUState *cs, bool ifetch) -{ - CPULoongArchState *env = cpu_env(cs); - - if (FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PG)) { - return FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV); - } - return MMU_DA_IDX; -} - static void loongarch_la464_init_csr(Object *obj) { #ifndef CONFIG_USER_ONLY @@ -911,30 +677,6 @@ static void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags) } } -#ifdef CONFIG_TCG -static const TCGCPUOps loongarch_tcg_ops = { - .guest_default_memory_order = 0, - .mttcg_supported = true, - - .initialize = loongarch_translate_init, - .translate_code = loongarch_translate_code, - .get_tb_cpu_state = loongarch_get_tb_cpu_state, - .synchronize_from_tb = loongarch_cpu_synchronize_from_tb, - .restore_state_to_opc = loongarch_restore_state_to_opc, - .mmu_index = loongarch_cpu_mmu_index, - -#ifndef CONFIG_USER_ONLY - .tlb_fill = loongarch_cpu_tlb_fill, - .pointer_wrap = loongarch_pointer_wrap, - .cpu_exec_interrupt = loongarch_cpu_exec_interrupt, - .cpu_exec_halt = loongarch_cpu_has_work, - .cpu_exec_reset = cpu_reset, - .do_interrupt = loongarch_cpu_do_interrupt, - .do_transaction_failed = loongarch_cpu_do_transaction_failed, -#endif -}; -#endif /* CONFIG_TCG */ - #ifndef CONFIG_USER_ONLY #include "hw/core/sysemu-cpu-ops.h" diff --git a/target/loongarch/internals.h b/target/loongarch/internals.h index e50d109767..e994f5a3d3 100644 --- a/target/loongarch/internals.h +++ b/target/loongarch/internals.h @@ -41,6 +41,8 @@ uint64_t cpu_loongarch_get_constant_timer_counter(LoongArchCPU *cpu); uint64_t cpu_loongarch_get_constant_timer_ticks(LoongArchCPU *cpu); void cpu_loongarch_store_constant_timer_config(LoongArchCPU *cpu, uint64_t value); +bool loongarch_cpu_has_work(CPUState *cs); +bool cpu_loongarch_hw_interrupts_pending(CPULoongArchState *env); #endif /* !CONFIG_USER_ONLY */ uint64_t read_fcc(CPULoongArchState *env); diff --git a/target/loongarch/tcg/meson.build b/target/loongarch/tcg/meson.build index bdf34f9673..b7adfe46f1 100644 --- a/target/loongarch/tcg/meson.build +++ b/target/loongarch/tcg/meson.build @@ -7,6 +7,7 @@ loongarch_ss.add([zlib, gen]) loongarch_ss.add(files( 'fpu_helper.c', 'op_helper.c', + 'tcg_cpu.c', 'translate.c', 'vec_helper.c', )) diff --git a/target/loongarch/tcg/tcg_cpu.c b/target/loongarch/tcg/tcg_cpu.c new file mode 100644 index 0000000000..c7f49838e3 --- /dev/null +++ b/target/loongarch/tcg/tcg_cpu.c @@ -0,0 +1,266 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * LoongArch CPU parameters for QEMU. + * + * Copyright (c) 2025 Loongson Technology Corporation Limited + */ +#include "qemu/osdep.h" +#include "qemu/accel.h" +#include "qemu/error-report.h" +#include "qemu/log.h" +#include "accel/accel-cpu-target.h" +#include "accel/tcg/cpu-ldst.h" +#include "accel/tcg/cpu-ops.h" +#include "exec/translation-block.h" +#include "exec/target_page.h" +#include "tcg_loongarch.h" +#include "internals.h" + +#ifndef CONFIG_USER_ONLY +static void loongarch_cpu_do_interrupt(CPUState *cs) +{ + CPULoongArchState *env = cpu_env(cs); + bool update_badinstr = 1; + int cause = -1; + bool tlbfill = FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR); + uint32_t vec_size = FIELD_EX64(env->CSR_ECFG, CSR_ECFG, VS); + + if (cs->exception_index != EXCCODE_INT) { + qemu_log_mask(CPU_LOG_INT, + "%s enter: pc " TARGET_FMT_lx " ERA " TARGET_FMT_lx + " TLBRERA " TARGET_FMT_lx " exception: %d (%s)\n", + __func__, env->pc, env->CSR_ERA, env->CSR_TLBRERA, + cs->exception_index, + loongarch_exception_name(cs->exception_index)); + } + + switch (cs->exception_index) { + case EXCCODE_DBP: + env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DCL, 1); + env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, ECODE, 0xC); + goto set_DERA; + set_DERA: + env->CSR_DERA = env->pc; + env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DST, 1); + set_pc(env, env->CSR_EENTRY + 0x480); + break; + case EXCCODE_INT: + if (FIELD_EX64(env->CSR_DBG, CSR_DBG, DST)) { + env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DEI, 1); + goto set_DERA; + } + QEMU_FALLTHROUGH; + case EXCCODE_PIF: + case EXCCODE_ADEF: + cause = cs->exception_index; + update_badinstr = 0; + break; + case EXCCODE_SYS: + case EXCCODE_BRK: + case EXCCODE_INE: + case EXCCODE_IPE: + case EXCCODE_FPD: + case EXCCODE_FPE: + case EXCCODE_SXD: + case EXCCODE_ASXD: + env->CSR_BADV = env->pc; + QEMU_FALLTHROUGH; + case EXCCODE_BCE: + case EXCCODE_ADEM: + case EXCCODE_PIL: + case EXCCODE_PIS: + case EXCCODE_PME: + case EXCCODE_PNR: + case EXCCODE_PNX: + case EXCCODE_PPI: + cause = cs->exception_index; + break; + default: + qemu_log("Error: exception(%d) has not been supported\n", + cs->exception_index); + abort(); + } + + if (update_badinstr) { + env->CSR_BADI = cpu_ldl_code(env, env->pc); + } + + /* Save PLV and IE */ + if (tlbfill) { + env->CSR_TLBRPRMD = FIELD_DP64(env->CSR_TLBRPRMD, CSR_TLBRPRMD, PPLV, + FIELD_EX64(env->CSR_CRMD, + CSR_CRMD, PLV)); + env->CSR_TLBRPRMD = FIELD_DP64(env->CSR_TLBRPRMD, CSR_TLBRPRMD, PIE, + FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE)); + /* set the DA mode */ + env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DA, 1); + env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PG, 0); + env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, + PC, (env->pc >> 2)); + } else { + env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ECODE, + EXCODE_MCODE(cause)); + env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ESUBCODE, + EXCODE_SUBCODE(cause)); + env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PPLV, + FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV)); + env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PIE, + FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE)); + env->CSR_ERA = env->pc; + } + + env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PLV, 0); + env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, IE, 0); + + if (vec_size) { + vec_size = (1 << vec_size) * 4; + } + + if (cs->exception_index == EXCCODE_INT) { + /* Interrupt */ + uint32_t vector = 0; + uint32_t pending = FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS); + pending &= FIELD_EX64(env->CSR_ECFG, CSR_ECFG, LIE); + + /* Find the highest-priority interrupt. */ + vector = 31 - clz32(pending); + set_pc(env, env->CSR_EENTRY + \ + (EXCCODE_EXTERNAL_INT + vector) * vec_size); + qemu_log_mask(CPU_LOG_INT, + "%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx + " cause %d\n" " A " TARGET_FMT_lx " D " + TARGET_FMT_lx " vector = %d ExC " TARGET_FMT_lx "ExS" + TARGET_FMT_lx "\n", + __func__, env->pc, env->CSR_ERA, + cause, env->CSR_BADV, env->CSR_DERA, vector, + env->CSR_ECFG, env->CSR_ESTAT); + } else { + if (tlbfill) { + set_pc(env, env->CSR_TLBRENTRY); + } else { + set_pc(env, env->CSR_EENTRY + EXCODE_MCODE(cause) * vec_size); + } + qemu_log_mask(CPU_LOG_INT, + "%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx + " cause %d%s\n, ESTAT " TARGET_FMT_lx + " EXCFG " TARGET_FMT_lx " BADVA " TARGET_FMT_lx + "BADI " TARGET_FMT_lx " SYS_NUM " TARGET_FMT_lu + " cpu %d asid " TARGET_FMT_lx "\n", __func__, env->pc, + tlbfill ? env->CSR_TLBRERA : env->CSR_ERA, + cause, tlbfill ? "(refill)" : "", env->CSR_ESTAT, + env->CSR_ECFG, + tlbfill ? env->CSR_TLBRBADV : env->CSR_BADV, + env->CSR_BADI, env->gpr[11], cs->cpu_index, + env->CSR_ASID); + } + cs->exception_index = -1; +} + +static void loongarch_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, + vaddr addr, unsigned size, + MMUAccessType access_type, + int mmu_idx, MemTxAttrs attrs, + MemTxResult response, + uintptr_t retaddr) +{ + CPULoongArchState *env = cpu_env(cs); + + if (access_type == MMU_INST_FETCH) { + do_raise_exception(env, EXCCODE_ADEF, retaddr); + } else { + do_raise_exception(env, EXCCODE_ADEM, retaddr); + } +} + +static inline bool cpu_loongarch_hw_interrupts_enabled(CPULoongArchState *env) +{ + bool ret = 0; + + ret = (FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE) && + !(FIELD_EX64(env->CSR_DBG, CSR_DBG, DST))); + + return ret; +} + +static bool loongarch_cpu_exec_interrupt(CPUState *cs, int interrupt_request) +{ + if (interrupt_request & CPU_INTERRUPT_HARD) { + CPULoongArchState *env = cpu_env(cs); + + if (cpu_loongarch_hw_interrupts_enabled(env) && + cpu_loongarch_hw_interrupts_pending(env)) { + /* Raise it */ + cs->exception_index = EXCCODE_INT; + loongarch_cpu_do_interrupt(cs); + return true; + } + } + return false; +} + +static vaddr loongarch_pointer_wrap(CPUState *cs, int mmu_idx, + vaddr result, vaddr base) +{ + return is_va32(cpu_env(cs)) ? (uint32_t)result : result; +} +#endif + +static TCGTBCPUState loongarch_get_tb_cpu_state(CPUState *cs) +{ + CPULoongArchState *env = cpu_env(cs); + uint32_t flags; + + flags = env->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK); + flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, FPE) * HW_FLAGS_EUEN_FPE; + flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, SXE) * HW_FLAGS_EUEN_SXE; + flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, ASXE) * HW_FLAGS_EUEN_ASXE; + flags |= is_va32(env) * HW_FLAGS_VA32; + + return (TCGTBCPUState){ .pc = env->pc, .flags = flags }; +} + +static void loongarch_cpu_synchronize_from_tb(CPUState *cs, + const TranslationBlock *tb) +{ + tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL)); + set_pc(cpu_env(cs), tb->pc); +} + +static void loongarch_restore_state_to_opc(CPUState *cs, + const TranslationBlock *tb, + const uint64_t *data) +{ + set_pc(cpu_env(cs), data[0]); +} + +static int loongarch_cpu_mmu_index(CPUState *cs, bool ifetch) +{ + CPULoongArchState *env = cpu_env(cs); + + if (FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PG)) { + return FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV); + } + return MMU_DA_IDX; +} + +const TCGCPUOps loongarch_tcg_ops = { + .guest_default_memory_order = 0, + .mttcg_supported = true, + + .initialize = loongarch_translate_init, + .translate_code = loongarch_translate_code, + .get_tb_cpu_state = loongarch_get_tb_cpu_state, + .synchronize_from_tb = loongarch_cpu_synchronize_from_tb, + .restore_state_to_opc = loongarch_restore_state_to_opc, + .mmu_index = loongarch_cpu_mmu_index, + +#ifndef CONFIG_USER_ONLY + .tlb_fill = loongarch_cpu_tlb_fill, + .pointer_wrap = loongarch_pointer_wrap, + .cpu_exec_interrupt = loongarch_cpu_exec_interrupt, + .cpu_exec_halt = loongarch_cpu_has_work, + .cpu_exec_reset = cpu_reset, + .do_interrupt = loongarch_cpu_do_interrupt, + .do_transaction_failed = loongarch_cpu_do_transaction_failed, +#endif +}; diff --git a/target/loongarch/tcg/tcg_loongarch.h b/target/loongarch/tcg/tcg_loongarch.h index 47702893e3..7fb627f2d6 100644 --- a/target/loongarch/tcg/tcg_loongarch.h +++ b/target/loongarch/tcg/tcg_loongarch.h @@ -9,6 +9,7 @@ #include "cpu.h" #include "cpu-mmu.h" +extern const TCGCPUOps loongarch_tcg_ops; void loongarch_csr_translate_init(void); bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr address, int size, -- 2.47.0 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PULL 5/6] target/loongarch: Move function do_raise_exception() to tcg_cpu.c 2025-10-09 12:35 [PULL 0/6] loongarch-to-apply queue Song Gao ` (3 preceding siblings ...) 2025-10-09 12:35 ` [PULL 4/6] target/loongarch: Move TCG specified functions to tcg_cpu.c Song Gao @ 2025-10-09 12:36 ` Song Gao 2025-10-09 12:36 ` [PULL 6/6] target/loongarch: Define loongarch_exception_name() as static Song Gao 2025-10-09 16:23 ` [PULL 0/6] loongarch-to-apply queue Richard Henderson 6 siblings, 0 replies; 18+ messages in thread From: Song Gao @ 2025-10-09 12:36 UTC (permalink / raw) To: qemu-devel; +Cc: Bibo Mao, Richard Henderson From: Bibo Mao <maobibo@loongson.cn> Function do_raise_exception() is specified with TCG mode, so move it to file target/loongarch/tcg/tcg_cpu.c It is only code movement and there is no any function change. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250929035338.2320419-3-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn> --- target/loongarch/cpu.c | 56 ---------------------------------- target/loongarch/tcg/tcg_cpu.c | 56 ++++++++++++++++++++++++++++++++++ 2 files changed, 56 insertions(+), 56 deletions(-) diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 245c6d3ab9..86490e0f72 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -44,62 +44,6 @@ const char * const fregnames[32] = { "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", }; -struct TypeExcp { - int32_t exccode; - const char * const name; -}; - -static const struct TypeExcp excp_names[] = { - {EXCCODE_INT, "Interrupt"}, - {EXCCODE_PIL, "Page invalid exception for load"}, - {EXCCODE_PIS, "Page invalid exception for store"}, - {EXCCODE_PIF, "Page invalid exception for fetch"}, - {EXCCODE_PME, "Page modified exception"}, - {EXCCODE_PNR, "Page Not Readable exception"}, - {EXCCODE_PNX, "Page Not Executable exception"}, - {EXCCODE_PPI, "Page Privilege error"}, - {EXCCODE_ADEF, "Address error for instruction fetch"}, - {EXCCODE_ADEM, "Address error for Memory access"}, - {EXCCODE_SYS, "Syscall"}, - {EXCCODE_BRK, "Break"}, - {EXCCODE_INE, "Instruction Non-Existent"}, - {EXCCODE_IPE, "Instruction privilege error"}, - {EXCCODE_FPD, "Floating Point Disabled"}, - {EXCCODE_FPE, "Floating Point Exception"}, - {EXCCODE_DBP, "Debug breakpoint"}, - {EXCCODE_BCE, "Bound Check Exception"}, - {EXCCODE_SXD, "128 bit vector instructions Disable exception"}, - {EXCCODE_ASXD, "256 bit vector instructions Disable exception"}, - {EXCP_HLT, "EXCP_HLT"}, -}; - -const char *loongarch_exception_name(int32_t exception) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(excp_names); i++) { - if (excp_names[i].exccode == exception) { - return excp_names[i].name; - } - } - return "Unknown"; -} - -void G_NORETURN do_raise_exception(CPULoongArchState *env, - uint32_t exception, - uintptr_t pc) -{ - CPUState *cs = env_cpu(env); - - qemu_log_mask(CPU_LOG_INT, "%s: exception: %d (%s)\n", - __func__, - exception, - loongarch_exception_name(exception)); - cs->exception_index = exception; - - cpu_loop_exit_restore(cs, pc); -} - static void loongarch_cpu_set_pc(CPUState *cs, vaddr value) { set_pc(cpu_env(cs), value); diff --git a/target/loongarch/tcg/tcg_cpu.c b/target/loongarch/tcg/tcg_cpu.c index c7f49838e3..59b5800ecf 100644 --- a/target/loongarch/tcg/tcg_cpu.c +++ b/target/loongarch/tcg/tcg_cpu.c @@ -16,6 +16,62 @@ #include "tcg_loongarch.h" #include "internals.h" +struct TypeExcp { + int32_t exccode; + const char * const name; +}; + +static const struct TypeExcp excp_names[] = { + {EXCCODE_INT, "Interrupt"}, + {EXCCODE_PIL, "Page invalid exception for load"}, + {EXCCODE_PIS, "Page invalid exception for store"}, + {EXCCODE_PIF, "Page invalid exception for fetch"}, + {EXCCODE_PME, "Page modified exception"}, + {EXCCODE_PNR, "Page Not Readable exception"}, + {EXCCODE_PNX, "Page Not Executable exception"}, + {EXCCODE_PPI, "Page Privilege error"}, + {EXCCODE_ADEF, "Address error for instruction fetch"}, + {EXCCODE_ADEM, "Address error for Memory access"}, + {EXCCODE_SYS, "Syscall"}, + {EXCCODE_BRK, "Break"}, + {EXCCODE_INE, "Instruction Non-Existent"}, + {EXCCODE_IPE, "Instruction privilege error"}, + {EXCCODE_FPD, "Floating Point Disabled"}, + {EXCCODE_FPE, "Floating Point Exception"}, + {EXCCODE_DBP, "Debug breakpoint"}, + {EXCCODE_BCE, "Bound Check Exception"}, + {EXCCODE_SXD, "128 bit vector instructions Disable exception"}, + {EXCCODE_ASXD, "256 bit vector instructions Disable exception"}, + {EXCP_HLT, "EXCP_HLT"}, +}; + +const char *loongarch_exception_name(int32_t exception) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(excp_names); i++) { + if (excp_names[i].exccode == exception) { + return excp_names[i].name; + } + } + return "Unknown"; +} + +void G_NORETURN do_raise_exception(CPULoongArchState *env, + uint32_t exception, + uintptr_t pc) +{ + CPUState *cs = env_cpu(env); + + qemu_log_mask(CPU_LOG_INT, "%s: exception: %d (%s)\n", + __func__, + exception, + loongarch_exception_name(exception)); + cs->exception_index = exception; + + cpu_loop_exit_restore(cs, pc); +} + #ifndef CONFIG_USER_ONLY static void loongarch_cpu_do_interrupt(CPUState *cs) { -- 2.47.0 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PULL 6/6] target/loongarch: Define loongarch_exception_name() as static 2025-10-09 12:35 [PULL 0/6] loongarch-to-apply queue Song Gao ` (4 preceding siblings ...) 2025-10-09 12:36 ` [PULL 5/6] target/loongarch: Move function do_raise_exception() " Song Gao @ 2025-10-09 12:36 ` Song Gao 2025-10-09 16:23 ` [PULL 0/6] loongarch-to-apply queue Richard Henderson 6 siblings, 0 replies; 18+ messages in thread From: Song Gao @ 2025-10-09 12:36 UTC (permalink / raw) To: qemu-devel; +Cc: Bibo Mao, Richard Henderson From: Bibo Mao <maobibo@loongson.cn> Function loongarch_exception_name() is only called in defined file target/loongarch/tcg/tcg_cpu.c, set this function as static. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250929035338.2320419-4-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn> --- target/loongarch/internals.h | 2 -- target/loongarch/tcg/tcg_cpu.c | 2 +- 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/target/loongarch/internals.h b/target/loongarch/internals.h index e994f5a3d3..8793bd9df6 100644 --- a/target/loongarch/internals.h +++ b/target/loongarch/internals.h @@ -24,8 +24,6 @@ void G_NORETURN do_raise_exception(CPULoongArchState *env, uint32_t exception, uintptr_t pc); -const char *loongarch_exception_name(int32_t exception); - #ifdef CONFIG_TCG int ieee_ex_to_loongarch(int xcpt); void restore_fp_status(CPULoongArchState *env); diff --git a/target/loongarch/tcg/tcg_cpu.c b/target/loongarch/tcg/tcg_cpu.c index 59b5800ecf..82b54e6dc3 100644 --- a/target/loongarch/tcg/tcg_cpu.c +++ b/target/loongarch/tcg/tcg_cpu.c @@ -45,7 +45,7 @@ static const struct TypeExcp excp_names[] = { {EXCP_HLT, "EXCP_HLT"}, }; -const char *loongarch_exception_name(int32_t exception) +static const char *loongarch_exception_name(int32_t exception) { int i; -- 2.47.0 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PULL 0/6] loongarch-to-apply queue 2025-10-09 12:35 [PULL 0/6] loongarch-to-apply queue Song Gao ` (5 preceding siblings ...) 2025-10-09 12:36 ` [PULL 6/6] target/loongarch: Define loongarch_exception_name() as static Song Gao @ 2025-10-09 16:23 ` Richard Henderson 6 siblings, 0 replies; 18+ messages in thread From: Richard Henderson @ 2025-10-09 16:23 UTC (permalink / raw) To: qemu-devel On 10/9/25 05:35, Song Gao wrote: > The following changes since commit 37ad0e48e9fd58b170abbf31c18a994346f62ed7: > > Merge tag 'pull-10.2-maintainer-071025-1' ofhttps://gitlab.com/stsquad/qemu into staging (2025-10-07 08:46:28 -0700) > > are available in the Git repository at: > > https://github.com/gaosong715/qemu.git tags/pull-loongarch-20251009 > > for you to fetch changes up to fa6af7f6bf6dbc4c83595905d2572ad86358aa67: > > target/loongarch: Define loongarch_exception_name() as static (2025-10-09 19:11:37 +0800) > > ---------------------------------------------------------------- > pull-loongarch-20251009 Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/10.2 as appropriate. r~ ^ permalink raw reply [flat|nested] 18+ messages in thread
* [PULL 0/6] loongarch-to-apply queue
@ 2025-02-12 3:16 Bibo Mao
2025-02-12 17:39 ` Stefan Hajnoczi
0 siblings, 1 reply; 18+ messages in thread
From: Bibo Mao @ 2025-02-12 3:16 UTC (permalink / raw)
To: Stefan Hajnoczi; +Cc: qemu-devel, Song Gao
The following changes since commit ffaf7f0376f8040ce9068d71ae9ae8722505c42e:
Merge tag 'pull-10.0-testing-and-gdstub-updates-100225-1' of https://gitlab.com/stsquad/qemu into staging (2025-02-10 13:26:17 -0500)
are available in the Git repository at:
https://gitlab.com/bibo-mao/qemu.git tags/pull-loongarch-20250212
for you to fetch changes up to 456739ce4347c21b6fa2ec1b6585bc4a6504446f:
hw/loongarch/virt: CPU irq line connection improvement (2025-02-12 10:05:22 +0800)
----------------------------------------------------------------
pull-loongarch-20250212 queue
----------------------------------------------------------------
Bibo Mao (6):
hw/loongarch/virt: Rename filename acpi-build with virt-acpi-build
hw/loongarch/virt: Rename function prefix name
hw/loongarch/virt: Add separate file for fdt building
hw/loongarch/virt: Set iocsr address space when CPU is created
hw/loongarch/virt: Remove unused ipistate
hw/loongarch/virt: CPU irq line connection improvement
hw/loongarch/meson.build | 6 +-
hw/loongarch/{acpi-build.c => virt-acpi-build.c} | 6 +-
hw/loongarch/virt-fdt-build.c | 535 ++++++++++++++++++++
hw/loongarch/virt.c | 593 ++---------------------
include/hw/loongarch/virt.h | 5 +-
target/loongarch/cpu.h | 2 -
6 files changed, 584 insertions(+), 563 deletions(-)
rename hw/loongarch/{acpi-build.c => virt-acpi-build.c} (99%)
create mode 100644 hw/loongarch/virt-fdt-build.c
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PULL 0/6] loongarch-to-apply queue 2025-02-12 3:16 Bibo Mao @ 2025-02-12 17:39 ` Stefan Hajnoczi 0 siblings, 0 replies; 18+ messages in thread From: Stefan Hajnoczi @ 2025-02-12 17:39 UTC (permalink / raw) To: Bibo Mao; +Cc: Stefan Hajnoczi, qemu-devel, Song Gao [-- Attachment #1: Type: text/plain, Size: 116 bytes --] Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/10.0 for any user-visible changes. [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 488 bytes --] ^ permalink raw reply [flat|nested] 18+ messages in thread
* [PULL 0/6] loongarch-to-apply queue
@ 2025-01-09 6:57 Bibo Mao
2025-01-09 16:32 ` Stefan Hajnoczi
0 siblings, 1 reply; 18+ messages in thread
From: Bibo Mao @ 2025-01-09 6:57 UTC (permalink / raw)
To: Stefan Hajnoczi; +Cc: qemu-devel, Song Gao
The following changes since commit 3f8bcbba3b320c610689576fc47595f1076198dd:
Merge tag 'pull-request-2025-01-08' of https://gitlab.com/thuth/qemu into staging (2025-01-08 11:38:21 -0500)
are available in the Git repository at:
https://gitlab.com/bibo-mao/qemu.git tags/pull-loongarch-20250109
for you to fetch changes up to c3afa714bcea4c8b014fec99881bd0bdbe8262b8:
hw/intc/loongarch_extioi: Add irq routing support from physical id (2025-01-09 14:13:41 +0800)
----------------------------------------------------------------
pull-loongarch-20250109
----------------------------------------------------------------
Bibo Mao (4):
target/loongarch: Only support 64bit pte width
hw/intc/loongarch_extioi: Get cpu number from possible_cpu_arch_ids
hw/intc/loongarch_extioi: Remove num-cpu property
hw/intc/loongarch_extioi: Add irq routing support from physical id
Jiaxun Yang (2):
hw/core/loader: Use ssize_t for efi zboot unpacker
hw/loongarch/boot: Support Linux raw boot image
hw/arm/boot.c | 2 +-
hw/core/loader.c | 4 +-
hw/intc/loongarch_extioi.c | 36 +++++++----
hw/intc/loongarch_extioi_common.c | 18 +++++-
hw/loongarch/boot.c | 69 ++++++++++++++++++++++
hw/loongarch/virt.c | 1 -
include/hw/intc/loongarch_extioi_common.h | 2 +
include/hw/loader.h | 2 +-
target/loongarch/helper.h | 1 +
target/loongarch/tcg/csr_helper.c | 21 +++++++
.../tcg/insn_trans/trans_privileged.c.inc | 2 +-
target/loongarch/tcg/tlb_helper.c | 17 +-----
12 files changed, 142 insertions(+), 33 deletions(-)
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PULL 0/6] loongarch-to-apply queue 2025-01-09 6:57 Bibo Mao @ 2025-01-09 16:32 ` Stefan Hajnoczi 0 siblings, 0 replies; 18+ messages in thread From: Stefan Hajnoczi @ 2025-01-09 16:32 UTC (permalink / raw) To: Bibo Mao; +Cc: Stefan Hajnoczi, qemu-devel, Song Gao [-- Attachment #1: Type: text/plain, Size: 116 bytes --] Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/10.0 for any user-visible changes. [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 488 bytes --] ^ permalink raw reply [flat|nested] 18+ messages in thread
* [PULL 0/6] loongarch-to-apply queue
@ 2024-12-25 2:40 Bibo Mao
0 siblings, 0 replies; 18+ messages in thread
From: Bibo Mao @ 2024-12-25 2:40 UTC (permalink / raw)
To: Stefan Hajnoczi; +Cc: qemu-devel, Song Gao
The following changes since commit aa3a285b5bc56a4208b3b57d4a55291e9c260107:
Merge tag 'mem-2024-12-21' of https://github.com/davidhildenbrand/qemu into staging (2024-12-22 14:33:27 -0500)
are available in the Git repository at:
https://gitlab.com/bibo-mao/qemu.git tags/pull-loongarch-20241225
for you to fetch changes up to cb91b7108cb0b3781de9a00994fe78b631d80012:
target/loongarch: Use auto method with LASX feature (2024-12-25 10:33:20 +0800)
----------------------------------------------------------------
pull-loongarch-20241225
----------------------------------------------------------------
Bibo Mao (5):
target/loongarch: Use actual operand size with vbsrl check
hw/loongarch/virt: Create fdt table on machine creation done notification
hw/loongarch/virt: Improve fdt table creation for CPU object
target/loongarch: Use auto method with LSX feature
target/loongarch: Use auto method with LASX feature
ghy (1):
target/loongarch: Fix vldi inst
hw/loongarch/virt.c | 142 ++++++++++++++----------
target/loongarch/cpu.c | 86 ++++++++------
target/loongarch/cpu.h | 4 +
target/loongarch/kvm/kvm.c | 107 ++++++++++++++++++
target/loongarch/tcg/insn_trans/trans_vec.c.inc | 4 +-
5 files changed, 249 insertions(+), 94 deletions(-)
^ permalink raw reply [flat|nested] 18+ messages in thread* [PULL 0/6] loongarch-to-apply queue
@ 2024-10-24 9:26 Song Gao
2024-10-25 18:11 ` Peter Maydell
0 siblings, 1 reply; 18+ messages in thread
From: Song Gao @ 2024-10-24 9:26 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
The following changes since commit 6f625ce2f21d6a1243065d236298277c56f972d5:
Merge tag 'pull-request-2024-10-21' of https://gitlab.com/thuth/qemu into staging (2024-10-21 17:12:59 +0100)
are available in the Git repository at:
https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20241024
for you to fetch changes up to c44e0d6ba280dcc6bdf4ed555020c61d564b526c:
target/loongarch: Add steal time support on migration (2024-10-24 17:27:55 +0800)
----------------------------------------------------------------
pull-loongarch-20241024
----------------------------------------------------------------
Bibo Mao (6):
target/loongarch: Add loongson binary translation feature
target/loongarch: Implement lbt registers save/restore function
target/loongarch/kvm: Implement LoongArch PMU extension
linux-headers: loongarch: Add kvm_para.h and unistd_64.h
linux-headers: Update to Linux v6.12-rc3
target/loongarch: Add steal time support on migration
include/standard-headers/drm/drm_fourcc.h | 43 +++
include/standard-headers/linux/const.h | 17 ++
include/standard-headers/linux/ethtool.h | 226 +++++++++++++++
include/standard-headers/linux/fuse.h | 22 +-
include/standard-headers/linux/input-event-codes.h | 2 +
include/standard-headers/linux/pci_regs.h | 41 ++-
include/standard-headers/linux/virtio_balloon.h | 16 +-
include/standard-headers/linux/virtio_gpu.h | 1 +
linux-headers/asm-arm64/mman.h | 9 +
linux-headers/asm-arm64/unistd.h | 25 +-
linux-headers/asm-generic/unistd.h | 6 +-
linux-headers/asm-loongarch/kvm.h | 24 ++
linux-headers/asm-loongarch/kvm_para.h | 21 ++
linux-headers/asm-loongarch/unistd.h | 4 +-
linux-headers/asm-loongarch/unistd_64.h | 320 +++++++++++++++++++++
linux-headers/asm-riscv/kvm.h | 7 +
linux-headers/asm-riscv/unistd.h | 41 +--
linux-headers/asm-x86/kvm.h | 2 +
linux-headers/asm-x86/unistd_64.h | 1 +
linux-headers/asm-x86/unistd_x32.h | 1 +
linux-headers/linux/bits.h | 3 +
linux-headers/linux/const.h | 17 ++
linux-headers/linux/iommufd.h | 143 +++++++--
linux-headers/linux/kvm.h | 23 +-
linux-headers/linux/mman.h | 1 +
linux-headers/linux/psp-sev.h | 28 ++
scripts/update-linux-headers.sh | 4 +
target/loongarch/cpu.c | 43 +++
target/loongarch/cpu.h | 23 ++
target/loongarch/kvm/kvm.c | 225 ++++++++++++++-
target/loongarch/loongarch-qmp-cmds.c | 2 +-
target/loongarch/machine.c | 30 +-
32 files changed, 1274 insertions(+), 97 deletions(-)
create mode 100644 linux-headers/asm-loongarch/kvm_para.h
create mode 100644 linux-headers/asm-loongarch/unistd_64.h
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PULL 0/6] loongarch-to-apply queue 2024-10-24 9:26 Song Gao @ 2024-10-25 18:11 ` Peter Maydell 2024-10-26 7:23 ` bibo mao 0 siblings, 1 reply; 18+ messages in thread From: Peter Maydell @ 2024-10-25 18:11 UTC (permalink / raw) To: Song Gao; +Cc: qemu-devel On Thu, 24 Oct 2024 at 10:44, Song Gao <gaosong@loongson.cn> wrote: > > The following changes since commit 6f625ce2f21d6a1243065d236298277c56f972d5: > > Merge tag 'pull-request-2024-10-21' of https://gitlab.com/thuth/qemu into staging (2024-10-21 17:12:59 +0100) > > are available in the Git repository at: > > https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20241024 > > for you to fetch changes up to c44e0d6ba280dcc6bdf4ed555020c61d564b526c: > > target/loongarch: Add steal time support on migration (2024-10-24 17:27:55 +0800) > > ---------------------------------------------------------------- > pull-loongarch-20241024 > > ---------------------------------------------------------------- > Bibo Mao (6): > target/loongarch: Add loongson binary translation feature > target/loongarch: Implement lbt registers save/restore function > target/loongarch/kvm: Implement LoongArch PMU extension > linux-headers: loongarch: Add kvm_para.h and unistd_64.h > linux-headers: Update to Linux v6.12-rc3 > target/loongarch: Add steal time support on migration Hi; this fails to build on all the aarch64 jobs (both normal and cross-compile): https://gitlab.com/qemu-project/qemu/-/jobs/8190899599 https://gitlab.com/qemu-project/qemu/-/jobs/8190899331 In file included from /usr/include/aarch64-linux-gnu/sys/syscall.h:24, from ../util/oslib-posix.c:48: linux-headers/asm/unistd.h:2:10: fatal error: asm/unistd_64.h: No such file or directory 2 | #include <asm/unistd_64.h> | ^~~~~~~~~~~~~~~~~ thanks -- PMM ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PULL 0/6] loongarch-to-apply queue 2024-10-25 18:11 ` Peter Maydell @ 2024-10-26 7:23 ` bibo mao 0 siblings, 0 replies; 18+ messages in thread From: bibo mao @ 2024-10-26 7:23 UTC (permalink / raw) To: Peter Maydell; +Cc: Song Gao, qemu-devel Peter Maydell <peter.maydell@linaro.org> 于2024年10月26日周六 02:12写道： > > On Thu, 24 Oct 2024 at 10:44, Song Gao <gaosong@loongson.cn> wrote: > > > > The following changes since commit 6f625ce2f21d6a1243065d236298277c56f972d5: > > > > Merge tag 'pull-request-2024-10-21' of https://gitlab.com/thuth/qemu into staging (2024-10-21 17:12:59 +0100) > > > > are available in the Git repository at: > > > > https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20241024 > > > > for you to fetch changes up to c44e0d6ba280dcc6bdf4ed555020c61d564b526c: > > > > target/loongarch: Add steal time support on migration (2024-10-24 17:27:55 +0800) > > > > ---------------------------------------------------------------- > > pull-loongarch-20241024 > > > > ---------------------------------------------------------------- > > Bibo Mao (6): > > target/loongarch: Add loongson binary translation feature > > target/loongarch: Implement lbt registers save/restore function > > target/loongarch/kvm: Implement LoongArch PMU extension > > linux-headers: loongarch: Add kvm_para.h and unistd_64.h > > linux-headers: Update to Linux v6.12-rc3 > > target/loongarch: Add steal time support on migration > > Hi; this fails to build on all the aarch64 jobs > (both normal and cross-compile): > > https://gitlab.com/qemu-project/qemu/-/jobs/8190899599 > https://gitlab.com/qemu-project/qemu/-/jobs/8190899331 > > In file included from /usr/include/aarch64-linux-gnu/sys/syscall.h:24, > from ../util/oslib-posix.c:48: > linux-headers/asm/unistd.h:2:10: fatal error: asm/unistd_64.h: No such > file or directory > 2 | #include <asm/unistd_64.h> > | ^~~~~~~~~~~~~~~~~ OOPS, there is missing file about unistd_64.h on ARM64 besides LoongArch64 also. Will check and verify on all architectures. Regards Bibo Mao > > > thanks > -- PMM > ^ permalink raw reply [flat|nested] 18+ messages in thread
* [PULL 0/6] loongarch-to-apply queue
@ 2024-06-06 4:01 Song Gao
2024-06-07 0:06 ` Richard Henderson
0 siblings, 1 reply; 18+ messages in thread
From: Song Gao @ 2024-06-06 4:01 UTC (permalink / raw)
To: qemu-devel; +Cc: richard.henderson
The following changes since commit db2feb2df8d19592c9859efb3f682404e0052957:
Merge tag 'pull-misc-20240605' of https://gitlab.com/rth7680/qemu into staging (2024-06-05 14:17:01 -0700)
are available in the Git repository at:
https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20240606
for you to fetch changes up to 78f932ea1f7b3b9b0ac628dc2a91281318fe51fa:
target/loongarch: fix a wrong print in cpu dump (2024-06-06 11:58:06 +0800)
----------------------------------------------------------------
pull-loongarch-20240606
----------------------------------------------------------------
Bibo Mao (2):
tests/libqos: Add loongarch virt machine node
tests/qtest: Add numa test for loongarch system
Song Gao (3):
hw/intc/loongarch_extioi: Add extioi virt extension definition
hw/loongarch/virt: Use MemTxAttrs interface for misc ops
hw/loongarch/virt: Enable extioi virt extension
lanyanzhi (1):
target/loongarch: fix a wrong print in cpu dump
hw/intc/loongarch_extioi.c | 88 ++++++++++++-
hw/loongarch/virt.c | 184 +++++++++++++++++++++++-----
include/hw/intc/loongarch_extioi.h | 21 ++++
include/hw/loongarch/virt.h | 1 +
target/loongarch/cpu.c | 2 +-
target/loongarch/cpu.h | 1 +
tests/qtest/libqos/loongarch-virt-machine.c | 114 +++++++++++++++++
tests/qtest/libqos/meson.build | 1 +
tests/qtest/meson.build | 2 +-
tests/qtest/numa-test.c | 53 ++++++++
10 files changed, 428 insertions(+), 39 deletions(-)
create mode 100644 tests/qtest/libqos/loongarch-virt-machine.c
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PULL 0/6] loongarch-to-apply queue 2024-06-06 4:01 Song Gao @ 2024-06-07 0:06 ` Richard Henderson 0 siblings, 0 replies; 18+ messages in thread From: Richard Henderson @ 2024-06-07 0:06 UTC (permalink / raw) To: Song Gao, qemu-devel On 6/5/24 21:01, Song Gao wrote: > The following changes since commit db2feb2df8d19592c9859efb3f682404e0052957: > > Merge tag 'pull-misc-20240605' ofhttps://gitlab.com/rth7680/qemu into staging (2024-06-05 14:17:01 -0700) > > are available in the Git repository at: > > https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20240606 > > for you to fetch changes up to 78f932ea1f7b3b9b0ac628dc2a91281318fe51fa: > > target/loongarch: fix a wrong print in cpu dump (2024-06-06 11:58:06 +0800) > > ---------------------------------------------------------------- > pull-loongarch-20240606 Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/9.1 as appropriate. r~ ^ permalink raw reply [flat|nested] 18+ messages in thread
end of thread, other threads:[~2025-10-09 16:24 UTC | newest] Thread overview: 18+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2025-10-09 12:35 [PULL 0/6] loongarch-to-apply queue Song Gao 2025-10-09 12:35 ` [PULL 1/6] bios-tables-test-allowed-diff.h: Allow LoongArch DSDT.* Song Gao 2025-10-09 12:35 ` [PULL 2/6] hw/loongarch/virt: Align VIRT_GED_CPUHP_ADDR to 4 bytes Song Gao 2025-10-09 12:35 ` [PULL 3/6] tests/data/acpi/loongarch64: Update expected DSDT.* Song Gao 2025-10-09 12:35 ` [PULL 4/6] target/loongarch: Move TCG specified functions to tcg_cpu.c Song Gao 2025-10-09 12:36 ` [PULL 5/6] target/loongarch: Move function do_raise_exception() " Song Gao 2025-10-09 12:36 ` [PULL 6/6] target/loongarch: Define loongarch_exception_name() as static Song Gao 2025-10-09 16:23 ` [PULL 0/6] loongarch-to-apply queue Richard Henderson -- strict thread matches above, loose matches on Subject: below -- 2025-02-12 3:16 Bibo Mao 2025-02-12 17:39 ` Stefan Hajnoczi 2025-01-09 6:57 Bibo Mao 2025-01-09 16:32 ` Stefan Hajnoczi 2024-12-25 2:40 Bibo Mao 2024-10-24 9:26 Song Gao 2024-10-25 18:11 ` Peter Maydell 2024-10-26 7:23 ` bibo mao 2024-06-06 4:01 Song Gao 2024-06-07 0:06 ` Richard Henderson
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