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Tue, 10 Aug 2021 12:32:39 -0700 (PDT) Received: from [192.168.10.222] ([191.19.172.190]) by smtp.gmail.com with ESMTPSA id p23sm25013633pff.158.2021.08.10.12.32.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 10 Aug 2021 12:32:39 -0700 (PDT) Subject: Re: [PATCH 09/19] PPC64/TCG: Implement 'rfebb' instruction To: David Gibson References: <20210809131057.1694145-1-danielhb413@gmail.com> <20210809131057.1694145-10-danielhb413@gmail.com> From: Daniel Henrique Barboza Message-ID: Date: Tue, 10 Aug 2021 16:32:35 -0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=windows-1252; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=danielhb413@gmail.com; helo=mail-pj1-x1036.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: gustavo.romero@linaro.org, Gustavo Romero , qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 8/10/21 12:50 AM, David Gibson wrote: > On Mon, Aug 09, 2021 at 10:10:47AM -0300, Daniel Henrique Barboza wrote: >> From: Gustavo Romero >> >> An Event-Based Branch (EBB) allows applications to change the NIA when a >> event-based exception occurs. Event-based exceptions are enabled by >> setting the Branch Event Status and Control Register (BESCR). If the >> event-based exception is enabled when the exception occurs, an EBB >> happens. >> >> The EBB will: >> >> - set the Global Enable (GE) bit of BESCR to 0; >> - set bits 0-61 of the Event-Based Branch Return Register (EBBRR) to the >> effective address of the NIA that would have executed if the EBB >> didn't happen; >> - Instruction fetch and execution will continue in the effective address >> contained in the Event-Based Branch Handler Register (EBBHR). >> >> The EBB Handler will process the event and then execute the Return From >> Event-Based Branch (rfebb) instruction. rfebb sets BESCR_GE and then >> redirects execution to the address pointed in EBBRR. This process is >> described in the PowerISA v3.1, Book II, Chapter 6 [1]. >> >> This patch implements the rfebb instruction. Descriptions of all >> relevant BESCR bits are also added - this patch is only using BESCR_GE, >> but next patches will use the remaining bits. >> >> Note that we're implementing the extended rfebb mnemonic (BESCR_GE is >> being always set to 1). The basic rfebb instruction would accept an >> operand that would be used to set GE. >> >> [1] https://wiki.raptorcs.com/w/images/f/f5/PowerISA_public.v3.1.pdf >> >> CC: Gustavo Romero >> Signed-off-by: Gustavo Romero >> Signed-off-by: Daniel Henrique Barboza >> --- >> target/ppc/cpu.h | 12 ++++++++++++ >> target/ppc/translate.c | 21 +++++++++++++++++++++ >> 2 files changed, 33 insertions(+) >> >> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h >> index afd9cd402b..ae431e65be 100644 >> --- a/target/ppc/cpu.h >> +++ b/target/ppc/cpu.h >> @@ -358,6 +358,18 @@ typedef struct ppc_v3_pate_t { >> #define MMCR1_PMC3SEL PPC_BITMASK(48, 55) >> #define MMCR1_PMC4SEL PPC_BITMASK(56, 63) >> >> +/* EBB/BESCR bits */ >> +/* Global Enable */ >> +#define BESCR_GE PPC_BIT(0) >> +/* External Event-based Exception Enable */ >> +#define BESCR_EE PPC_BIT(30) >> +/* Performance Monitor Event-based Exception Enable */ >> +#define BESCR_PME PPC_BIT(31) >> +/* External Event-based Exception Occurred */ >> +#define BESCR_EEO PPC_BIT(62) >> +/* Performance Monitor Event-based Exception Occurred */ >> +#define BESCR_PMEO PPC_BIT(63) >> + >> /* LPCR bits */ >> #define LPCR_VPM0 PPC_BIT(0) >> #define LPCR_VPM1 PPC_BIT(1) >> diff --git a/target/ppc/translate.c b/target/ppc/translate.c >> index 62356cfadf..afc254a03f 100644 >> --- a/target/ppc/translate.c >> +++ b/target/ppc/translate.c >> @@ -2701,6 +2701,26 @@ static void gen_darn(DisasContext *ctx) >> } >> } >> } >> + >> +/* rfebb */ >> +static void gen_rfebb(DisasContext *ctx) > > Oof.. not necessarily a nack, but it would be nice to implement any > new instructions using the disastree path rather than the old ppc > specific decode logic. I'm not sure what is the disastree path. Is it similar to how rfscv is implemented? Daniel > >> +{ >> + TCGv target = tcg_temp_new(); >> + TCGv bescr = tcg_temp_new(); >> + >> + gen_load_spr(target, SPR_EBBRR); >> + tcg_gen_mov_tl(cpu_nip, target); >> + >> + gen_load_spr(bescr, SPR_BESCR); >> + tcg_gen_ori_tl(bescr, bescr, BESCR_GE); >> + gen_store_spr(SPR_BESCR, bescr); >> + >> + ctx->base.is_jmp = DISAS_EXIT; >> + >> + tcg_temp_free(target); >> + tcg_temp_free(bescr); >> +} >> + >> #endif >> >> /*** Integer rotate ***/ >> @@ -7724,6 +7744,7 @@ GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), >> GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), >> GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300), >> GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300), >> +GEN_HANDLER_E(rfebb, 0x13, 0x12, 0x04, 0x03FFF001, PPC_NONE, PPC2_ISA207S), >> GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), >> GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206), >> #endif >