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Tue, 12 Mar 2024 08:10:31 +0000 (GMT) Message-ID: Date: Tue, 12 Mar 2024 13:40:30 +0530 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 02/13] target/ppc: POWER10 does not have transactional memory Content-Language: en-US To: Nicholas Piggin , qemu-ppc@nongnu.org Cc: qemu-devel@nongnu.org, Daniel Henrique Barboza , David Gibson References: <20240311185200.2185753-1-npiggin@gmail.com> <20240311185200.2185753-3-npiggin@gmail.com> From: Harsh Prateek Bora In-Reply-To: <20240311185200.2185753-3-npiggin@gmail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: xpW5cssffRHBLEEMVnGajWM_8XZ0G4m4 X-Proofpoint-GUID: Mcr5a_dY0uAGgyEaudU59u-0z4c26iKj X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-12_06,2024-03-11_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 clxscore=1015 mlxlogscore=999 priorityscore=1501 suspectscore=0 mlxscore=0 adultscore=0 phishscore=0 malwarescore=0 impostorscore=0 bulkscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311290000 definitions=main-2403120062 Received-SPF: pass client-ip=148.163.158.5; envelope-from=harshpb@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Nick, One query/comment below: On 3/12/24 00:21, Nicholas Piggin wrote: > POWER10 hardware implements a degenerate transactional memory facility > in POWER8/9 PCR compatibility modes to permit migration from older > CPUs, but POWER10 / ISA v3.1 mode does not support it so the CPU model > should not support it. > > Signed-off-by: Nicholas Piggin > --- > target/ppc/cpu_init.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c > index 572cbdf25f..d7e84a2f40 100644 > --- a/target/ppc/cpu_init.c > +++ b/target/ppc/cpu_init.c > @@ -6573,7 +6573,7 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) > PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | > PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | > PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | > - PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310 | > + PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310 | > PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206; > pcc->msr_mask = (1ull << MSR_SF) | > (1ull << MSR_HV) | > @@ -6617,7 +6617,7 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) > pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | > POWERPC_FLAG_BE | POWERPC_FLAG_PMM | > POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | > - POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV; > + POWERPC_FLAG_VSX | POWERPC_FLAG_SCV; > pcc->l1_dcache_size = 0x8000; > pcc->l1_icache_size = 0x8000; > } Shouldn't we also have below change included with this: diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index aac095e5fd..faefc0420e 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -6641,7 +6641,6 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206 | PPC2_ATTN; pcc->msr_mask = (1ull << MSR_SF) | (1ull << MSR_HV) | - (1ull << MSR_TM) | (1ull << MSR_VR) | (1ull << MSR_VSX) | (1ull << MSR_EE) | Otherwise, Reviewed-by: Harsh Prateek Bora