From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:56172) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RWnbP-00027L-IK for qemu-devel@nongnu.org; Sat, 03 Dec 2011 06:18:06 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RWnbM-0002eY-Gn for qemu-devel@nongnu.org; Sat, 03 Dec 2011 06:17:55 -0500 Received: from fmmailgate03.web.de ([217.72.192.234]:56683) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RWnbL-0002dz-VL for qemu-devel@nongnu.org; Sat, 03 Dec 2011 06:17:52 -0500 Received: from moweb001.kundenserver.de (moweb001.kundenserver.de [172.19.20.114]) by fmmailgate03.web.de (Postfix) with ESMTP id 58A901AB328AB for ; Sat, 3 Dec 2011 12:17:51 +0100 (CET) From: Jan Kiszka Date: Sat, 3 Dec 2011 12:17:32 +0100 Message-Id: In-Reply-To: References: In-Reply-To: References: Subject: [Qemu-devel] [RFC][PATCH 07/16] ioapic: Convert to memory API List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Avi Kivity , Marcelo Tosatti Cc: Blue Swirl , Anthony Liguori , qemu-devel , kvm@vger.kernel.org, "Michael S. Tsirkin" From: Jan Kiszka This maintains the old imprecise access size handling. Signed-off-by: Jan Kiszka --- hw/ioapic.c | 28 +++++++++++----------------- 1 files changed, 11 insertions(+), 17 deletions(-) diff --git a/hw/ioapic.c b/hw/ioapic.c index 61991d7..56b1612 100644 --- a/hw/ioapic.c +++ b/hw/ioapic.c @@ -86,6 +86,7 @@ typedef struct IOAPICState IOAPICState; struct IOAPICState { SysBusDevice busdev; + MemoryRegion io_memory; uint8_t id; uint8_t ioregsel; uint32_t irr; @@ -195,7 +196,8 @@ void ioapic_eoi_broadcast(int vector) } } -static uint32_t ioapic_mem_readl(void *opaque, target_phys_addr_t addr) +static uint64_t +ioapic_mem_read(void *opaque, target_phys_addr_t addr, unsigned int size) { IOAPICState *s = opaque; int index; @@ -234,7 +236,8 @@ static uint32_t ioapic_mem_readl(void *opaque, target_phys_addr_t addr) } static void -ioapic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) +ioapic_mem_write(void *opaque, target_phys_addr_t addr, uint64_t val, + unsigned int size) { IOAPICState *s = opaque; int index; @@ -309,32 +312,23 @@ static void ioapic_reset(DeviceState *d) } } -static CPUReadMemoryFunc * const ioapic_mem_read[3] = { - ioapic_mem_readl, - ioapic_mem_readl, - ioapic_mem_readl, -}; - -static CPUWriteMemoryFunc * const ioapic_mem_write[3] = { - ioapic_mem_writel, - ioapic_mem_writel, - ioapic_mem_writel, +static const MemoryRegionOps ioapic_io_ops = { + .read = ioapic_mem_read, + .write = ioapic_mem_write, + .endianness = DEVICE_NATIVE_ENDIAN, }; static int ioapic_init1(SysBusDevice *dev) { IOAPICState *s = FROM_SYSBUS(IOAPICState, dev); - int io_memory; static int ioapic_no; if (ioapic_no >= MAX_IOAPICS) { return -1; } - io_memory = cpu_register_io_memory(ioapic_mem_read, - ioapic_mem_write, s, - DEVICE_NATIVE_ENDIAN); - sysbus_init_mmio(dev, 0x1000, io_memory); + memory_region_init_io(&s->io_memory, &ioapic_io_ops, s, "ioapic", 0x1000); + sysbus_init_mmio_region(dev, &s->io_memory); qdev_init_gpio_in(&dev->qdev, ioapic_set_irq, IOAPIC_NUM_PINS); -- 1.7.3.4