From: Richard Henderson <richard.henderson@linaro.org>
To: gaosong <gaosong@loongson.cn>, qemu-devel@nongnu.org
Cc: yangxiaojuan@loongson.cn, huqi@loongson.cn,
peter.maydell@linaro.org, alex.bennee@linaro.org,
maobibo@loongson.cn
Subject: Re: [PATCH v2 2/4] target/loongarch: bstrins.w need set dest register EXT_SIGN
Date: Thu, 29 Sep 2022 08:14:18 -0700 [thread overview]
Message-ID: <df8ec1eb-f7e4-579b-74cf-d27a85ec6047@linaro.org> (raw)
In-Reply-To: <c330da65-8069-4ec9-929e-15b2a1b2c47b@loongson.cn>
[-- Attachment #1: Type: text/plain, Size: 2045 bytes --]
On 9/29/22 00:27, gaosong wrote:
>
> 在 2022/9/28 下午11:13, Richard Henderson 写道:
>> On 9/26/22 23:48, Song Gao wrote:
>>> Signed-off-by: Song Gao <gaosong@loongson.cn>
>>> ---
>>> target/loongarch/insn_trans/trans_bit.c.inc | 4 ++--
>>> 1 file changed, 2 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/target/loongarch/insn_trans/trans_bit.c.inc
>>> b/target/loongarch/insn_trans/trans_bit.c.inc
>>> index 9337714ec4..33e94878fd 100644
>>> --- a/target/loongarch/insn_trans/trans_bit.c.inc
>>> +++ b/target/loongarch/insn_trans/trans_bit.c.inc
>>> @@ -37,7 +37,7 @@ static bool gen_rr_ms_ls(DisasContext *ctx, arg_rr_ms_ls *a,
>>> DisasExtend src_ext, DisasExtend dst_ext,
>>> void (*func)(TCGv, TCGv, unsigned int, unsigned int))
>>> {
>>> - TCGv dest = gpr_dst(ctx, a->rd, dst_ext);
>>> + TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
>>> TCGv src1 = gpr_src(ctx, a->rj, src_ext);
>>> if (a->ls > a->ms) {
>>> @@ -206,7 +206,7 @@ TRANS(maskeqz, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_maskeqz)
>>> TRANS(masknez, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_masknez)
>>> TRANS(bytepick_w, gen_rrr_sa, EXT_NONE, EXT_NONE, gen_bytepick_w)
>>> TRANS(bytepick_d, gen_rrr_sa, EXT_NONE, EXT_NONE, gen_bytepick_d)
>>> -TRANS(bstrins_w, gen_rr_ms_ls, EXT_NONE, EXT_NONE, gen_bstrins)
>>> +TRANS(bstrins_w, gen_rr_ms_ls, EXT_NONE, EXT_SIGN, gen_bstrins)
>>
>> These two hunks do opposite things: change dst_ext from NONE to SIGN, and then ignore
>> the change.
>>
>> I assume the first hunk is in fact in error.
>>
> rd is also a src register, rd should be src_dst.
>
> TCGv dest = gpr_src(ctx, a->rd, src_dst); what about this?
Ah, I see the problem. We're sharing a helper meant for unary operations for an
instruction that is a binary operation with an in+out operand.
I suggest not attempting to share code between bstrins and bstrpick, like so.
r~
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diff --git a/target/loongarch/insn_trans/trans_bit.c.inc b/target/loongarch/insn_trans/trans_bit.c.inc
index 9337714ec4..b01e4aeb23 100644
--- a/target/loongarch/insn_trans/trans_bit.c.inc
+++ b/target/loongarch/insn_trans/trans_bit.c.inc
@@ -27,26 +27,34 @@ static void gen_bytepick_d(TCGv dest, TCGv src1, TCGv src2, target_long sa)
tcg_gen_extract2_i64(dest, src1, src2, (64 - sa * 8));
}
-static void gen_bstrins(TCGv dest, TCGv src1,
- unsigned int ls, unsigned int len)
+static bool gen_bstrins(DisasContext *ctx, arg_rr_ms_ls *a,
+ DisasExtend dst_ext)
{
- tcg_gen_deposit_tl(dest, dest, src1, ls, len);
-}
-
-static bool gen_rr_ms_ls(DisasContext *ctx, arg_rr_ms_ls *a,
- DisasExtend src_ext, DisasExtend dst_ext,
- void (*func)(TCGv, TCGv, unsigned int, unsigned int))
-{
- TCGv dest = gpr_dst(ctx, a->rd, dst_ext);
- TCGv src1 = gpr_src(ctx, a->rj, src_ext);
+ TCGv src1 = gpr_src(ctx, a->rd, EXT_NONE);
+ TCGv src2 = gpr_src(ctx, a->rj, EXT_NONE);
+ TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
if (a->ls > a->ms) {
return false;
}
- func(dest, src1, a->ls, a->ms - a->ls + 1);
+ tcg_gen_deposit_tl(dest, src1, src2, a->ls, a->ms - a->ls + 1);
gen_set_gpr(a->rd, dest, dst_ext);
+ return true;
+}
+static bool gen_bstrpick(DisasContext *ctx, arg_rr_ms_ls *a,
+ DisasExtend dst_ext)
+{
+ TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
+ TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
+
+ if (a->ls > a->ms) {
+ return false;
+ }
+
+ tcg_gen_extract_tl(dest, src1, a->ls, a->ms - a->ls + 1);
+ gen_set_gpr(a->rd, dest, dst_ext);
return true;
}
@@ -206,7 +214,7 @@ TRANS(maskeqz, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_maskeqz)
TRANS(masknez, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_masknez)
TRANS(bytepick_w, gen_rrr_sa, EXT_NONE, EXT_NONE, gen_bytepick_w)
TRANS(bytepick_d, gen_rrr_sa, EXT_NONE, EXT_NONE, gen_bytepick_d)
-TRANS(bstrins_w, gen_rr_ms_ls, EXT_NONE, EXT_NONE, gen_bstrins)
-TRANS(bstrins_d, gen_rr_ms_ls, EXT_NONE, EXT_NONE, gen_bstrins)
-TRANS(bstrpick_w, gen_rr_ms_ls, EXT_NONE, EXT_SIGN, tcg_gen_extract_tl)
-TRANS(bstrpick_d, gen_rr_ms_ls, EXT_NONE, EXT_NONE, tcg_gen_extract_tl)
+TRANS(bstrins_w, gen_bstrins, EXT_SIGN)
+TRANS(bstrins_d, gen_bstrins, EXT_NONE)
+TRANS(bstrpick_w, gen_bstrpick, EXT_SIGN)
+TRANS(bstrpick_d, gen_bstrpick, EXT_NONE)
next prev parent reply other threads:[~2022-09-29 16:27 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-27 6:48 [PATCH v2 0/4] Fix some loongarch tcg bugs Song Gao
2022-09-27 6:48 ` [PATCH v2 1/4] target/loongarch: ftint_xxx insns set the result high 32bit 0xffffffff Song Gao
2022-09-28 15:14 ` Richard Henderson
2022-09-29 3:24 ` gaosong
2022-09-27 6:48 ` [PATCH v2 2/4] target/loongarch: bstrins.w need set dest register EXT_SIGN Song Gao
2022-09-28 15:13 ` Richard Henderson
2022-09-29 7:27 ` gaosong
2022-09-29 15:14 ` Richard Henderson [this message]
2022-09-27 6:48 ` [PATCH v2 3/4] target/loongarch: Fix fnm{sub/add}_{s/d} set wrong flags Song Gao
2022-09-28 15:16 ` Richard Henderson
2022-09-27 6:48 ` [PATCH v2 4/4] target/loongarch: flogb_{s/d} add set float_flag_divbyzero Song Gao
2022-09-28 15:24 ` Richard Henderson
2022-09-29 7:27 ` gaosong
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