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([2602:ae:1541:f901:396:9f0d:afc2:978e]) by smtp.gmail.com with ESMTPSA id j1-20020a17090276c100b00195f0fb0c18sm21184293plt.31.2023.03.28.07.27.28 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 28 Mar 2023 07:27:29 -0700 (PDT) Message-ID: Date: Tue, 28 Mar 2023 07:27:26 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.8.0 Subject: Re: [PATCH v6 13/25] target/riscv: Introduce mmuidx_priv Content-Language: en-US To: LIU Zhiwei , qemu-devel@nongnu.org References: <20230325105429.1142530-1-richard.henderson@linaro.org> <20230325105429.1142530-14-richard.henderson@linaro.org> <6b21f385-96fd-78f4-bdba-ed552bf2464a@linaro.org> <075a0bde-0d28-75e1-097f-f5218403b23d@linux.alibaba.com> <61c3d6d1-e242-f256-7d68-51a2155dc62a@linux.alibaba.com> From: Richard Henderson In-Reply-To: <61c3d6d1-e242-f256-7d68-51a2155dc62a@linux.alibaba.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 3/27/23 18:54, LIU Zhiwei wrote: >>>> Can we remove the PRIV from the tb flags after we have this function? >>> >>> No, because this is the priv of the memory operation as modified by e.g. MPRV, not the >>> true cpu priv. >> >> For this implementation, we explicitly use the tb flags for mmu index. I think it is the >> reason why we have to maintain the redundant privilege in tb flags. >> It may be better to only store machine states into tb flags. Can we just pass everything >> that we need, for example, the priv and sum, and then implicitly >> calculate the ctx->mem_idx in disas_init_fn? >> >> I remember that you give the similar suggestion in the comment process >> >> https://mail.gnu.org/archive/html/qemu-riscv/2023-03/msg00566.html >> >> Best Regards, >> Zhiwei >> > To make this comment clear, I paste a simple implementatioin here. But it is just for > discussing, not a normal patch for merging. > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 623288e6f9..d4506be5be 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -632,12 +632,10 @@ G_NORETURN void riscv_raise_exception(CPURISCVState *env, >  target_ulong riscv_cpu_get_fflags(CPURISCVState *env); >  void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); > > -#define TB_FLAGS_PRIV_MMU_MASK                3 > -#define TB_FLAGS_PRIV_HYP_ACCESS_MASK   (1 << 2) > - >  #include "exec/cpu-all.h" > > -FIELD(TB_FLAGS, MEM_IDX, 0, 3) > +FIELD(TB_FLAGS, PRIV, 0, 2) > +FIELD(TB_FLAGS, SUM, 2, 1) We would need to include MPRV, MPP, MPV, VIRT_ENABLED as well. With SUM, that would be 6 bits in tb_flags instead of 3 bits for MEM_IDX. r~