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[216.180.64.156]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71df0cbba1csm8319035b3a.33.2024.10.09.16.31.32 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 09 Oct 2024 16:31:33 -0700 (PDT) Message-ID: Date: Wed, 9 Oct 2024 16:31:32 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 08/23] accel/tcg: Add IntervalTreeRoot to CPUTLBDesc Content-Language: en-US To: Richard Henderson , qemu-devel@nongnu.org References: <20241009150855.804605-1-richard.henderson@linaro.org> <20241009150855.804605-9-richard.henderson@linaro.org> From: Pierrick Bouvier In-Reply-To: <20241009150855.804605-9-richard.henderson@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=pierrick.bouvier@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 10/9/24 08:08, Richard Henderson wrote: > Add the data structures for tracking softmmu pages via > a balanced interval tree. So far, only initialize and > destroy the data structure. > > Signed-off-by: Richard Henderson > --- > include/hw/core/cpu.h | 3 +++ > accel/tcg/cputlb.c | 11 +++++++++++ > 2 files changed, 14 insertions(+) > > diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h > index d21a24c82f..b567abe3e2 100644 > --- a/include/hw/core/cpu.h > +++ b/include/hw/core/cpu.h > @@ -34,6 +34,7 @@ > #include "qemu/rcu_queue.h" > #include "qemu/queue.h" > #include "qemu/thread.h" > +#include "qemu/interval-tree.h" > #include "qom/object.h" > > typedef int (*WriteCoreDumpFunction)(const void *buf, size_t size, > @@ -287,6 +288,8 @@ typedef struct CPUTLBDesc { > CPUTLBEntry vtable[CPU_VTLB_SIZE]; > CPUTLBEntryFull vfulltlb[CPU_VTLB_SIZE]; > CPUTLBEntryFull *fulltlb; > + /* All active tlb entries for this address space. */ > + IntervalTreeRoot iroot; > } CPUTLBDesc; > > /* > diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c > index 8affa25db3..435c2dc132 100644 > --- a/accel/tcg/cputlb.c > +++ b/accel/tcg/cputlb.c > @@ -89,6 +89,13 @@ QEMU_BUILD_BUG_ON(sizeof(vaddr) > sizeof(run_on_cpu_data)); > QEMU_BUILD_BUG_ON(NB_MMU_MODES > 16); > #define ALL_MMUIDX_BITS ((1 << NB_MMU_MODES) - 1) > > +/* Extra data required to manage CPUTLBEntryFull within an interval tree. */ > +typedef struct CPUTLBEntryTree { > + IntervalTreeNode itree; > + CPUTLBEntry copy; > + CPUTLBEntryFull full; > +} CPUTLBEntryTree; > + > static inline size_t tlb_n_entries(CPUTLBDescFast *fast) > { > return (fast->mask >> CPU_TLB_ENTRY_BITS) + 1; > @@ -305,6 +312,7 @@ static void tlb_mmu_flush_locked(CPUTLBDesc *desc, CPUTLBDescFast *fast) > desc->large_page_mask = -1; > desc->vindex = 0; > memset(desc->vtable, -1, sizeof(desc->vtable)); > + interval_tree_free_nodes(&desc->iroot, offsetof(CPUTLBEntryTree, itree)); > } > > static void tlb_flush_one_mmuidx_locked(CPUState *cpu, int mmu_idx, > @@ -326,6 +334,7 @@ static void tlb_mmu_init(CPUTLBDesc *desc, CPUTLBDescFast *fast, int64_t now) > fast->mask = (n_entries - 1) << CPU_TLB_ENTRY_BITS; > fast->table = g_new(CPUTLBEntry, n_entries); > desc->fulltlb = g_new(CPUTLBEntryFull, n_entries); > + memset(&desc->iroot, 0, sizeof(desc->iroot)); > tlb_mmu_flush_locked(desc, fast); > } > > @@ -365,6 +374,8 @@ void tlb_destroy(CPUState *cpu) > > g_free(fast->table); > g_free(desc->fulltlb); > + interval_tree_free_nodes(&cpu->neg.tlb.d[i].iroot, > + offsetof(CPUTLBEntryTree, itree)); > } > } > Reviewed-by: Pierrick Bouvier