[PATCH 0/2] hw/arm/sbsa-ref: add ITS support in GIC

[PATCH 0/2] hw/arm/sbsa-ref: add ITS support in GIC

[Marcin Juszkiewicz]

In 2021 Shashi Mallela sent v8 of GIC ITS patchset [1]. At that time it
was decided to do platform versioning first.

1. https://lore.kernel.org/qemu-devel/20210812165341.40784-8-shashi.mallela@linaro.org/

Now we are going through our list of changes for SBSA Reference Platform
and GIC ITS is one of early ones. There was decision that there will be
no option to disable it and platform version will get a minor bump.

First patch is refreshed version of v8 one from 2021. GIC ITS is placed
behind GIC Redistributor in memory space to allow use of older EDK2
firmware.

New address will be placed in DeviceTree for firmware to use - that's a
job for second patch. Which also bumps platform version to 0.2 version.

Trusted Firmware will read GIC ITS address and provide to EDK2 via
Secure Monitor Call (SMC). Same way as it is done with GIC addresses
already.

Marcin Juszkiewicz (1):
  hw/arm/sbsa-ref: add GIC ITS to DeviceTree

Shashi Mallela (1):
  hw/arm/sbsa-ref: add ITS support in SBSA GIC

 hw/arm/sbsa-ref.c | 35 ++++++++++++++++++++++++++++++++---
 1 file changed, 32 insertions(+), 3 deletions(-)

-- 
2.40.1

[PATCH 1/2] hw/arm/sbsa-ref: add ITS support in SBSA GIC

[Marcin Juszkiewicz]

From: Shashi Mallela <shashi.mallela@linaro.org>

Included creation of ITS as part of SBSA platform GIC
initialization.

Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>

---
 hw/arm/sbsa-ref.c | 26 ++++++++++++++++++++++++--
 1 file changed, 24 insertions(+), 2 deletions(-)

diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index de21200ff9..1520cd598c 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -65,6 +65,7 @@ enum {
     SBSA_CPUPERIPHS,
     SBSA_GIC_DIST,
     SBSA_GIC_REDIST,
+    SBSA_GIC_ITS,
     SBSA_SECURE_EC,
     SBSA_GWDT_WS0,
     SBSA_GWDT_REFRESH,
@@ -108,6 +109,7 @@ static const MemMapEntry sbsa_ref_memmap[] = {
     [SBSA_CPUPERIPHS] =         { 0x40000000, 0x00040000 },
     [SBSA_GIC_DIST] =           { 0x40060000, 0x00010000 },
     [SBSA_GIC_REDIST] =         { 0x40080000, 0x04000000 },
+    [SBSA_GIC_ITS] =            { 0x44081000, 0x00020000 },
     [SBSA_SECURE_EC] =          { 0x50000000, 0x00001000 },
     [SBSA_GWDT_REFRESH] =       { 0x50010000, 0x00001000 },
     [SBSA_GWDT_CONTROL] =       { 0x50011000, 0x00001000 },
@@ -409,7 +411,20 @@ static void create_secure_ram(SBSAMachineState *sms,
     memory_region_add_subregion(secure_sysmem, base, secram);
 }
 
-static void create_gic(SBSAMachineState *sms)
+static void create_its(SBSAMachineState *sms)
+{
+    const char *itsclass = its_class_name();
+    DeviceState *dev;
+
+    dev = qdev_new(itsclass);
+
+    object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(sms->gic),
+                             &error_abort);
+    sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
+    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, sbsa_ref_memmap[SBSA_GIC_ITS].base);
+}
+
+static void create_gic(SBSAMachineState *sms, MemoryRegion *mem)
 {
     unsigned int smp_cpus = MACHINE(sms)->smp.cpus;
     SysBusDevice *gicbusdev;
@@ -436,6 +451,12 @@ static void create_gic(SBSAMachineState *sms)
     qdev_prop_set_uint32(sms->gic, "len-redist-region-count", 1);
     qdev_prop_set_uint32(sms->gic, "redist-region-count[0]", redist0_count);
 
+    if (!kvm_irqchip_in_kernel()) {
+        object_property_set_link(OBJECT(sms->gic), "sysmem",
+                                OBJECT(mem), &error_fatal);
+        qdev_prop_set_bit(sms->gic, "has-lpi", true);
+    }
+
     gicbusdev = SYS_BUS_DEVICE(sms->gic);
     sysbus_realize_and_unref(gicbusdev, &error_fatal);
     sysbus_mmio_map(gicbusdev, 0, sbsa_ref_memmap[SBSA_GIC_DIST].base);
@@ -482,6 +503,7 @@ static void create_gic(SBSAMachineState *sms)
         sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus,
                            qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
     }
+    create_its(sms);
 }
 
 static void create_uart(const SBSAMachineState *sms, int uart,
@@ -788,7 +810,7 @@ static void sbsa_ref_init(MachineState *machine)
 
     create_secure_ram(sms, secure_sysmem);
 
-    create_gic(sms);
+    create_gic(sms, sysmem);
 
     create_uart(sms, SBSA_UART, sysmem, serial_hd(0));
     create_uart(sms, SBSA_SECURE_UART, secure_sysmem, serial_hd(1));
-- 
2.40.1

Re: [PATCH 1/2] hw/arm/sbsa-ref: add ITS support in SBSA GIC

[Peter Maydell]

On Tue, 6 Jun 2023 at 19:24, Marcin Juszkiewicz
<marcin.juszkiewicz@linaro.org> wrote:
>
> From: Shashi Mallela <shashi.mallela@linaro.org>
>
> Included creation of ITS as part of SBSA platform GIC
> initialization.
>
> Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>

Marcin, this should have your signed-off-by too because
the patch came to us via you.

> +static void create_gic(SBSAMachineState *sms, MemoryRegion *mem)
>  {
>      unsigned int smp_cpus = MACHINE(sms)->smp.cpus;
>      SysBusDevice *gicbusdev;
> @@ -436,6 +451,12 @@ static void create_gic(SBSAMachineState *sms)
>      qdev_prop_set_uint32(sms->gic, "len-redist-region-count", 1);
>      qdev_prop_set_uint32(sms->gic, "redist-region-count[0]", redist0_count);
>
> +    if (!kvm_irqchip_in_kernel()) {
> +        object_property_set_link(OBJECT(sms->gic), "sysmem",
> +                                OBJECT(mem), &error_fatal);
> +        qdev_prop_set_bit(sms->gic, "has-lpi", true);
> +    }

sbsa-ref never uses KVM, so we don't need the
kvm_irqchip_in_kernel() check, we can just always
set the link and the has-lpi prop.

Otherwise this looks OK.

thanks
-- PMM

[PATCH 2/2] hw/arm/sbsa-ref: add GIC ITS to DeviceTree

[Marcin Juszkiewicz]

We need GIC ITS information in DeviceTree so TF-A can pass it to EDK2.

Bumping platform version to 0.2 as this is important hardware change.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

---
 hw/arm/sbsa-ref.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index 1520cd598c..2bd9e370a7 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -183,8 +183,15 @@ static void sbsa_fdt_add_gic_node(SBSAMachineState *sms)
                                  2, sbsa_ref_memmap[SBSA_GIC_REDIST].base,
                                  2, sbsa_ref_memmap[SBSA_GIC_REDIST].size);
 
+    nodename = g_strdup_printf("/intc/its");
+    qemu_fdt_add_subnode(sms->fdt, nodename);
+    qemu_fdt_setprop_sized_cells(sms->fdt, nodename, "reg",
+                                 2, sbsa_ref_memmap[SBSA_GIC_ITS].base,
+                                 2, sbsa_ref_memmap[SBSA_GIC_ITS].size);
+
     g_free(nodename);
 }
+
 /*
  * Firmware on this machine only uses ACPI table to load OS, these limited
  * device tree nodes are just to let firmware know the info which varies from
@@ -221,7 +228,7 @@ static void create_fdt(SBSAMachineState *sms)
      *                        fw compatibility.
      */
     qemu_fdt_setprop_cell(fdt, "/", "machine-version-major", 0);
-    qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 1);
+    qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 2);
 
     if (ms->numa_state->have_numa_distance) {
         int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t);
-- 
2.40.1

Re: [PATCH 2/2] hw/arm/sbsa-ref: add GIC ITS to DeviceTree

[Peter Maydell]

On Tue, 6 Jun 2023 at 19:24, Marcin Juszkiewicz
<marcin.juszkiewicz@linaro.org> wrote:
>
> We need GIC ITS information in DeviceTree so TF-A can pass it to EDK2.
>
> Bumping platform version to 0.2 as this is important hardware change.
>
> Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
>
> ---
>  hw/arm/sbsa-ref.c | 9 ++++++++-
>  1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
> index 1520cd598c..2bd9e370a7 100644
> --- a/hw/arm/sbsa-ref.c
> +++ b/hw/arm/sbsa-ref.c
> @@ -183,8 +183,15 @@ static void sbsa_fdt_add_gic_node(SBSAMachineState *sms)
>                                   2, sbsa_ref_memmap[SBSA_GIC_REDIST].base,
>                                   2, sbsa_ref_memmap[SBSA_GIC_REDIST].size);
>
> +    nodename = g_strdup_printf("/intc/its");
> +    qemu_fdt_add_subnode(sms->fdt, nodename);
> +    qemu_fdt_setprop_sized_cells(sms->fdt, nodename, "reg",
> +                                 2, sbsa_ref_memmap[SBSA_GIC_ITS].base,
> +                                 2, sbsa_ref_memmap[SBSA_GIC_ITS].size);
> +
>      g_free(nodename);
>  }
> +
>  /*
>   * Firmware on this machine only uses ACPI table to load OS, these limited
>   * device tree nodes are just to let firmware know the info which varies from
> @@ -221,7 +228,7 @@ static void create_fdt(SBSAMachineState *sms)
>       *                        fw compatibility.
>       */
>      qemu_fdt_setprop_cell(fdt, "/", "machine-version-major", 0);
> -    qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 1);
> +    qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 2);
>
>      if (ms->numa_state->have_numa_distance) {
>          int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t);

We should fold this patch into the previous one.

If we are bumping the version-minor, we should add something
to the documentation that says what the difference between
0.1 and 0.2 is. (And if we can remember what 0.0 was that
would be worth noting.)

thanks
-- PMM

Re: [PATCH 2/2] hw/arm/sbsa-ref: add GIC ITS to DeviceTree

[Marcin Juszkiewicz]

W dniu 19.06.2023 o 14:55, Peter Maydell pisze:
> On Tue, 6 Jun 2023 at 19:24, Marcin Juszkiewicz
> <marcin.juszkiewicz@linaro.org> wrote:
>>
>> We need GIC ITS information in DeviceTree so TF-A can pass it to EDK2.
>>
>> Bumping platform version to 0.2 as this is important hardware change.


> We should fold this patch into the previous one.

Will do. With "Co-authored-by:" tag as ITS stuff was done by Shashi 
Mallela while I did DT part. And S-o-b too.

> If we are bumping the version-minor, we should add something
> to the documentation that says what the difference between
> 0.1 and 0.2 is. (And if we can remember what 0.0 was that
> would be worth noting.)

Will rebase on top of target-arm.next once you push it with 
documentation updates.