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From: Richard Henderson <richard.henderson@linaro.org>
To: Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
	qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com
Subject: Re: [PATCH alternate 2/2] target/riscv: Fix write_misa vs aligned next_pc
Date: Sat, 26 Apr 2025 07:12:19 -0700	[thread overview]
Message-ID: <dffe288e-5d28-4d56-8584-5d0b15365b72@linaro.org> (raw)
In-Reply-To: <1521e92e-699d-443b-8542-439854e6764a@ventanamicro.com>

On 4/25/25 15:20, Daniel Henrique Barboza wrote:
>> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
>> index c52c87faae..992ec8ebff 100644
>> --- a/target/riscv/csr.c
>> +++ b/target/riscv/csr.c
>> @@ -2111,10 +2111,13 @@ static RISCVException write_misa(CPURISCVState *env, int csrno,
>>       val &= env->misa_ext_mask;
>>       /*
>> -     * Suppress 'C' if next instruction is not aligned
>> -     * TODO: this should check next_pc
>> +     * Suppress 'C' if next instruction is not aligned.
>> +     * Outside of the context of a running cpu, env->pc contains next_pc.
>> +     * Within the context of a running cpu, env->pc contains the pc of
>> +     * the csrw/csrrw instruction.  But since all such instructions are
>> +     * exactly 4 bytes, next_pc has the same alignment mod 4.
> 
> 
> By "outside of the context of a running CPU" you mean a halted CPU, correct?

Correct, e.g. from gdbstub.

> 
> And now, for a running CPU, env->pc has the pc of csrw/csrrw because of patch 1.

Correct.

> Otherwise it would contain a pc that was synchronized via the last
> synchronize_from_tb, or any other insn that happened to sync env->pc in
> the same TB via gen_update_pc(). We're not keeping env->pc up to date all
> the time because it would be extra work that wouldn't be needed most of the
> time. Am I too off the mark?

Correct.

> 
> The reason I'm asking is because I see at least one place (get_physical_address())
> where it's stated that "the env->pc at this point is incorrect".

Correct, since get_physical_address is called from riscv_cpu_tlb_fill, which can be called 
during the processing of any guest memory operation.


> And I see env->pc
> being either the current PC or the next insn PC depending on the situation.
> Reading these 2 patches clarified it a bit (assuming I'm not completely incorrect,
> of course).

I would expect env->pc to be more or less random in get_physical_address, with a bias 
toward the PC of the first instruction of the TB.

I'm not sure why get_physical_address has that comment.  The current pc isn't relevant to 
resolving a virtual address.  It only becomes relevant when there is a fault, and the pc 
is restored via unwinding along the fault path.


r~


  reply	other threads:[~2025-04-26 14:13 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-04-25 16:50 [PATCH alternate 0/2] target/riscv: Fix write_misa vs aligned next_pc Richard Henderson
2025-04-25 16:50 ` [PATCH alternate 1/2] target/riscv: Update pc before csrw, csrrw Richard Henderson
2025-04-25 22:02   ` Daniel Henrique Barboza
2025-04-25 16:50 ` [PATCH alternate 2/2] target/riscv: Fix write_misa vs aligned next_pc Richard Henderson
2025-04-25 22:20   ` Daniel Henrique Barboza
2025-04-26 14:12     ` Richard Henderson [this message]
2025-04-25 22:35 ` [PATCH alternate 0/2] " Philippe Mathieu-Daudé
2025-04-26  8:30   ` Daniel Henrique Barboza

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