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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-73e25967aedsm4834233b3a.83.2025.04.26.07.12.21 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 26 Apr 2025 07:12:21 -0700 (PDT) Message-ID: Date: Sat, 26 Apr 2025 07:12:19 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH alternate 2/2] target/riscv: Fix write_misa vs aligned next_pc To: Daniel Henrique Barboza , qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com References: <20250425165055.807801-1-richard.henderson@linaro.org> <20250425165055.807801-3-richard.henderson@linaro.org> <1521e92e-699d-443b-8542-439854e6764a@ventanamicro.com> Content-Language: en-US From: Richard Henderson In-Reply-To: <1521e92e-699d-443b-8542-439854e6764a@ventanamicro.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 4/25/25 15:20, Daniel Henrique Barboza wrote: >> diff --git a/target/riscv/csr.c b/target/riscv/csr.c >> index c52c87faae..992ec8ebff 100644 >> --- a/target/riscv/csr.c >> +++ b/target/riscv/csr.c >> @@ -2111,10 +2111,13 @@ static RISCVException write_misa(CPURISCVState *env, int csrno, >>       val &= env->misa_ext_mask; >>       /* >> -     * Suppress 'C' if next instruction is not aligned >> -     * TODO: this should check next_pc >> +     * Suppress 'C' if next instruction is not aligned. >> +     * Outside of the context of a running cpu, env->pc contains next_pc. >> +     * Within the context of a running cpu, env->pc contains the pc of >> +     * the csrw/csrrw instruction.  But since all such instructions are >> +     * exactly 4 bytes, next_pc has the same alignment mod 4. > > > By "outside of the context of a running CPU" you mean a halted CPU, correct? Correct, e.g. from gdbstub. > > And now, for a running CPU, env->pc has the pc of csrw/csrrw because of patch 1. Correct. > Otherwise it would contain a pc that was synchronized via the last > synchronize_from_tb, or any other insn that happened to sync env->pc in > the same TB via gen_update_pc(). We're not keeping env->pc up to date all > the time because it would be extra work that wouldn't be needed most of the > time. Am I too off the mark? Correct. > > The reason I'm asking is because I see at least one place (get_physical_address()) > where it's stated that "the env->pc at this point is incorrect". Correct, since get_physical_address is called from riscv_cpu_tlb_fill, which can be called during the processing of any guest memory operation. > And I see env->pc > being either the current PC or the next insn PC depending on the situation. > Reading these 2 patches clarified it a bit (assuming I'm not completely incorrect, > of course). I would expect env->pc to be more or less random in get_physical_address, with a bias toward the PC of the first instruction of the TB. I'm not sure why get_physical_address has that comment. The current pc isn't relevant to resolving a virtual address. It only becomes relevant when there is a fault, and the pc is restored via unwinding along the fault path. r~