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[176.184.10.225]) by smtp.gmail.com with ESMTPSA id x14-20020a170906804e00b009884f015a44sm2721166ejw.49.2023.06.19.06.54.23 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 19 Jun 2023 06:54:24 -0700 (PDT) Message-ID: Date: Mon, 19 Jun 2023 15:54:20 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.11.0 Subject: Re: [PATCH v2 12/12] target/arm: Allow users to set the number of VFP registers Content-Language: en-US To: Peter Maydell , Mads Ynddal Cc: =?UTF-8?Q?C=c3=a9dric_Le_Goater?= , "open list:ARM cores" , qemu-devel@nongnu.org, Joel Stanley , Andrew Jeffery , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= References: <20230607043943.1837186-1-clg@kaod.org> <20230607043943.1837186-13-clg@kaod.org> <955C217E-FE0F-41E2-8E97-9AFD8C4A0DBE@ynddal.dk> From: Richard Henderson In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-ej1-x636.google.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.09, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 6/19/23 15:41, Peter Maydell wrote: > On Mon, 19 Jun 2023 at 13:47, Mads Ynddal wrote: >> >> Sorry, if this has already been acknowledged, but I couldn't find it on the >> mailinglist. >> >> This commit seems to break compatibility with macOS accelerator hvf when >> virtualizing ARM CPUs. >> >> It breaks the VM on boot-up with the message "ARM CPUs must have both VFP-D32 >> and Neon or neither". I haven't looked into what VFP-D32 and Neon are, but the >> same VM worked on earlier versions of QEMU. >> >> It can be reproduced with the following: >> >> qemu-system-aarch64 \ >> -nodefaults \ >> -display "none" \ >> -machine "virt" \ >> -accel "hvf" \ >> -cpu "host" \ >> -serial "mon:stdio" >> qemu-system-aarch64: ARM CPUs must have both VFP-D32 and Neon or neither >> >> >> If you fix/work on this issue in a separate thread/patch, you can add >> reported-by, so I'll automatically follow and help test it: >> >> Reported-by: Mads Ynddal >> > > >>> @@ -1406,6 +1409,22 @@ void arm_cpu_post_init(Object *obj) >>> } >>> } >>> >>> + if (cpu->has_vfp && cpu_isar_feature(aa32_simd_r32, cpu)) { >>> + cpu->has_vfp_d32 = true; >>> + if (!kvm_enabled()) { > > Probably this should be "if (!kvm_enabled() && !hvf_enabled())". > Is that sufficient to fix the regression ? (I have a feeling it > isn't, but we might as well test...) Yes, insufficient. But I'm also changing these to tcg || qtest. > >>> + /* >>> + * The permitted values of the SIMDReg bits [3:0] on >>> + * Armv8-A are either 0b0000 and 0b0010. On such CPUs, >>> + * make sure that has_vfp_d32 can not be set to false. >>> + */ >>> + if (!(arm_feature(&cpu->env, ARM_FEATURE_V8) && >>> + !arm_feature(&cpu->env, ARM_FEATURE_M))) { >>> + qdev_property_add_static(DEVICE(obj), >>> + &arm_cpu_has_vfp_d32_property); >>> + } >>> + } >>> + } >>> + >>> if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) { >>> cpu->has_neon = true; >>> if (!kvm_enabled()) { >>> @@ -1672,6 +1691,19 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) >>> return; >>> } >>> >>> + if (cpu->has_vfp_d32 != cpu->has_neon) { >>> + error_setg(errp, "ARM CPUs must have both VFP-D32 and Neon or neither"); >>> + return; >>> + } > > The other thing I see looking again at this code is that it > doesn't account for CPUs which don't have AArch32 support > at all. The MVFR0 register which the aa32_simd_r32 feature > test is looking at is an AArch32 register, and the test > will not return a sensible answer on an AArch64-only CPU. This is the problem. The code needs restructuring (which I am about to test). > On the other side of this, target/arm/hvf/hvf.c always > sets ARM_FEATURE_NEON, which I think is probably not > correct given that Neon is also an AArch32-only thing. At one time NEON also meant AdvSIMD, though we have now changed aa64 to the isar test. We could probably get rid of NEON now too, with just a little more cleanup. r~