* [PATCH v2 01/17] hw/arm/aspeed: Add LTPI controller
2025-11-05 3:58 [PATCH v2 00/17] hw/arm/aspeed: AST1700 LTPI support and device hookups Kane Chen via
@ 2025-11-05 3:58 ` Kane Chen via
2025-11-07 13:07 ` Cédric Le Goater
2025-11-05 3:58 ` [PATCH v2 02/17] hw/arm/aspeed: Attach LTPI controller to AST27X0 platform Kane Chen via
` (17 subsequent siblings)
18 siblings, 1 reply; 46+ messages in thread
From: Kane Chen via @ 2025-11-05 3:58 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, Kane-Chen-AS
From: Kane-Chen-AS <kane_chen@aspeedtech.com>
LTPI (LVDS Tunneling Protocol & Interface) is defined in the OCP DC-SCM
2.0 specification:
https://www.opencompute.org/documents/ocp-dc-scm-2-0-ltpi-ver-1-0-pdf
LTPI is a protocol and physical interface for tunneling various low-speed
signals between the HPM and SCM. As shown in Figure 2, the AST27x0 (left)
integrates two LTPI controllers, allowing it to connect to up to two
extended boards.
This commit introduces a simple device model for the ASPEED LTPI
controller in QEMU.
The model includes basic MMIO read/write operations and sets default
register values during reset to emulate a link-up state.
Implements register space with read/write callbacks.
Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
---
include/hw/misc/aspeed_ltpi.h | 25 +++++++++
hw/misc/aspeed_ltpi.c | 98 +++++++++++++++++++++++++++++++++++
hw/misc/meson.build | 1 +
3 files changed, 124 insertions(+)
create mode 100644 include/hw/misc/aspeed_ltpi.h
create mode 100644 hw/misc/aspeed_ltpi.c
diff --git a/include/hw/misc/aspeed_ltpi.h b/include/hw/misc/aspeed_ltpi.h
new file mode 100644
index 0000000000..2c31a555dd
--- /dev/null
+++ b/include/hw/misc/aspeed_ltpi.h
@@ -0,0 +1,25 @@
+/*
+ * ASPEED LTPI Controller
+ *
+ * Copyright (C) 2025 ASPEED Technology Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+#ifndef ASPEED_LTPI_H
+#define ASPEED_LTPI_H
+
+#include "hw/sysbus.h"
+
+#define TYPE_ASPEED_LTPI "aspeed.ltpi-ctrl"
+OBJECT_DECLARE_SIMPLE_TYPE(AspeedLTPIState, ASPEED_LTPI)
+
+#define ASPEED_LTPI_NR_REGS (0x900 >> 2)
+
+struct AspeedLTPIState {
+ SysBusDevice parent;
+ MemoryRegion mmio;
+
+ uint32_t regs[ASPEED_LTPI_NR_REGS];
+};
+
+#endif /* ASPEED_LTPI_H */
diff --git a/hw/misc/aspeed_ltpi.c b/hw/misc/aspeed_ltpi.c
new file mode 100644
index 0000000000..fdb71077a4
--- /dev/null
+++ b/hw/misc/aspeed_ltpi.c
@@ -0,0 +1,98 @@
+/*
+ * ASPEED LTPI Controller
+ *
+ * Copyright (C) 2025 ASPEED Technology Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "migration/vmstate.h"
+#include "hw/misc/aspeed_ltpi.h"
+
+#define LTPI_LINK_MNG 0x42
+#define LTPI_PHY_MODE 0x80
+
+static uint64_t aspeed_ltpi_read(void *opaque, hwaddr offset, unsigned size)
+{
+ AspeedLTPIState *s = opaque;
+ uint32_t idx = offset >> 2;
+
+ return s->regs[idx];
+}
+
+static void aspeed_ltpi_write(void *opaque, hwaddr offset,
+ uint64_t val, unsigned size)
+{
+ AspeedLTPIState *s = opaque;
+ uint32_t idx = offset >> 2;
+
+ switch (offset) {
+ default:
+ s->regs[idx] = (uint32_t)val;
+ break;
+ }
+}
+
+static const MemoryRegionOps aspeed_ltpi_ops = {
+ .read = aspeed_ltpi_read,
+ .write = aspeed_ltpi_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 1,
+ .max_access_size = 4,
+ },
+};
+
+static void aspeed_ltpi_reset(DeviceState *dev)
+{
+ AspeedLTPIState *s = ASPEED_LTPI(dev);
+ memset(s->regs, 0, sizeof(s->regs));
+ /* set default values */
+ s->regs[LTPI_LINK_MNG] = 0x11900007;
+ s->regs[LTPI_PHY_MODE] = 0x2;
+}
+
+
+static const VMStateDescription vmstate_aspeed_ltpi = {
+ .name = TYPE_ASPEED_LTPI,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32_ARRAY(regs, AspeedLTPIState,
+ ASPEED_LTPI_NR_REGS),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void aspeed_ltpi_realize(DeviceState *dev, Error **errp)
+{
+ AspeedLTPIState *s = ASPEED_LTPI(dev);
+
+ memory_region_init_io(&s->mmio, OBJECT(s), &aspeed_ltpi_ops, s,
+ TYPE_ASPEED_LTPI, ASPEED_LTPI_NR_REGS);
+ sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mmio);
+}
+
+static void aspeed_ltpi_class_init(ObjectClass *klass, const void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ dc->realize = aspeed_ltpi_realize;
+ dc->vmsd = &vmstate_aspeed_ltpi;
+ device_class_set_legacy_reset(dc, aspeed_ltpi_reset);
+}
+
+static const TypeInfo aspeed_ltpi_info = {
+ .name = TYPE_ASPEED_LTPI,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(AspeedLTPIState),
+ .class_init = aspeed_ltpi_class_init,
+};
+
+static void aspeed_ltpi_register_types(void)
+{
+ type_register_static(&aspeed_ltpi_info);
+}
+
+type_init(aspeed_ltpi_register_types);
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index b1d8d8e5d2..45b16e7797 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -136,6 +136,7 @@ system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
'aspeed_hace.c',
'aspeed_i3c.c',
'aspeed_lpc.c',
+ 'aspeed_ltpi.c',
'aspeed_scu.c',
'aspeed_sbc.c',
'aspeed_sdmc.c',
--
2.43.0
^ permalink raw reply related [flat|nested] 46+ messages in thread* Re: [PATCH v2 01/17] hw/arm/aspeed: Add LTPI controller
2025-11-05 3:58 ` [PATCH v2 01/17] hw/arm/aspeed: Add LTPI controller Kane Chen via
@ 2025-11-07 13:07 ` Cédric Le Goater
0 siblings, 0 replies; 46+ messages in thread
From: Cédric Le Goater @ 2025-11-07 13:07 UTC (permalink / raw)
To: Kane Chen, Peter Maydell, Steven Lee, Troy Lee, Jamin Lin,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee
On 11/5/25 04:58, Kane Chen wrote:
> From: Kane-Chen-AS <kane_chen@aspeedtech.com>
>
> LTPI (LVDS Tunneling Protocol & Interface) is defined in the OCP DC-SCM
> 2.0 specification:
> https://www.opencompute.org/documents/ocp-dc-scm-2-0-ltpi-ver-1-0-pdf
>
> LTPI is a protocol and physical interface for tunneling various low-speed
> signals between the HPM and SCM. As shown in Figure 2, the AST27x0 (left)
> integrates two LTPI controllers, allowing it to connect to up to two
> extended boards.
>
> This commit introduces a simple device model for the ASPEED LTPI
> controller in QEMU.
>
> The model includes basic MMIO read/write operations and sets default
> register values during reset to emulate a link-up state.
>
> Implements register space with read/write callbacks.
>
> Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
> ---
> include/hw/misc/aspeed_ltpi.h | 25 +++++++++
> hw/misc/aspeed_ltpi.c | 98 +++++++++++++++++++++++++++++++++++
> hw/misc/meson.build | 1 +
> 3 files changed, 124 insertions(+)
> create mode 100644 include/hw/misc/aspeed_ltpi.h
> create mode 100644 hw/misc/aspeed_ltpi.c
>
> diff --git a/include/hw/misc/aspeed_ltpi.h b/include/hw/misc/aspeed_ltpi.h
> new file mode 100644
> index 0000000000..2c31a555dd
> --- /dev/null
> +++ b/include/hw/misc/aspeed_ltpi.h
> @@ -0,0 +1,25 @@
> +/*
> + * ASPEED LTPI Controller
> + *
> + * Copyright (C) 2025 ASPEED Technology Inc.
> + *
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + */
> +#ifndef ASPEED_LTPI_H
> +#define ASPEED_LTPI_H
> +
> +#include "hw/sysbus.h"
> +
> +#define TYPE_ASPEED_LTPI "aspeed.ltpi-ctrl"
> +OBJECT_DECLARE_SIMPLE_TYPE(AspeedLTPIState, ASPEED_LTPI)
> +
> +#define ASPEED_LTPI_NR_REGS (0x900 >> 2)
> +
> +struct AspeedLTPIState {
> + SysBusDevice parent;
> + MemoryRegion mmio;
> +
> + uint32_t regs[ASPEED_LTPI_NR_REGS];
> +};
> +
> +#endif /* ASPEED_LTPI_H */
> diff --git a/hw/misc/aspeed_ltpi.c b/hw/misc/aspeed_ltpi.c
> new file mode 100644
> index 0000000000..fdb71077a4
> --- /dev/null
> +++ b/hw/misc/aspeed_ltpi.c
> @@ -0,0 +1,98 @@
> +/*
> + * ASPEED LTPI Controller
> + *
> + * Copyright (C) 2025 ASPEED Technology Inc.
> + *
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qemu/log.h"
> +#include "migration/vmstate.h"
> +#include "hw/misc/aspeed_ltpi.h"
> +
> +#define LTPI_LINK_MNG 0x42
> +#define LTPI_PHY_MODE 0x80
> +
> +static uint64_t aspeed_ltpi_read(void *opaque, hwaddr offset, unsigned size)
> +{
> + AspeedLTPIState *s = opaque;
> + uint32_t idx = offset >> 2;
> +
> + return s->regs[idx];
> +}
> +
> +static void aspeed_ltpi_write(void *opaque, hwaddr offset,
> + uint64_t val, unsigned size)
> +{
> + AspeedLTPIState *s = opaque;
> + uint32_t idx = offset >> 2;
> +
> + switch (offset) {
> + default:
> + s->regs[idx] = (uint32_t)val;
> + break;
> + }
> +}
> +
> +static const MemoryRegionOps aspeed_ltpi_ops = {
> + .read = aspeed_ltpi_read,
> + .write = aspeed_ltpi_write,
> + .endianness = DEVICE_LITTLE_ENDIAN,
> + .valid = {
> + .min_access_size = 1,
> + .max_access_size = 4,
> + },
> +};
> +
> +static void aspeed_ltpi_reset(DeviceState *dev)
> +{
> + AspeedLTPIState *s = ASPEED_LTPI(dev);
> + memset(s->regs, 0, sizeof(s->regs));
> + /* set default values */
> + s->regs[LTPI_LINK_MNG] = 0x11900007;
> + s->regs[LTPI_PHY_MODE] = 0x2;
> +}
> +
> +
> +static const VMStateDescription vmstate_aspeed_ltpi = {
> + .name = TYPE_ASPEED_LTPI,
> + .version_id = 1,
> + .minimum_version_id = 1,
> + .fields = (VMStateField[]) {
> + VMSTATE_UINT32_ARRAY(regs, AspeedLTPIState,
> + ASPEED_LTPI_NR_REGS),
> + VMSTATE_END_OF_LIST()
> + }
> +};
> +
> +static void aspeed_ltpi_realize(DeviceState *dev, Error **errp)
> +{
> + AspeedLTPIState *s = ASPEED_LTPI(dev);
> +
> + memory_region_init_io(&s->mmio, OBJECT(s), &aspeed_ltpi_ops, s,
> + TYPE_ASPEED_LTPI, ASPEED_LTPI_NR_REGS);
The MMIO aperture is not number of registers. It should be 0x900.
Also, AIUI, there are 3 different register sets under this controller.
Don't we want to model them with sub regions ?
Thanks,
C.
> + sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mmio);
> +}
> +
> +static void aspeed_ltpi_class_init(ObjectClass *klass, const void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> + dc->realize = aspeed_ltpi_realize;
> + dc->vmsd = &vmstate_aspeed_ltpi;
> + device_class_set_legacy_reset(dc, aspeed_ltpi_reset);
> +}
> +
> +static const TypeInfo aspeed_ltpi_info = {
> + .name = TYPE_ASPEED_LTPI,
> + .parent = TYPE_SYS_BUS_DEVICE,
> + .instance_size = sizeof(AspeedLTPIState),
> + .class_init = aspeed_ltpi_class_init,
> +};
> +
> +static void aspeed_ltpi_register_types(void)
> +{
> + type_register_static(&aspeed_ltpi_info);
> +}
> +
> +type_init(aspeed_ltpi_register_types);
> diff --git a/hw/misc/meson.build b/hw/misc/meson.build
> index b1d8d8e5d2..45b16e7797 100644
> --- a/hw/misc/meson.build
> +++ b/hw/misc/meson.build
> @@ -136,6 +136,7 @@ system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
> 'aspeed_hace.c',
> 'aspeed_i3c.c',
> 'aspeed_lpc.c',
> + 'aspeed_ltpi.c',
> 'aspeed_scu.c',
> 'aspeed_sbc.c',
> 'aspeed_sdmc.c',
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH v2 02/17] hw/arm/aspeed: Attach LTPI controller to AST27X0 platform
2025-11-05 3:58 [PATCH v2 00/17] hw/arm/aspeed: AST1700 LTPI support and device hookups Kane Chen via
2025-11-05 3:58 ` [PATCH v2 01/17] hw/arm/aspeed: Add LTPI controller Kane Chen via
@ 2025-11-05 3:58 ` Kane Chen via
2025-11-07 13:08 ` Cédric Le Goater
2025-11-05 3:58 ` [PATCH v2 03/17] hw/arm/aspeed: Add AST1700 LTPI expander device model Kane Chen via
` (16 subsequent siblings)
18 siblings, 1 reply; 46+ messages in thread
From: Kane Chen via @ 2025-11-05 3:58 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, Kane-Chen-AS
From: Kane-Chen-AS <kane_chen@aspeedtech.com>
Connect the LTPI controller device (representing the AST1700 I/O
expander) to the AST27X0 SoC model. This patch sets up the memory
mapping and device registration according to the AST2700 SoC design,
where the LTPI controller is exposed at fixed MMIO regions.
This change only handles device instantiation and integration,
without implementing the controller's internal logic.
Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
---
include/hw/arm/aspeed_soc.h | 5 +++++
hw/arm/aspeed_ast27x0.c | 18 ++++++++++++++++++
2 files changed, 23 insertions(+)
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index 4b8e599f1a..bae60d85ea 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -42,6 +42,7 @@
#include "hw/fsi/aspeed_apb2opb.h"
#include "hw/char/serial-mm.h"
#include "hw/intc/arm_gicv3.h"
+#include "hw/misc/aspeed_ltpi.h"
#define VBOOTROM_FILE_NAME "ast27x0_bootrom.bin"
@@ -53,6 +54,7 @@
#define ASPEED_UARTS_NUM 13
#define ASPEED_JTAG_NUM 2
#define ASPEED_PCIE_NUM 3
+#define ASPEED_IOEXP_NUM 2
struct AspeedSoCState {
DeviceState parent;
@@ -110,6 +112,7 @@ struct AspeedSoCState {
UnimplementedDeviceState ltpi;
UnimplementedDeviceState jtag[ASPEED_JTAG_NUM];
AspeedAPB2OPBState fsi[2];
+ AspeedLTPIState ltpi_ctrl[ASPEED_IOEXP_NUM];
};
#define TYPE_ASPEED_SOC "aspeed-soc"
@@ -275,6 +278,8 @@ enum {
ASPEED_GIC_REDIST,
ASPEED_DEV_IPC0,
ASPEED_DEV_IPC1,
+ ASPEED_DEV_LTPI_CTRL1,
+ ASPEED_DEV_LTPI_CTRL2,
};
const char *aspeed_soc_cpu_type(const char * const *valid_cpu_types);
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index c484bcd4e2..c0d8639bde 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -86,6 +86,8 @@ static const hwaddr aspeed_soc_ast2700_memmap[] = {
[ASPEED_DEV_UART10] = 0x14C33900,
[ASPEED_DEV_UART11] = 0x14C33A00,
[ASPEED_DEV_UART12] = 0x14C33B00,
+ [ASPEED_DEV_LTPI_CTRL1] = 0x14C34000,
+ [ASPEED_DEV_LTPI_CTRL2] = 0x14C35000,
[ASPEED_DEV_WDT] = 0x14C37000,
[ASPEED_DEV_PCIE_MMIO0] = 0x60000000,
[ASPEED_DEV_PCIE_MMIO1] = 0x80000000,
@@ -543,6 +545,10 @@ static void aspeed_soc_ast2700_init(Object *obj)
object_property_set_int(OBJECT(&s->pcie[i]), "id", i, &error_abort);
}
+ for (i = 0; i < ASPEED_IOEXP_NUM; i++) {
+ object_initialize_child(obj, "ltpi-ctrl[*]",
+ &s->ltpi_ctrl[i], TYPE_ASPEED_LTPI);
+ }
object_initialize_child(obj, "dpmcu", &s->dpmcu,
TYPE_UNIMPLEMENTED_DEVICE);
object_initialize_child(obj, "ltpi", &s->ltpi,
@@ -688,6 +694,8 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
g_autofree char *name = NULL;
qemu_irq irq;
int uart;
+ AspeedLTPIState *ltpi_ctrl;
+ hwaddr ltpi_base;
/* Default boot region (SPI memory or ROMs) */
memory_region_init(&s->spi_boot_container, OBJECT(s),
@@ -1021,6 +1029,16 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
return;
}
+ /* LTPI controller */
+ for (i = 0; i < ASPEED_IOEXP_NUM; i++) {
+ ltpi_ctrl = ASPEED_LTPI(&s->ltpi_ctrl[i]);
+ ltpi_base = sc->memmap[ASPEED_DEV_LTPI_CTRL1 + i];
+
+ if (!sysbus_realize(SYS_BUS_DEVICE(ltpi_ctrl), errp)) {
+ return;
+ }
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(ltpi_ctrl), 0, ltpi_base);
+ }
aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->dpmcu),
"aspeed.dpmcu",
sc->memmap[ASPEED_DEV_DPMCU],
--
2.43.0
^ permalink raw reply related [flat|nested] 46+ messages in thread* Re: [PATCH v2 02/17] hw/arm/aspeed: Attach LTPI controller to AST27X0 platform
2025-11-05 3:58 ` [PATCH v2 02/17] hw/arm/aspeed: Attach LTPI controller to AST27X0 platform Kane Chen via
@ 2025-11-07 13:08 ` Cédric Le Goater
0 siblings, 0 replies; 46+ messages in thread
From: Cédric Le Goater @ 2025-11-07 13:08 UTC (permalink / raw)
To: Kane Chen, Peter Maydell, Steven Lee, Troy Lee, Jamin Lin,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee
On 11/5/25 04:58, Kane Chen wrote:
> From: Kane-Chen-AS <kane_chen@aspeedtech.com>
>
> Connect the LTPI controller device (representing the AST1700 I/O
> expander) to the AST27X0 SoC model. This patch sets up the memory
> mapping and device registration according to the AST2700 SoC design,
> where the LTPI controller is exposed at fixed MMIO regions.
>
> This change only handles device instantiation and integration,
> without implementing the controller's internal logic.
>
> Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
> ---
> include/hw/arm/aspeed_soc.h | 5 +++++
> hw/arm/aspeed_ast27x0.c | 18 ++++++++++++++++++
> 2 files changed, 23 insertions(+)
>
> diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
> index 4b8e599f1a..bae60d85ea 100644
> --- a/include/hw/arm/aspeed_soc.h
> +++ b/include/hw/arm/aspeed_soc.h
> @@ -42,6 +42,7 @@
> #include "hw/fsi/aspeed_apb2opb.h"
> #include "hw/char/serial-mm.h"
> #include "hw/intc/arm_gicv3.h"
> +#include "hw/misc/aspeed_ltpi.h"
>
> #define VBOOTROM_FILE_NAME "ast27x0_bootrom.bin"
>
> @@ -53,6 +54,7 @@
> #define ASPEED_UARTS_NUM 13
> #define ASPEED_JTAG_NUM 2
> #define ASPEED_PCIE_NUM 3
> +#define ASPEED_IOEXP_NUM 2
>
> struct AspeedSoCState {
> DeviceState parent;
> @@ -110,6 +112,7 @@ struct AspeedSoCState {
> UnimplementedDeviceState ltpi;
> UnimplementedDeviceState jtag[ASPEED_JTAG_NUM];
> AspeedAPB2OPBState fsi[2];
> + AspeedLTPIState ltpi_ctrl[ASPEED_IOEXP_NUM];
> };
>
> #define TYPE_ASPEED_SOC "aspeed-soc"
> @@ -275,6 +278,8 @@ enum {
> ASPEED_GIC_REDIST,
> ASPEED_DEV_IPC0,
> ASPEED_DEV_IPC1,
> + ASPEED_DEV_LTPI_CTRL1,
> + ASPEED_DEV_LTPI_CTRL2,
> };
>
> const char *aspeed_soc_cpu_type(const char * const *valid_cpu_types);
> diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
> index c484bcd4e2..c0d8639bde 100644
> --- a/hw/arm/aspeed_ast27x0.c
> +++ b/hw/arm/aspeed_ast27x0.c
> @@ -86,6 +86,8 @@ static const hwaddr aspeed_soc_ast2700_memmap[] = {
> [ASPEED_DEV_UART10] = 0x14C33900,
> [ASPEED_DEV_UART11] = 0x14C33A00,
> [ASPEED_DEV_UART12] = 0x14C33B00,
> + [ASPEED_DEV_LTPI_CTRL1] = 0x14C34000,
> + [ASPEED_DEV_LTPI_CTRL2] = 0x14C35000,
> [ASPEED_DEV_WDT] = 0x14C37000,
> [ASPEED_DEV_PCIE_MMIO0] = 0x60000000,
> [ASPEED_DEV_PCIE_MMIO1] = 0x80000000,
> @@ -543,6 +545,10 @@ static void aspeed_soc_ast2700_init(Object *obj)
> object_property_set_int(OBJECT(&s->pcie[i]), "id", i, &error_abort);
> }
>
> + for (i = 0; i < ASPEED_IOEXP_NUM; i++) {
> + object_initialize_child(obj, "ltpi-ctrl[*]",
> + &s->ltpi_ctrl[i], TYPE_ASPEED_LTPI);
> + }
> object_initialize_child(obj, "dpmcu", &s->dpmcu,
> TYPE_UNIMPLEMENTED_DEVICE);
> object_initialize_child(obj, "ltpi", &s->ltpi,
> @@ -688,6 +694,8 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
> g_autofree char *name = NULL;
> qemu_irq irq;
> int uart;
> + AspeedLTPIState *ltpi_ctrl;
> + hwaddr ltpi_base;
These 2 variable declarations could be moved under the loop introduced
below.
Thanks,
C.
>
> /* Default boot region (SPI memory or ROMs) */
> memory_region_init(&s->spi_boot_container, OBJECT(s),
> @@ -1021,6 +1029,16 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
> return;
> }
>
> + /* LTPI controller */
> + for (i = 0; i < ASPEED_IOEXP_NUM; i++) {
> + ltpi_ctrl = ASPEED_LTPI(&s->ltpi_ctrl[i]);
> + ltpi_base = sc->memmap[ASPEED_DEV_LTPI_CTRL1 + i];
> +
> + if (!sysbus_realize(SYS_BUS_DEVICE(ltpi_ctrl), errp)) {
> + return;
> + }
> + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(ltpi_ctrl), 0, ltpi_base);
> + }
> aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->dpmcu),
> "aspeed.dpmcu",
> sc->memmap[ASPEED_DEV_DPMCU],
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH v2 03/17] hw/arm/aspeed: Add AST1700 LTPI expander device model
2025-11-05 3:58 [PATCH v2 00/17] hw/arm/aspeed: AST1700 LTPI support and device hookups Kane Chen via
2025-11-05 3:58 ` [PATCH v2 01/17] hw/arm/aspeed: Add LTPI controller Kane Chen via
2025-11-05 3:58 ` [PATCH v2 02/17] hw/arm/aspeed: Attach LTPI controller to AST27X0 platform Kane Chen via
@ 2025-11-05 3:58 ` Kane Chen via
2025-11-07 13:10 ` Cédric Le Goater
2025-11-05 3:58 ` [PATCH v2 04/17] hw/arm/aspeed: Integrate AST1700 device into AST27X0 Kane Chen via
` (15 subsequent siblings)
18 siblings, 1 reply; 46+ messages in thread
From: Kane Chen via @ 2025-11-05 3:58 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, Kane-Chen-AS
From: Kane-Chen-AS <kane_chen@aspeedtech.com>
Introduce a minimal QEMU device model for the ASPEED AST1700, an
MCU-less I/O expander used in the LTPI topology defined by the
DC-SCM 2.0 specification (see figure 2):
https://www.opencompute.org/documents/ocp-dc-scm-2-0-ltpi-ver-1-0-pdf
This initial implementation includes:
* Definition of aspeed.ast1700 as a SysBusDevice
* Setup of a basic memory region to reserve I/O space for future
peripheral modeling
This stub establishes the foundation for LTPI-related device emulation,
without implementing any functional peripherals at this stage.
Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
---
include/hw/misc/aspeed_ast1700.h | 32 ++++++++++++++++++
hw/misc/aspeed_ast1700.c | 57 ++++++++++++++++++++++++++++++++
hw/misc/meson.build | 1 +
3 files changed, 90 insertions(+)
create mode 100644 include/hw/misc/aspeed_ast1700.h
create mode 100644 hw/misc/aspeed_ast1700.c
diff --git a/include/hw/misc/aspeed_ast1700.h b/include/hw/misc/aspeed_ast1700.h
new file mode 100644
index 0000000000..b7c666eef2
--- /dev/null
+++ b/include/hw/misc/aspeed_ast1700.h
@@ -0,0 +1,32 @@
+/*
+ * ASPEED AST1700 IO Expander
+ *
+ * Copyright (C) 2025 ASPEED Technology Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+#ifndef ASPEED_AST1700_H
+#define ASPEED_AST1700_H
+
+#include "hw/sysbus.h"
+#include "hw/misc/aspeed_scu.h"
+#include "hw/adc/aspeed_adc.h"
+#include "hw/gpio/aspeed_gpio.h"
+#include "hw/i2c/aspeed_i2c.h"
+#include "hw/misc/aspeed_ltpi.h"
+#include "hw/ssi/aspeed_smc.h"
+#include "hw/watchdog/wdt_aspeed.h"
+#include "hw/char/serial-mm.h"
+#include "hw/misc/unimp.h"
+
+#define TYPE_ASPEED_AST1700 "aspeed.ast1700"
+
+OBJECT_DECLARE_SIMPLE_TYPE(AspeedAST1700SoCState, ASPEED_AST1700)
+
+struct AspeedAST1700SoCState {
+ SysBusDevice parent_obj;
+
+ MemoryRegion iomem;
+};
+
+#endif /* ASPEED_AST1700_H */
diff --git a/hw/misc/aspeed_ast1700.c b/hw/misc/aspeed_ast1700.c
new file mode 100644
index 0000000000..bb05e392f4
--- /dev/null
+++ b/hw/misc/aspeed_ast1700.c
@@ -0,0 +1,57 @@
+/*
+ * ASPEED AST1700 IO Expander
+ *
+ * Copyright (C) 2025 ASPEED Technology Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "hw/boards.h"
+#include "hw/qdev-core.h"
+#include "qom/object.h"
+#include "hw/qdev-properties.h"
+#include "qemu/log.h"
+#include "migration/vmstate.h"
+#include "hw/misc/aspeed_ast1700.h"
+
+#define AST2700_SOC_LTPI_SIZE 0x01000000
+static void aspeed_ast1700_realize(DeviceState *dev, Error **errp)
+{
+ AspeedAST1700SoCState *s = ASPEED_AST1700(dev);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+
+ /* Occupy memory space for all controllers in AST1700 */
+ memory_region_init(&s->iomem, OBJECT(s), TYPE_ASPEED_AST1700,
+ AST2700_SOC_LTPI_SIZE);
+ sysbus_init_mmio(sbd, &s->iomem);
+
+}
+
+static void aspeed_ast1700_instance_init(Object *obj)
+{
+ return;
+}
+
+static void aspeed_ast1700_class_init(ObjectClass *klass, const void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->realize = aspeed_ast1700_realize;
+}
+
+static const TypeInfo aspeed_ast1700_info = {
+ .name = TYPE_ASPEED_AST1700,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(AspeedAST1700SoCState),
+ .class_init = aspeed_ast1700_class_init,
+ .instance_init = aspeed_ast1700_instance_init,
+};
+
+
+static void aspeed_ast1700_register_types(void)
+{
+ type_register_static(&aspeed_ast1700_info);
+}
+
+type_init(aspeed_ast1700_register_types);
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index 45b16e7797..9477e63cdf 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -133,6 +133,7 @@ system_ss.add(when: 'CONFIG_PVPANIC_PCI', if_true: files('pvpanic-pci.c'))
system_ss.add(when: 'CONFIG_PVPANIC_MMIO', if_true: files('pvpanic-mmio.c'))
system_ss.add(when: 'CONFIG_AUX', if_true: files('auxbus.c'))
system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
+ 'aspeed_ast1700.c',
'aspeed_hace.c',
'aspeed_i3c.c',
'aspeed_lpc.c',
--
2.43.0
^ permalink raw reply related [flat|nested] 46+ messages in thread* Re: [PATCH v2 03/17] hw/arm/aspeed: Add AST1700 LTPI expander device model
2025-11-05 3:58 ` [PATCH v2 03/17] hw/arm/aspeed: Add AST1700 LTPI expander device model Kane Chen via
@ 2025-11-07 13:10 ` Cédric Le Goater
0 siblings, 0 replies; 46+ messages in thread
From: Cédric Le Goater @ 2025-11-07 13:10 UTC (permalink / raw)
To: Kane Chen, Peter Maydell, Steven Lee, Troy Lee, Jamin Lin,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee
On 11/5/25 04:58, Kane Chen wrote:
> From: Kane-Chen-AS <kane_chen@aspeedtech.com>
>
> Introduce a minimal QEMU device model for the ASPEED AST1700, an
> MCU-less I/O expander used in the LTPI topology defined by the
> DC-SCM 2.0 specification (see figure 2):
> https://www.opencompute.org/documents/ocp-dc-scm-2-0-ltpi-ver-1-0-pdf
>
> This initial implementation includes:
>
> * Definition of aspeed.ast1700 as a SysBusDevice
>
> * Setup of a basic memory region to reserve I/O space for future
> peripheral modeling
>
> This stub establishes the foundation for LTPI-related device emulation,
> without implementing any functional peripherals at this stage.
>
> Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
> ---
> include/hw/misc/aspeed_ast1700.h | 32 ++++++++++++++++++
> hw/misc/aspeed_ast1700.c | 57 ++++++++++++++++++++++++++++++++
> hw/misc/meson.build | 1 +
> 3 files changed, 90 insertions(+)
> create mode 100644 include/hw/misc/aspeed_ast1700.h
> create mode 100644 hw/misc/aspeed_ast1700.c
>
> diff --git a/include/hw/misc/aspeed_ast1700.h b/include/hw/misc/aspeed_ast1700.h
> new file mode 100644
> index 0000000000..b7c666eef2
> --- /dev/null
> +++ b/include/hw/misc/aspeed_ast1700.h
> @@ -0,0 +1,32 @@
> +/*
> + * ASPEED AST1700 IO Expander
> + *
> + * Copyright (C) 2025 ASPEED Technology Inc.
> + *
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + */
> +#ifndef ASPEED_AST1700_H
> +#define ASPEED_AST1700_H
> +
> +#include "hw/sysbus.h"
> +#include "hw/misc/aspeed_scu.h"
> +#include "hw/adc/aspeed_adc.h"
> +#include "hw/gpio/aspeed_gpio.h"
> +#include "hw/i2c/aspeed_i2c.h"
> +#include "hw/misc/aspeed_ltpi.h"
> +#include "hw/ssi/aspeed_smc.h"
> +#include "hw/watchdog/wdt_aspeed.h"
> +#include "hw/char/serial-mm.h"
> +#include "hw/misc/unimp.h"
There are too much includes. Please introduce the minimum each time.
> +
> +#define TYPE_ASPEED_AST1700 "aspeed.ast1700"
> +
> +OBJECT_DECLARE_SIMPLE_TYPE(AspeedAST1700SoCState, ASPEED_AST1700)
> +
> +struct AspeedAST1700SoCState {
> + SysBusDevice parent_obj;
> +
> + MemoryRegion iomem;
> +};
> +
> +#endif /* ASPEED_AST1700_H */
> diff --git a/hw/misc/aspeed_ast1700.c b/hw/misc/aspeed_ast1700.c
> new file mode 100644
> index 0000000000..bb05e392f4
> --- /dev/null
> +++ b/hw/misc/aspeed_ast1700.c
> @@ -0,0 +1,57 @@
> +/*
> + * ASPEED AST1700 IO Expander
> + *
> + * Copyright (C) 2025 ASPEED Technology Inc.
> + *
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + */
> +
> +#include "qemu/osdep.h"
> +#include "hw/boards.h"
> +#include "hw/qdev-core.h"
> +#include "qom/object.h"
> +#include "hw/qdev-properties.h"
> +#include "qemu/log.h"
> +#include "migration/vmstate.h"
No vmstate ?
> +#include "hw/misc/aspeed_ast1700.h"
> +> +#define AST2700_SOC_LTPI_SIZE 0x01000000
> +static void aspeed_ast1700_realize(DeviceState *dev, Error **errp)
> +{
> + AspeedAST1700SoCState *s = ASPEED_AST1700(dev);
> + SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
> +
> + /* Occupy memory space for all controllers in AST1700 */
> + memory_region_init(&s->iomem, OBJECT(s), TYPE_ASPEED_AST1700,
> + AST2700_SOC_LTPI_SIZE);
> + sysbus_init_mmio(sbd, &s->iomem);
> +
> +}
> +
> +static void aspeed_ast1700_instance_init(Object *obj)
> +{
> + return;
> +}
It's better to introduce a routine when needed.
Thanks,
C.
> +static void aspeed_ast1700_class_init(ObjectClass *klass, const void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> +
> + dc->realize = aspeed_ast1700_realize;
> +}
> +
> +static const TypeInfo aspeed_ast1700_info = {
> + .name = TYPE_ASPEED_AST1700,
> + .parent = TYPE_SYS_BUS_DEVICE,
> + .instance_size = sizeof(AspeedAST1700SoCState),
> + .class_init = aspeed_ast1700_class_init,
> + .instance_init = aspeed_ast1700_instance_init,
> +};
> +
> +
> +static void aspeed_ast1700_register_types(void)
> +{
> + type_register_static(&aspeed_ast1700_info);
> +}
> +
> +type_init(aspeed_ast1700_register_types);
> diff --git a/hw/misc/meson.build b/hw/misc/meson.build
> index 45b16e7797..9477e63cdf 100644
> --- a/hw/misc/meson.build
> +++ b/hw/misc/meson.build
> @@ -133,6 +133,7 @@ system_ss.add(when: 'CONFIG_PVPANIC_PCI', if_true: files('pvpanic-pci.c'))
> system_ss.add(when: 'CONFIG_PVPANIC_MMIO', if_true: files('pvpanic-mmio.c'))
> system_ss.add(when: 'CONFIG_AUX', if_true: files('auxbus.c'))
> system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
> + 'aspeed_ast1700.c',
> 'aspeed_hace.c',
> 'aspeed_i3c.c',
> 'aspeed_lpc.c',
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH v2 04/17] hw/arm/aspeed: Integrate AST1700 device into AST27X0
2025-11-05 3:58 [PATCH v2 00/17] hw/arm/aspeed: AST1700 LTPI support and device hookups Kane Chen via
` (2 preceding siblings ...)
2025-11-05 3:58 ` [PATCH v2 03/17] hw/arm/aspeed: Add AST1700 LTPI expander device model Kane Chen via
@ 2025-11-05 3:58 ` Kane Chen via
2025-11-07 13:30 ` Cédric Le Goater
2025-11-05 3:58 ` [PATCH v2 05/17] hw/arm/aspeed: Integrate interrupt controller for AST1700 Kane Chen via
` (14 subsequent siblings)
18 siblings, 1 reply; 46+ messages in thread
From: Kane Chen via @ 2025-11-05 3:58 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, Kane-Chen-AS
From: Kane-Chen-AS <kane_chen@aspeedtech.com>
Connect the AST1700 device as a child of the AST27X0 model to reflect
its role in DC-SCM 2.0 LTPI-based architectures. This patch wires
the AST1700 device into the platform without introducing functional
peripherals.
This forms the base for LTPI expander emulation in QEMU using
AST27X0 as the host controller.
Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
---
include/hw/arm/aspeed_soc.h | 9 +++++++--
include/hw/misc/aspeed_ast1700.h | 1 +
hw/arm/aspeed_ast27x0.c | 30 ++++++++++++++++++++++--------
hw/misc/aspeed_ast1700.c | 6 ++++++
4 files changed, 36 insertions(+), 10 deletions(-)
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index bae60d85ea..00cd8df038 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -43,6 +43,7 @@
#include "hw/char/serial-mm.h"
#include "hw/intc/arm_gicv3.h"
#include "hw/misc/aspeed_ltpi.h"
+#include "hw/misc/aspeed_ast1700.h"
#define VBOOTROM_FILE_NAME "ast27x0_bootrom.bin"
@@ -109,10 +110,10 @@ struct AspeedSoCState {
UnimplementedDeviceState espi;
UnimplementedDeviceState udc;
UnimplementedDeviceState sgpiom;
- UnimplementedDeviceState ltpi;
UnimplementedDeviceState jtag[ASPEED_JTAG_NUM];
AspeedAPB2OPBState fsi[2];
AspeedLTPIState ltpi_ctrl[ASPEED_IOEXP_NUM];
+ AspeedAST1700SoCState ioexp[ASPEED_IOEXP_NUM];
};
#define TYPE_ASPEED_SOC "aspeed-soc"
@@ -174,6 +175,7 @@ struct AspeedSoCClass {
int macs_num;
int uarts_num;
int uarts_base;
+ int ioexp_num;
const int *irqmap;
const hwaddr *memmap;
uint32_t num_cpus;
@@ -186,7 +188,8 @@ enum {
ASPEED_DEV_IOMEM,
ASPEED_DEV_IOMEM0,
ASPEED_DEV_IOMEM1,
- ASPEED_DEV_LTPI,
+ ASPEED_DEV_LTPI_IO0,
+ ASPEED_DEV_LTPI_IO1,
ASPEED_DEV_UART0,
ASPEED_DEV_UART1,
ASPEED_DEV_UART2,
@@ -280,6 +283,8 @@ enum {
ASPEED_DEV_IPC1,
ASPEED_DEV_LTPI_CTRL1,
ASPEED_DEV_LTPI_CTRL2,
+ ASPEED_DEV_IOEXP0_INTCIO,
+ ASPEED_DEV_IOEXP1_INTCIO,
};
const char *aspeed_soc_cpu_type(const char * const *valid_cpu_types);
diff --git a/include/hw/misc/aspeed_ast1700.h b/include/hw/misc/aspeed_ast1700.h
index b7c666eef2..624ef61eda 100644
--- a/include/hw/misc/aspeed_ast1700.h
+++ b/include/hw/misc/aspeed_ast1700.h
@@ -20,6 +20,7 @@
#include "hw/misc/unimp.h"
#define TYPE_ASPEED_AST1700 "aspeed.ast1700"
+#define TYPE_ASPEED_AST1700_AST2700 "aspeed.ast1700-ast2700"
OBJECT_DECLARE_SIMPLE_TYPE(AspeedAST1700SoCState, ASPEED_AST1700)
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index c0d8639bde..054864467d 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -26,7 +26,6 @@
#define AST2700_SOC_IO_SIZE 0x00FE0000
#define AST2700_SOC_IOMEM_SIZE 0x01000000
#define AST2700_SOC_DPMCU_SIZE 0x00040000
-#define AST2700_SOC_LTPI_SIZE 0x01000000
static const hwaddr aspeed_soc_ast2700_memmap[] = {
[ASPEED_DEV_VBOOTROM] = 0x00000000,
@@ -89,11 +88,14 @@ static const hwaddr aspeed_soc_ast2700_memmap[] = {
[ASPEED_DEV_LTPI_CTRL1] = 0x14C34000,
[ASPEED_DEV_LTPI_CTRL2] = 0x14C35000,
[ASPEED_DEV_WDT] = 0x14C37000,
+ [ASPEED_DEV_LTPI_IO0] = 0x30000000,
+ [ASPEED_DEV_IOEXP0_INTCIO] = 0x30C18000,
+ [ASPEED_DEV_LTPI_IO1] = 0x50000000,
+ [ASPEED_DEV_IOEXP1_INTCIO] = 0x50C18000,
[ASPEED_DEV_PCIE_MMIO0] = 0x60000000,
[ASPEED_DEV_PCIE_MMIO1] = 0x80000000,
[ASPEED_DEV_PCIE_MMIO2] = 0xA0000000,
[ASPEED_DEV_SPI_BOOT] = 0x100000000,
- [ASPEED_DEV_LTPI] = 0x300000000,
[ASPEED_DEV_SDRAM] = 0x400000000,
};
@@ -549,10 +551,15 @@ static void aspeed_soc_ast2700_init(Object *obj)
object_initialize_child(obj, "ltpi-ctrl[*]",
&s->ltpi_ctrl[i], TYPE_ASPEED_LTPI);
}
+
+ for (i = 0; i < sc->ioexp_num; i++) {
+ /* AST1700 IOEXP */
+ object_initialize_child(obj, "ioexp[*]", &s->ioexp[i],
+ TYPE_ASPEED_AST1700_AST2700);
+ }
+
object_initialize_child(obj, "dpmcu", &s->dpmcu,
TYPE_UNIMPLEMENTED_DEVICE);
- object_initialize_child(obj, "ltpi", &s->ltpi,
- TYPE_UNIMPLEMENTED_DEVICE);
object_initialize_child(obj, "iomem", &s->iomem,
TYPE_UNIMPLEMENTED_DEVICE);
object_initialize_child(obj, "iomem0", &s->iomem0,
@@ -1039,14 +1046,20 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
}
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(ltpi_ctrl), 0, ltpi_base);
}
+
+ /* IO Expander */
+ for (i = 0; i < sc->ioexp_num; i++) {
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->ioexp[i]), errp)) {
+ return;
+ }
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioexp[i]), 0,
+ sc->memmap[ASPEED_DEV_LTPI_IO0 + i]);
+ }
+
aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->dpmcu),
"aspeed.dpmcu",
sc->memmap[ASPEED_DEV_DPMCU],
AST2700_SOC_DPMCU_SIZE);
- aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->ltpi),
- "aspeed.ltpi",
- sc->memmap[ASPEED_DEV_LTPI],
- AST2700_SOC_LTPI_SIZE);
aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->iomem),
"aspeed.io",
sc->memmap[ASPEED_DEV_IOMEM],
@@ -1112,6 +1125,7 @@ static void aspeed_soc_ast2700a1_class_init(ObjectClass *oc, const void *data)
sc->macs_num = 3;
sc->uarts_num = 13;
sc->num_cpus = 4;
+ sc->ioexp_num = 2;
sc->uarts_base = ASPEED_DEV_UART0;
sc->irqmap = aspeed_soc_ast2700a1_irqmap;
sc->memmap = aspeed_soc_ast2700_memmap;
diff --git a/hw/misc/aspeed_ast1700.c b/hw/misc/aspeed_ast1700.c
index bb05e392f4..3125bec795 100644
--- a/hw/misc/aspeed_ast1700.c
+++ b/hw/misc/aspeed_ast1700.c
@@ -48,10 +48,16 @@ static const TypeInfo aspeed_ast1700_info = {
.instance_init = aspeed_ast1700_instance_init,
};
+static const TypeInfo aspeed_ast1700_ast2700_info = {
+ .name = TYPE_ASPEED_AST1700_AST2700,
+ .parent = TYPE_ASPEED_AST1700,
+};
+
static void aspeed_ast1700_register_types(void)
{
type_register_static(&aspeed_ast1700_info);
+ type_register_static(&aspeed_ast1700_ast2700_info);
}
type_init(aspeed_ast1700_register_types);
--
2.43.0
^ permalink raw reply related [flat|nested] 46+ messages in thread* Re: [PATCH v2 04/17] hw/arm/aspeed: Integrate AST1700 device into AST27X0
2025-11-05 3:58 ` [PATCH v2 04/17] hw/arm/aspeed: Integrate AST1700 device into AST27X0 Kane Chen via
@ 2025-11-07 13:30 ` Cédric Le Goater
0 siblings, 0 replies; 46+ messages in thread
From: Cédric Le Goater @ 2025-11-07 13:30 UTC (permalink / raw)
To: Kane Chen, Peter Maydell, Steven Lee, Troy Lee, Jamin Lin,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee
On 11/5/25 04:58, Kane Chen wrote:
> From: Kane-Chen-AS <kane_chen@aspeedtech.com>
>
> Connect the AST1700 device as a child of the AST27X0 model to reflect
> its role in DC-SCM 2.0 LTPI-based architectures. This patch wires
> the AST1700 device into the platform without introducing functional
> peripherals.
>
> This forms the base for LTPI expander emulation in QEMU using
> AST27X0 as the host controller.
>
> Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
> ---
> include/hw/arm/aspeed_soc.h | 9 +++++++--
> include/hw/misc/aspeed_ast1700.h | 1 +
> hw/arm/aspeed_ast27x0.c | 30 ++++++++++++++++++++++--------
> hw/misc/aspeed_ast1700.c | 6 ++++++
> 4 files changed, 36 insertions(+), 10 deletions(-)
>
> diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
> index bae60d85ea..00cd8df038 100644
> --- a/include/hw/arm/aspeed_soc.h
> +++ b/include/hw/arm/aspeed_soc.h
> @@ -43,6 +43,7 @@
> #include "hw/char/serial-mm.h"
> #include "hw/intc/arm_gicv3.h"
> #include "hw/misc/aspeed_ltpi.h"
> +#include "hw/misc/aspeed_ast1700.h"
>
> #define VBOOTROM_FILE_NAME "ast27x0_bootrom.bin"
>
> @@ -109,10 +110,10 @@ struct AspeedSoCState {
> UnimplementedDeviceState espi;
> UnimplementedDeviceState udc;
> UnimplementedDeviceState sgpiom;
> - UnimplementedDeviceState ltpi;
> UnimplementedDeviceState jtag[ASPEED_JTAG_NUM];
> AspeedAPB2OPBState fsi[2];
> AspeedLTPIState ltpi_ctrl[ASPEED_IOEXP_NUM];
> + AspeedAST1700SoCState ioexp[ASPEED_IOEXP_NUM];
> };
>
> #define TYPE_ASPEED_SOC "aspeed-soc"
> @@ -174,6 +175,7 @@ struct AspeedSoCClass {
> int macs_num;
> int uarts_num;
> int uarts_base;
> + int ioexp_num;
> const int *irqmap;
> const hwaddr *memmap;
> uint32_t num_cpus;
> @@ -186,7 +188,8 @@ enum {
> ASPEED_DEV_IOMEM,
> ASPEED_DEV_IOMEM0,
> ASPEED_DEV_IOMEM1,
> - ASPEED_DEV_LTPI,
> + ASPEED_DEV_LTPI_IO0,
> + ASPEED_DEV_LTPI_IO1,
> ASPEED_DEV_UART0,
> ASPEED_DEV_UART1,
> ASPEED_DEV_UART2,
> @@ -280,6 +283,8 @@ enum {
> ASPEED_DEV_IPC1,
> ASPEED_DEV_LTPI_CTRL1,
> ASPEED_DEV_LTPI_CTRL2,
> + ASPEED_DEV_IOEXP0_INTCIO,
> + ASPEED_DEV_IOEXP1_INTCIO,
Please put the index number at the end of the enum definition.
These definitions are unused too. Please move in the next patch.
> };
>
> const char *aspeed_soc_cpu_type(const char * const *valid_cpu_types);
> diff --git a/include/hw/misc/aspeed_ast1700.h b/include/hw/misc/aspeed_ast1700.h
> index b7c666eef2..624ef61eda 100644
> --- a/include/hw/misc/aspeed_ast1700.h
> +++ b/include/hw/misc/aspeed_ast1700.h
> @@ -20,6 +20,7 @@
> #include "hw/misc/unimp.h"
>
> #define TYPE_ASPEED_AST1700 "aspeed.ast1700"
> +#define TYPE_ASPEED_AST1700_AST2700 "aspeed.ast1700-ast2700"
>
> OBJECT_DECLARE_SIMPLE_TYPE(AspeedAST1700SoCState, ASPEED_AST1700)
>
> diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
> index c0d8639bde..054864467d 100644
> --- a/hw/arm/aspeed_ast27x0.c
> +++ b/hw/arm/aspeed_ast27x0.c
> @@ -26,7 +26,6 @@
> #define AST2700_SOC_IO_SIZE 0x00FE0000
> #define AST2700_SOC_IOMEM_SIZE 0x01000000
> #define AST2700_SOC_DPMCU_SIZE 0x00040000
> -#define AST2700_SOC_LTPI_SIZE 0x01000000
>
> static const hwaddr aspeed_soc_ast2700_memmap[] = {
> [ASPEED_DEV_VBOOTROM] = 0x00000000,
> @@ -89,11 +88,14 @@ static const hwaddr aspeed_soc_ast2700_memmap[] = {
> [ASPEED_DEV_LTPI_CTRL1] = 0x14C34000,
> [ASPEED_DEV_LTPI_CTRL2] = 0x14C35000,
> [ASPEED_DEV_WDT] = 0x14C37000,
> + [ASPEED_DEV_LTPI_IO0] = 0x30000000,
> + [ASPEED_DEV_IOEXP0_INTCIO] = 0x30C18000,
> + [ASPEED_DEV_LTPI_IO1] = 0x50000000,
> + [ASPEED_DEV_IOEXP1_INTCIO] = 0x50C18000,
> [ASPEED_DEV_PCIE_MMIO0] = 0x60000000,
> [ASPEED_DEV_PCIE_MMIO1] = 0x80000000,
> [ASPEED_DEV_PCIE_MMIO2] = 0xA0000000,
> [ASPEED_DEV_SPI_BOOT] = 0x100000000,
> - [ASPEED_DEV_LTPI] = 0x300000000,
> [ASPEED_DEV_SDRAM] = 0x400000000,
> };
>
> @@ -549,10 +551,15 @@ static void aspeed_soc_ast2700_init(Object *obj)
> object_initialize_child(obj, "ltpi-ctrl[*]",
> &s->ltpi_ctrl[i], TYPE_ASPEED_LTPI);
> }
> +
> + for (i = 0; i < sc->ioexp_num; i++) {
> + /* AST1700 IOEXP */
> + object_initialize_child(obj, "ioexp[*]", &s->ioexp[i],
> + TYPE_ASPEED_AST1700_AST2700);
> + }
> +
> object_initialize_child(obj, "dpmcu", &s->dpmcu,
> TYPE_UNIMPLEMENTED_DEVICE);
> - object_initialize_child(obj, "ltpi", &s->ltpi,
> - TYPE_UNIMPLEMENTED_DEVICE);
> object_initialize_child(obj, "iomem", &s->iomem,
> TYPE_UNIMPLEMENTED_DEVICE);
> object_initialize_child(obj, "iomem0", &s->iomem0,
> @@ -1039,14 +1046,20 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
> }
> aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(ltpi_ctrl), 0, ltpi_base);
> }
> +
> + /* IO Expander */
> + for (i = 0; i < sc->ioexp_num; i++) {
> + if (!sysbus_realize(SYS_BUS_DEVICE(&s->ioexp[i]), errp)) {
> + return;
> + }
> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioexp[i]), 0,
> + sc->memmap[ASPEED_DEV_LTPI_IO0 + i]);
> + }
> +
> aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->dpmcu),
> "aspeed.dpmcu",
> sc->memmap[ASPEED_DEV_DPMCU],
> AST2700_SOC_DPMCU_SIZE);
> - aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->ltpi),
> - "aspeed.ltpi",
> - sc->memmap[ASPEED_DEV_LTPI],
> - AST2700_SOC_LTPI_SIZE);
> aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->iomem),
> "aspeed.io",
> sc->memmap[ASPEED_DEV_IOMEM],
> @@ -1112,6 +1125,7 @@ static void aspeed_soc_ast2700a1_class_init(ObjectClass *oc, const void *data)
> sc->macs_num = 3;
> sc->uarts_num = 13;
> sc->num_cpus = 4;
> + sc->ioexp_num = 2;
> sc->uarts_base = ASPEED_DEV_UART0;
> sc->irqmap = aspeed_soc_ast2700a1_irqmap;
> sc->memmap = aspeed_soc_ast2700_memmap;
> diff --git a/hw/misc/aspeed_ast1700.c b/hw/misc/aspeed_ast1700.c
> index bb05e392f4..3125bec795 100644
> --- a/hw/misc/aspeed_ast1700.c
> +++ b/hw/misc/aspeed_ast1700.c
> @@ -48,10 +48,16 @@ static const TypeInfo aspeed_ast1700_info = {
> .instance_init = aspeed_ast1700_instance_init,
> };
>
> +static const TypeInfo aspeed_ast1700_ast2700_info = {
> + .name = TYPE_ASPEED_AST1700_AST2700,
> + .parent = TYPE_ASPEED_AST1700,
> +};
> +
As discussed earlier, this type is not useful.
Thanks,
C.
>
> static void aspeed_ast1700_register_types(void)
> {
> type_register_static(&aspeed_ast1700_info);
> + type_register_static(&aspeed_ast1700_ast2700_info);
> }
>
> type_init(aspeed_ast1700_register_types);
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH v2 05/17] hw/arm/aspeed: Integrate interrupt controller for AST1700
2025-11-05 3:58 [PATCH v2 00/17] hw/arm/aspeed: AST1700 LTPI support and device hookups Kane Chen via
` (3 preceding siblings ...)
2025-11-05 3:58 ` [PATCH v2 04/17] hw/arm/aspeed: Integrate AST1700 device into AST27X0 Kane Chen via
@ 2025-11-05 3:58 ` Kane Chen via
2025-11-07 13:36 ` Cédric Le Goater
2025-11-05 3:58 ` [PATCH v2 06/17] hw/arm/aspeed: Attach LTPI controller to AST1700 model Kane Chen via
` (13 subsequent siblings)
18 siblings, 1 reply; 46+ messages in thread
From: Kane Chen via @ 2025-11-05 3:58 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, Kane-Chen-AS
From: Kane-Chen-AS <kane_chen@aspeedtech.com>
Connect the AST1700 interrupt lines to the GIC in AST27X0, enabling
the propagation of AST1700-originated interrupts to the host SoC.
This patch does not implement interrupt sources in AST1700 itself,
only the wiring into AST27X0.
Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
---
include/hw/arm/aspeed_soc.h | 2 +-
include/hw/intc/aspeed_intc.h | 2 ++
hw/arm/aspeed_ast27x0.c | 36 +++++++++++++++++++++
hw/intc/aspeed_intc.c | 60 +++++++++++++++++++++++++++++++++++
4 files changed, 99 insertions(+), 1 deletion(-)
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index 00cd8df038..66a6a073f6 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -143,7 +143,7 @@ struct Aspeed27x0SoCState {
AspeedSoCState parent;
ARMCPU cpu[ASPEED_CPUS_NUM];
- AspeedINTCState intc[2];
+ AspeedINTCState intc[4];
GICv3State gic;
MemoryRegion dram_empty;
};
diff --git a/include/hw/intc/aspeed_intc.h b/include/hw/intc/aspeed_intc.h
index 51288384a5..4565bbab84 100644
--- a/include/hw/intc/aspeed_intc.h
+++ b/include/hw/intc/aspeed_intc.h
@@ -15,6 +15,8 @@
#define TYPE_ASPEED_INTC "aspeed.intc"
#define TYPE_ASPEED_2700_INTC TYPE_ASPEED_INTC "-ast2700"
#define TYPE_ASPEED_2700_INTCIO TYPE_ASPEED_INTC "io-ast2700"
+#define TYPE_ASPEED_2700_INTCIOEXP1 TYPE_ASPEED_INTC "ast2700-ioexp1"
+#define TYPE_ASPEED_2700_INTCIOEXP2 TYPE_ASPEED_INTC "ast2700-ioexp2"
#define TYPE_ASPEED_2700SSP_INTC TYPE_ASPEED_INTC "-ast2700ssp"
#define TYPE_ASPEED_2700SSP_INTCIO TYPE_ASPEED_INTC "io-ast2700ssp"
#define TYPE_ASPEED_2700TSP_INTC TYPE_ASPEED_INTC "-ast2700tsp"
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 054864467d..11625e165a 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -505,6 +505,10 @@ static void aspeed_soc_ast2700_init(Object *obj)
object_initialize_child(obj, "intc", &a->intc[0], TYPE_ASPEED_2700_INTC);
object_initialize_child(obj, "intcio", &a->intc[1],
TYPE_ASPEED_2700_INTCIO);
+ object_initialize_child(obj, "intcioexp0", &a->intc[2],
+ TYPE_ASPEED_2700_INTCIOEXP1);
+ object_initialize_child(obj, "intcioexp1", &a->intc[3],
+ TYPE_ASPEED_2700_INTCIOEXP2);
snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname);
object_initialize_child(obj, "adc", &s->adc, typename);
@@ -701,6 +705,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
g_autofree char *name = NULL;
qemu_irq irq;
int uart;
+ int j;
AspeedLTPIState *ltpi_ctrl;
hwaddr ltpi_base;
@@ -746,6 +751,22 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->intc[1]), 0,
sc->memmap[ASPEED_DEV_INTCIO]);
+ /* INTCIOEXP0 */
+ if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[2]), errp)) {
+ return;
+ }
+
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->intc[2]), 0,
+ sc->memmap[ASPEED_DEV_IOEXP0_INTCIO]);
+
+ /* INTCIOEXP */
+ if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[3]), errp)) {
+ return;
+ }
+
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->intc[3]), 0,
+ sc->memmap[ASPEED_DEV_IOEXP1_INTCIO]);
+
/* irq sources -> orgates -> INTC */
for (i = 0; i < ic->num_inpins; i++) {
qdev_connect_gpio_out(DEVICE(&a->intc[0].orgates[i]), 0,
@@ -1054,6 +1075,21 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioexp[i]), 0,
sc->memmap[ASPEED_DEV_LTPI_IO0 + i]);
+
+ icio = ASPEED_INTC_GET_CLASS(&a->intc[2 + i]);
+ /* INTC2/3 internal: orgate[i] -> input[i] */
+ for (j = 0; j < icio->num_inpins; j++) {
+ irq = qdev_get_gpio_in(DEVICE(&a->intc[2 + i]), j);
+ qdev_connect_gpio_out(DEVICE(&a->intc[2 + i].orgates[j]), 0,
+ irq);
+ }
+
+ /* INTC2/3 output[i] -> INTC0.orgate[0].input[i] */
+ for (j = 0; j < icio->num_outpins; j++) {
+ irq = qdev_get_gpio_in(DEVICE(&a->intc[0].orgates[0]), j);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc[2 + i]), j,
+ irq);
+ }
}
aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->dpmcu),
diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c
index 5cd786dee6..a04005ee7c 100644
--- a/hw/intc/aspeed_intc.c
+++ b/hw/intc/aspeed_intc.c
@@ -924,6 +924,64 @@ static const TypeInfo aspeed_2700_intc_info = {
.class_init = aspeed_2700_intc_class_init,
};
+static AspeedINTCIRQ aspeed_2700_intcioexp2_irqs[ASPEED_INTC_MAX_INPINS] = {
+ {0, 8, 1, R_GICINT192_EN, R_GICINT192_STATUS},
+ {1, 9, 1, R_GICINT193_EN, R_GICINT193_STATUS},
+};
+
+static void aspeed_2700_intcioexp2_class_init(ObjectClass *klass,
+ const void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ AspeedINTCClass *aic = ASPEED_INTC_CLASS(klass);
+
+ dc->desc = "ASPEED 2700 IOEXP2 INTC Controller";
+ aic->num_lines = 32;
+ aic->num_inpins = 2;
+ aic->num_outpins = 10;
+ aic->mem_size = 0x400;
+ aic->nr_regs = 0x58 >> 2;
+ aic->reg_offset = 0x100;
+ aic->reg_ops = &aspeed_intcio_ops;
+ aic->irq_table = aspeed_2700_intcioexp2_irqs;
+ aic->irq_table_count = ARRAY_SIZE(aspeed_2700_intcioexp2_irqs);
+}
+
+static const TypeInfo aspeed_2700_intcioexp2_info = {
+ .name = TYPE_ASPEED_2700_INTCIOEXP2,
+ .parent = TYPE_ASPEED_INTC,
+ .class_init = aspeed_2700_intcioexp2_class_init,
+};
+
+static AspeedINTCIRQ aspeed_2700_intcioexp1_irqs[ASPEED_INTC_MAX_INPINS] = {
+ {0, 6, 1, R_GICINT192_EN, R_GICINT192_STATUS},
+ {1, 7, 1, R_GICINT193_EN, R_GICINT193_STATUS},
+};
+
+static void aspeed_2700_intcioexp1_class_init(ObjectClass *klass,
+ const void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ AspeedINTCClass *aic = ASPEED_INTC_CLASS(klass);
+
+ dc->desc = "ASPEED 2700 IOEXP1 INTC Controller";
+ aic->num_lines = 32;
+ aic->num_inpins = 2;
+ aic->num_outpins = 10;
+ aic->mem_size = 0x400;
+ aic->nr_regs = 0x58 >> 2;
+ aic->reg_offset = 0x100;
+ aic->reg_ops = &aspeed_intcio_ops;
+ aic->irq_table = aspeed_2700_intcioexp1_irqs;
+ aic->irq_table_count = ARRAY_SIZE(aspeed_2700_intcioexp1_irqs);
+}
+
+static const TypeInfo aspeed_2700_intcioexp1_info = {
+ .name = TYPE_ASPEED_2700_INTCIOEXP1,
+ .parent = TYPE_ASPEED_INTC,
+ .class_init = aspeed_2700_intcioexp1_class_init,
+};
+
static AspeedINTCIRQ aspeed_2700_intcio_irqs[ASPEED_INTC_MAX_INPINS] = {
{0, 0, 1, R_GICINT192_EN, R_GICINT192_STATUS},
{1, 1, 1, R_GICINT193_EN, R_GICINT193_STATUS},
@@ -1099,6 +1157,8 @@ static void aspeed_intc_register_types(void)
type_register_static(&aspeed_intc_info);
type_register_static(&aspeed_2700_intc_info);
type_register_static(&aspeed_2700_intcio_info);
+ type_register_static(&aspeed_2700_intcioexp1_info);
+ type_register_static(&aspeed_2700_intcioexp2_info);
type_register_static(&aspeed_2700ssp_intc_info);
type_register_static(&aspeed_2700ssp_intcio_info);
type_register_static(&aspeed_2700tsp_intc_info);
--
2.43.0
^ permalink raw reply related [flat|nested] 46+ messages in thread* Re: [PATCH v2 05/17] hw/arm/aspeed: Integrate interrupt controller for AST1700
2025-11-05 3:58 ` [PATCH v2 05/17] hw/arm/aspeed: Integrate interrupt controller for AST1700 Kane Chen via
@ 2025-11-07 13:36 ` Cédric Le Goater
2025-11-10 2:09 ` Kane Chen
0 siblings, 1 reply; 46+ messages in thread
From: Cédric Le Goater @ 2025-11-07 13:36 UTC (permalink / raw)
To: Kane Chen, Peter Maydell, Steven Lee, Troy Lee, Jamin Lin,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee
On 11/5/25 04:58, Kane Chen wrote:
> From: Kane-Chen-AS <kane_chen@aspeedtech.com>
>
> Connect the AST1700 interrupt lines to the GIC in AST27X0, enabling
> the propagation of AST1700-originated interrupts to the host SoC.
>
> This patch does not implement interrupt sources in AST1700 itself,
> only the wiring into AST27X0.
>
> Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
> ---
> include/hw/arm/aspeed_soc.h | 2 +-
> include/hw/intc/aspeed_intc.h | 2 ++
> hw/arm/aspeed_ast27x0.c | 36 +++++++++++++++++++++
> hw/intc/aspeed_intc.c | 60 +++++++++++++++++++++++++++++++++++
> 4 files changed, 99 insertions(+), 1 deletion(-)
>
> diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
> index 00cd8df038..66a6a073f6 100644
> --- a/include/hw/arm/aspeed_soc.h
> +++ b/include/hw/arm/aspeed_soc.h
> @@ -143,7 +143,7 @@ struct Aspeed27x0SoCState {
> AspeedSoCState parent;
>
> ARMCPU cpu[ASPEED_CPUS_NUM];
> - AspeedINTCState intc[2];
> + AspeedINTCState intc[4];
Please introduce an 'intcioexp1[2]' array instead.
> GICv3State gic;
> MemoryRegion dram_empty;
> };
> diff --git a/include/hw/intc/aspeed_intc.h b/include/hw/intc/aspeed_intc.h
> index 51288384a5..4565bbab84 100644
> --- a/include/hw/intc/aspeed_intc.h
> +++ b/include/hw/intc/aspeed_intc.h
> @@ -15,6 +15,8 @@
> #define TYPE_ASPEED_INTC "aspeed.intc"
> #define TYPE_ASPEED_2700_INTC TYPE_ASPEED_INTC "-ast2700"
> #define TYPE_ASPEED_2700_INTCIO TYPE_ASPEED_INTC "io-ast2700"
> +#define TYPE_ASPEED_2700_INTCIOEXP1 TYPE_ASPEED_INTC "ast2700-ioexp1"
> +#define TYPE_ASPEED_2700_INTCIOEXP2 TYPE_ASPEED_INTC "ast2700-ioexp2"
> #define TYPE_ASPEED_2700SSP_INTC TYPE_ASPEED_INTC "-ast2700ssp"
> #define TYPE_ASPEED_2700SSP_INTCIO TYPE_ASPEED_INTC "io-ast2700ssp"
> #define TYPE_ASPEED_2700TSP_INTC TYPE_ASPEED_INTC "-ast2700tsp"
> diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
> index 054864467d..11625e165a 100644
> --- a/hw/arm/aspeed_ast27x0.c
> +++ b/hw/arm/aspeed_ast27x0.c
> @@ -505,6 +505,10 @@ static void aspeed_soc_ast2700_init(Object *obj)
> object_initialize_child(obj, "intc", &a->intc[0], TYPE_ASPEED_2700_INTC);
> object_initialize_child(obj, "intcio", &a->intc[1],
> TYPE_ASPEED_2700_INTCIO);
> + object_initialize_child(obj, "intcioexp0", &a->intc[2],
> + TYPE_ASPEED_2700_INTCIOEXP1);
> + object_initialize_child(obj, "intcioexp1", &a->intc[3],
> + TYPE_ASPEED_2700_INTCIOEXP2);
>
> snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname);
> object_initialize_child(obj, "adc", &s->adc, typename);
> @@ -701,6 +705,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
> g_autofree char *name = NULL;
> qemu_irq irq;
> int uart;
> + int j;
This index variable can be local to the loop.
> AspeedLTPIState *ltpi_ctrl;
> hwaddr ltpi_base;
>
> @@ -746,6 +751,22 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
> aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->intc[1]), 0,
> sc->memmap[ASPEED_DEV_INTCIO]);
>
> + /* INTCIOEXP0 */
> + if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[2]), errp)) {
> + return;
> + }
> +
> + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->intc[2]), 0,
> + sc->memmap[ASPEED_DEV_IOEXP0_INTCIO]);
> +
> + /* INTCIOEXP */
> + if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[3]), errp)) {
> + return;
> + }
> +
> + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->intc[3]), 0,
> + sc->memmap[ASPEED_DEV_IOEXP1_INTCIO]);
> +
> /* irq sources -> orgates -> INTC */
> for (i = 0; i < ic->num_inpins; i++) {
> qdev_connect_gpio_out(DEVICE(&a->intc[0].orgates[i]), 0,
> @@ -1054,6 +1075,21 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
> }
> sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioexp[i]), 0,
> sc->memmap[ASPEED_DEV_LTPI_IO0 + i]);
> +
> + icio = ASPEED_INTC_GET_CLASS(&a->intc[2 + i]);
> + /* INTC2/3 internal: orgate[i] -> input[i] */
> + for (j = 0; j < icio->num_inpins; j++) {
> + irq = qdev_get_gpio_in(DEVICE(&a->intc[2 + i]), j);
> + qdev_connect_gpio_out(DEVICE(&a->intc[2 + i].orgates[j]), 0,
> + irq);
> + }
> +
> + /* INTC2/3 output[i] -> INTC0.orgate[0].input[i] */
> + for (j = 0; j < icio->num_outpins; j++) {
> + irq = qdev_get_gpio_in(DEVICE(&a->intc[0].orgates[0]), j);
> + sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc[2 + i]), j,
> + irq);
> + }
> }
>
> aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->dpmcu),
> diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c
> index 5cd786dee6..a04005ee7c 100644
> --- a/hw/intc/aspeed_intc.c
> +++ b/hw/intc/aspeed_intc.c
> @@ -924,6 +924,64 @@ static const TypeInfo aspeed_2700_intc_info = {
> .class_init = aspeed_2700_intc_class_init,
> };
>
> +static AspeedINTCIRQ aspeed_2700_intcioexp2_irqs[ASPEED_INTC_MAX_INPINS] = {
> + {0, 8, 1, R_GICINT192_EN, R_GICINT192_STATUS},
> + {1, 9, 1, R_GICINT193_EN, R_GICINT193_STATUS},
> +};
> +
> +static void aspeed_2700_intcioexp2_class_init(ObjectClass *klass,
> + const void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> + AspeedINTCClass *aic = ASPEED_INTC_CLASS(klass);
> +
> + dc->desc = "ASPEED 2700 IOEXP2 INTC Controller";
> + aic->num_lines = 32;
> + aic->num_inpins = 2;
> + aic->num_outpins = 10;
> + aic->mem_size = 0x400;
> + aic->nr_regs = 0x58 >> 2;
> + aic->reg_offset = 0x100;
> + aic->reg_ops = &aspeed_intcio_ops;
> + aic->irq_table = aspeed_2700_intcioexp2_irqs;
> + aic->irq_table_count = ARRAY_SIZE(aspeed_2700_intcioexp2_irqs);
> +}
> +
> +static const TypeInfo aspeed_2700_intcioexp2_info = {
> + .name = TYPE_ASPEED_2700_INTCIOEXP2,
> + .parent = TYPE_ASPEED_INTC,
> + .class_init = aspeed_2700_intcioexp2_class_init,
> +};
> +
> +static AspeedINTCIRQ aspeed_2700_intcioexp1_irqs[ASPEED_INTC_MAX_INPINS] = {
> + {0, 6, 1, R_GICINT192_EN, R_GICINT192_STATUS},
> + {1, 7, 1, R_GICINT193_EN, R_GICINT193_STATUS},
> +};
> +
> +static void aspeed_2700_intcioexp1_class_init(ObjectClass *klass,
> + const void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> + AspeedINTCClass *aic = ASPEED_INTC_CLASS(klass);
> +
> + dc->desc = "ASPEED 2700 IOEXP1 INTC Controller";
> + aic->num_lines = 32;
> + aic->num_inpins = 2;
> + aic->num_outpins = 10;
> + aic->mem_size = 0x400;
> + aic->nr_regs = 0x58 >> 2;
> + aic->reg_offset = 0x100;
> + aic->reg_ops = &aspeed_intcio_ops;
> + aic->irq_table = aspeed_2700_intcioexp1_irqs;
> + aic->irq_table_count = ARRAY_SIZE(aspeed_2700_intcioexp1_irqs);
> +}
> +
> +static const TypeInfo aspeed_2700_intcioexp1_info = {
> + .name = TYPE_ASPEED_2700_INTCIOEXP1,
> + .parent = TYPE_ASPEED_INTC,
> + .class_init = aspeed_2700_intcioexp1_class_init,
> +};
> +
> static AspeedINTCIRQ aspeed_2700_intcio_irqs[ASPEED_INTC_MAX_INPINS] = {
> {0, 0, 1, R_GICINT192_EN, R_GICINT192_STATUS},
> {1, 1, 1, R_GICINT193_EN, R_GICINT193_STATUS},
> @@ -1099,6 +1157,8 @@ static void aspeed_intc_register_types(void)
> type_register_static(&aspeed_intc_info);
> type_register_static(&aspeed_2700_intc_info);
> type_register_static(&aspeed_2700_intcio_info);
> + type_register_static(&aspeed_2700_intcioexp1_info);
> + type_register_static(&aspeed_2700_intcioexp2_info);
> type_register_static(&aspeed_2700ssp_intc_info);
> type_register_static(&aspeed_2700ssp_intcio_info);
> type_register_static(&aspeed_2700tsp_intc_info);
Thanks,
C.
^ permalink raw reply [flat|nested] 46+ messages in thread* RE: [PATCH v2 05/17] hw/arm/aspeed: Integrate interrupt controller for AST1700
2025-11-07 13:36 ` Cédric Le Goater
@ 2025-11-10 2:09 ` Kane Chen
0 siblings, 0 replies; 46+ messages in thread
From: Kane Chen @ 2025-11-10 2:09 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee
Hi Cédric,
Thanks for reviewing. I’ll update the code based on your feedback.
Best Regards,
Kane
> -----Original Message-----
> From: Cédric Le Goater <clg@kaod.org>
> Sent: Friday, November 7, 2025 9:36 PM
> To: Kane Chen <kane_chen@aspeedtech.com>; Peter Maydell
> <peter.maydell@linaro.org>; Steven Lee <steven_lee@aspeedtech.com>; Troy
> Lee <leetroy@gmail.com>; Jamin Lin <jamin_lin@aspeedtech.com>; Andrew
> Jeffery <andrew@codeconstruct.com.au>; Joel Stanley <joel@jms.id.au>;
> open list:ASPEED BMCs <qemu-arm@nongnu.org>; open list:All patches CC
> here <qemu-devel@nongnu.org>
> Cc: Troy Lee <troy_lee@aspeedtech.com>
> Subject: Re: [PATCH v2 05/17] hw/arm/aspeed: Integrate interrupt controller
> for AST1700
>
> On 11/5/25 04:58, Kane Chen wrote:
> > From: Kane-Chen-AS <kane_chen@aspeedtech.com>
> >
> > Connect the AST1700 interrupt lines to the GIC in AST27X0, enabling
> > the propagation of AST1700-originated interrupts to the host SoC.
> >
> > This patch does not implement interrupt sources in AST1700 itself,
> > only the wiring into AST27X0.
> >
> > Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
> > ---
> > include/hw/arm/aspeed_soc.h | 2 +-
> > include/hw/intc/aspeed_intc.h | 2 ++
> > hw/arm/aspeed_ast27x0.c | 36 +++++++++++++++++++++
> > hw/intc/aspeed_intc.c | 60
> +++++++++++++++++++++++++++++++++++
> > 4 files changed, 99 insertions(+), 1 deletion(-)
> >
> > diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
> > index 00cd8df038..66a6a073f6 100644
> > --- a/include/hw/arm/aspeed_soc.h
> > +++ b/include/hw/arm/aspeed_soc.h
> > @@ -143,7 +143,7 @@ struct Aspeed27x0SoCState {
> > AspeedSoCState parent;
> >
> > ARMCPU cpu[ASPEED_CPUS_NUM];
> > - AspeedINTCState intc[2];
> > + AspeedINTCState intc[4];
>
> Please introduce an 'intcioexp1[2]' array instead.
>
> > GICv3State gic;
> > MemoryRegion dram_empty;
> > };
> > diff --git a/include/hw/intc/aspeed_intc.h
> > b/include/hw/intc/aspeed_intc.h index 51288384a5..4565bbab84 100644
> > --- a/include/hw/intc/aspeed_intc.h
> > +++ b/include/hw/intc/aspeed_intc.h
> > @@ -15,6 +15,8 @@
> > #define TYPE_ASPEED_INTC "aspeed.intc"
> > #define TYPE_ASPEED_2700_INTC TYPE_ASPEED_INTC "-ast2700"
> > #define TYPE_ASPEED_2700_INTCIO TYPE_ASPEED_INTC "io-ast2700"
> > +#define TYPE_ASPEED_2700_INTCIOEXP1 TYPE_ASPEED_INTC
> "ast2700-ioexp1"
> > +#define TYPE_ASPEED_2700_INTCIOEXP2 TYPE_ASPEED_INTC
> "ast2700-ioexp2"
> > #define TYPE_ASPEED_2700SSP_INTC TYPE_ASPEED_INTC "-ast2700ssp"
> > #define TYPE_ASPEED_2700SSP_INTCIO TYPE_ASPEED_INTC
> "io-ast2700ssp"
> > #define TYPE_ASPEED_2700TSP_INTC TYPE_ASPEED_INTC "-ast2700tsp"
> > diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index
> > 054864467d..11625e165a 100644
> > --- a/hw/arm/aspeed_ast27x0.c
> > +++ b/hw/arm/aspeed_ast27x0.c
> > @@ -505,6 +505,10 @@ static void aspeed_soc_ast2700_init(Object *obj)
> > object_initialize_child(obj, "intc", &a->intc[0],
> TYPE_ASPEED_2700_INTC);
> > object_initialize_child(obj, "intcio", &a->intc[1],
> > TYPE_ASPEED_2700_INTCIO);
> > + object_initialize_child(obj, "intcioexp0", &a->intc[2],
> > + TYPE_ASPEED_2700_INTCIOEXP1);
> > + object_initialize_child(obj, "intcioexp1", &a->intc[3],
> > + TYPE_ASPEED_2700_INTCIOEXP2);
> >
> > snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname);
> > object_initialize_child(obj, "adc", &s->adc, typename); @@
> > -701,6 +705,7 @@ static void aspeed_soc_ast2700_realize(DeviceState
> *dev, Error **errp)
> > g_autofree char *name = NULL;
> > qemu_irq irq;
> > int uart;
> > + int j;
>
> This index variable can be local to the loop.
>
> > AspeedLTPIState *ltpi_ctrl;
> > hwaddr ltpi_base;
> >
> > @@ -746,6 +751,22 @@ static void
> aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
> > aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->intc[1]), 0,
> > sc->memmap[ASPEED_DEV_INTCIO]);
> >
> > + /* INTCIOEXP0 */
> > + if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[2]), errp)) {
> > + return;
> > + }
> > +
> > + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->intc[2]), 0,
> > + sc->memmap[ASPEED_DEV_IOEXP0_INTCIO]);
> > +
> > + /* INTCIOEXP */
> > + if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[3]), errp)) {
> > + return;
> > + }
> > +
> > + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->intc[3]), 0,
> > + sc->memmap[ASPEED_DEV_IOEXP1_INTCIO]);
> > +
> > /* irq sources -> orgates -> INTC */
> > for (i = 0; i < ic->num_inpins; i++) {
> > qdev_connect_gpio_out(DEVICE(&a->intc[0].orgates[i]), 0, @@
> > -1054,6 +1075,21 @@ static void aspeed_soc_ast2700_realize(DeviceState
> *dev, Error **errp)
> > }
> > sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioexp[i]), 0,
> > sc->memmap[ASPEED_DEV_LTPI_IO0 + i]);
> > +
> > + icio = ASPEED_INTC_GET_CLASS(&a->intc[2 + i]);
> > + /* INTC2/3 internal: orgate[i] -> input[i] */
> > + for (j = 0; j < icio->num_inpins; j++) {
> > + irq = qdev_get_gpio_in(DEVICE(&a->intc[2 + i]), j);
> > + qdev_connect_gpio_out(DEVICE(&a->intc[2 + i].orgates[j]),
> 0,
> > + irq);
> > + }
> > +
> > + /* INTC2/3 output[i] -> INTC0.orgate[0].input[i] */
> > + for (j = 0; j < icio->num_outpins; j++) {
> > + irq = qdev_get_gpio_in(DEVICE(&a->intc[0].orgates[0]), j);
> > + sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc[2 + i]), j,
> > + irq);
> > + }
> > }
> >
> > aspeed_mmio_map_unimplemented(s->memory,
> > SYS_BUS_DEVICE(&s->dpmcu), diff --git a/hw/intc/aspeed_intc.c
> > b/hw/intc/aspeed_intc.c index 5cd786dee6..a04005ee7c 100644
> > --- a/hw/intc/aspeed_intc.c
> > +++ b/hw/intc/aspeed_intc.c
> > @@ -924,6 +924,64 @@ static const TypeInfo aspeed_2700_intc_info = {
> > .class_init = aspeed_2700_intc_class_init,
> > };
> >
> > +static AspeedINTCIRQ
> aspeed_2700_intcioexp2_irqs[ASPEED_INTC_MAX_INPINS] = {
> > + {0, 8, 1, R_GICINT192_EN, R_GICINT192_STATUS},
> > + {1, 9, 1, R_GICINT193_EN, R_GICINT193_STATUS}, };
> > +
> > +static void aspeed_2700_intcioexp2_class_init(ObjectClass *klass,
> > + const void *data)
> {
> > + DeviceClass *dc = DEVICE_CLASS(klass);
> > + AspeedINTCClass *aic = ASPEED_INTC_CLASS(klass);
> > +
> > + dc->desc = "ASPEED 2700 IOEXP2 INTC Controller";
> > + aic->num_lines = 32;
> > + aic->num_inpins = 2;
> > + aic->num_outpins = 10;
> > + aic->mem_size = 0x400;
> > + aic->nr_regs = 0x58 >> 2;
> > + aic->reg_offset = 0x100;
> > + aic->reg_ops = &aspeed_intcio_ops;
> > + aic->irq_table = aspeed_2700_intcioexp2_irqs;
> > + aic->irq_table_count = ARRAY_SIZE(aspeed_2700_intcioexp2_irqs);
> > +}
> > +
> > +static const TypeInfo aspeed_2700_intcioexp2_info = {
> > + .name = TYPE_ASPEED_2700_INTCIOEXP2,
> > + .parent = TYPE_ASPEED_INTC,
> > + .class_init = aspeed_2700_intcioexp2_class_init,
> > +};
> > +
> > +static AspeedINTCIRQ
> aspeed_2700_intcioexp1_irqs[ASPEED_INTC_MAX_INPINS] = {
> > + {0, 6, 1, R_GICINT192_EN, R_GICINT192_STATUS},
> > + {1, 7, 1, R_GICINT193_EN, R_GICINT193_STATUS}, };
> > +
> > +static void aspeed_2700_intcioexp1_class_init(ObjectClass *klass,
> > + const void *data)
> {
> > + DeviceClass *dc = DEVICE_CLASS(klass);
> > + AspeedINTCClass *aic = ASPEED_INTC_CLASS(klass);
> > +
> > + dc->desc = "ASPEED 2700 IOEXP1 INTC Controller";
> > + aic->num_lines = 32;
> > + aic->num_inpins = 2;
> > + aic->num_outpins = 10;
> > + aic->mem_size = 0x400;
> > + aic->nr_regs = 0x58 >> 2;
> > + aic->reg_offset = 0x100;
> > + aic->reg_ops = &aspeed_intcio_ops;
> > + aic->irq_table = aspeed_2700_intcioexp1_irqs;
> > + aic->irq_table_count = ARRAY_SIZE(aspeed_2700_intcioexp1_irqs);
> > +}
> > +
> > +static const TypeInfo aspeed_2700_intcioexp1_info = {
> > + .name = TYPE_ASPEED_2700_INTCIOEXP1,
> > + .parent = TYPE_ASPEED_INTC,
> > + .class_init = aspeed_2700_intcioexp1_class_init,
> > +};
> > +
> > static AspeedINTCIRQ
> aspeed_2700_intcio_irqs[ASPEED_INTC_MAX_INPINS] = {
> > {0, 0, 1, R_GICINT192_EN, R_GICINT192_STATUS},
> > {1, 1, 1, R_GICINT193_EN, R_GICINT193_STATUS}, @@ -1099,6
> > +1157,8 @@ static void aspeed_intc_register_types(void)
> > type_register_static(&aspeed_intc_info);
> > type_register_static(&aspeed_2700_intc_info);
> > type_register_static(&aspeed_2700_intcio_info);
> > + type_register_static(&aspeed_2700_intcioexp1_info);
> > + type_register_static(&aspeed_2700_intcioexp2_info);
> > type_register_static(&aspeed_2700ssp_intc_info);
> > type_register_static(&aspeed_2700ssp_intcio_info);
> > type_register_static(&aspeed_2700tsp_intc_info);
>
> Thanks,
>
> C.
>
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH v2 06/17] hw/arm/aspeed: Attach LTPI controller to AST1700 model
2025-11-05 3:58 [PATCH v2 00/17] hw/arm/aspeed: AST1700 LTPI support and device hookups Kane Chen via
` (4 preceding siblings ...)
2025-11-05 3:58 ` [PATCH v2 05/17] hw/arm/aspeed: Integrate interrupt controller for AST1700 Kane Chen via
@ 2025-11-05 3:58 ` Kane Chen via
2025-11-07 13:36 ` Cédric Le Goater
2025-11-05 3:58 ` [PATCH v2 07/17] hw/arm/aspeed: Attach UART device " Kane Chen via
` (12 subsequent siblings)
18 siblings, 1 reply; 46+ messages in thread
From: Kane Chen via @ 2025-11-05 3:58 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, Kane-Chen-AS
From: Kane-Chen-AS <kane_chen@aspeedtech.com>
Connect the LTPI controller to the AST1700 model by mapping its MMIO
region and wiring its interrupt line.
Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
---
include/hw/misc/aspeed_ast1700.h | 2 ++
hw/misc/aspeed_ast1700.c | 21 +++++++++++++++++++++
2 files changed, 23 insertions(+)
diff --git a/include/hw/misc/aspeed_ast1700.h b/include/hw/misc/aspeed_ast1700.h
index 624ef61eda..c2bea11346 100644
--- a/include/hw/misc/aspeed_ast1700.h
+++ b/include/hw/misc/aspeed_ast1700.h
@@ -28,6 +28,8 @@ struct AspeedAST1700SoCState {
SysBusDevice parent_obj;
MemoryRegion iomem;
+
+ AspeedLTPIState ltpi;
};
#endif /* ASPEED_AST1700_H */
diff --git a/hw/misc/aspeed_ast1700.c b/hw/misc/aspeed_ast1700.c
index 3125bec795..0ca2b90ff0 100644
--- a/hw/misc/aspeed_ast1700.c
+++ b/hw/misc/aspeed_ast1700.c
@@ -16,6 +16,14 @@
#include "hw/misc/aspeed_ast1700.h"
#define AST2700_SOC_LTPI_SIZE 0x01000000
+
+enum {
+ ASPEED_AST1700_DEV_LTPI_CTRL,
+};
+
+static const hwaddr aspeed_ast1700_io_memmap[] = {
+ [ASPEED_AST1700_DEV_LTPI_CTRL] = 0x00C34000,
+};
static void aspeed_ast1700_realize(DeviceState *dev, Error **errp)
{
AspeedAST1700SoCState *s = ASPEED_AST1700(dev);
@@ -26,10 +34,23 @@ static void aspeed_ast1700_realize(DeviceState *dev, Error **errp)
AST2700_SOC_LTPI_SIZE);
sysbus_init_mmio(sbd, &s->iomem);
+ /* LTPI controller */
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->ltpi), errp)) {
+ return;
+ }
+ memory_region_add_subregion(&s->iomem,
+ aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_LTPI_CTRL],
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->ltpi), 0));
}
static void aspeed_ast1700_instance_init(Object *obj)
{
+ AspeedAST1700SoCState *s = ASPEED_AST1700(obj);
+
+ /* LTPI controller */
+ object_initialize_child(obj, "ltpi-ctrl",
+ &s->ltpi, TYPE_ASPEED_LTPI);
+
return;
}
--
2.43.0
^ permalink raw reply related [flat|nested] 46+ messages in thread* Re: [PATCH v2 06/17] hw/arm/aspeed: Attach LTPI controller to AST1700 model
2025-11-05 3:58 ` [PATCH v2 06/17] hw/arm/aspeed: Attach LTPI controller to AST1700 model Kane Chen via
@ 2025-11-07 13:36 ` Cédric Le Goater
2025-11-10 2:05 ` Kane Chen
0 siblings, 1 reply; 46+ messages in thread
From: Cédric Le Goater @ 2025-11-07 13:36 UTC (permalink / raw)
To: Kane Chen, Peter Maydell, Steven Lee, Troy Lee, Jamin Lin,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee
On 11/5/25 04:58, Kane Chen wrote:
> From: Kane-Chen-AS <kane_chen@aspeedtech.com>
>
> Connect the LTPI controller to the AST1700 model by mapping its MMIO
> region and wiring its interrupt line.
>
> Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
> ---
> include/hw/misc/aspeed_ast1700.h | 2 ++
> hw/misc/aspeed_ast1700.c | 21 +++++++++++++++++++++
> 2 files changed, 23 insertions(+)
>
> diff --git a/include/hw/misc/aspeed_ast1700.h b/include/hw/misc/aspeed_ast1700.h
> index 624ef61eda..c2bea11346 100644
> --- a/include/hw/misc/aspeed_ast1700.h
> +++ b/include/hw/misc/aspeed_ast1700.h
> @@ -28,6 +28,8 @@ struct AspeedAST1700SoCState {
> SysBusDevice parent_obj;
>
> MemoryRegion iomem;
> +
> + AspeedLTPIState ltpi;
> };
>
> #endif /* ASPEED_AST1700_H */
> diff --git a/hw/misc/aspeed_ast1700.c b/hw/misc/aspeed_ast1700.c
> index 3125bec795..0ca2b90ff0 100644
> --- a/hw/misc/aspeed_ast1700.c
> +++ b/hw/misc/aspeed_ast1700.c
> @@ -16,6 +16,14 @@
> #include "hw/misc/aspeed_ast1700.h"
>
> #define AST2700_SOC_LTPI_SIZE 0x01000000
> +
> +enum {
> + ASPEED_AST1700_DEV_LTPI_CTRL,
> +};
> +
> +static const hwaddr aspeed_ast1700_io_memmap[] = {
> + [ASPEED_AST1700_DEV_LTPI_CTRL] = 0x00C34000,
> +};
> static void aspeed_ast1700_realize(DeviceState *dev, Error **errp)
> {
> AspeedAST1700SoCState *s = ASPEED_AST1700(dev);
> @@ -26,10 +34,23 @@ static void aspeed_ast1700_realize(DeviceState *dev, Error **errp)
> AST2700_SOC_LTPI_SIZE);
> sysbus_init_mmio(sbd, &s->iomem);
>
> + /* LTPI controller */
> + if (!sysbus_realize(SYS_BUS_DEVICE(&s->ltpi), errp)) {
> + return;
> + }
> + memory_region_add_subregion(&s->iomem,
> + aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_LTPI_CTRL],
> + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->ltpi), 0));
> }
>
> static void aspeed_ast1700_instance_init(Object *obj)
> {
> + AspeedAST1700SoCState *s = ASPEED_AST1700(obj);
> +
> + /* LTPI controller */
> + object_initialize_child(obj, "ltpi-ctrl",
> + &s->ltpi, TYPE_ASPEED_LTPI);
> +
> return;
> }
>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Thanks,
C.
^ permalink raw reply [flat|nested] 46+ messages in thread* RE: [PATCH v2 06/17] hw/arm/aspeed: Attach LTPI controller to AST1700 model
2025-11-07 13:36 ` Cédric Le Goater
@ 2025-11-10 2:05 ` Kane Chen
0 siblings, 0 replies; 46+ messages in thread
From: Kane Chen @ 2025-11-10 2:05 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee
Hi Cédric,
Thanks for reviewing.
Best Regards,
Kane
> -----Original Message-----
> From: Cédric Le Goater <clg@kaod.org>
> Sent: Friday, November 7, 2025 9:37 PM
> To: Kane Chen <kane_chen@aspeedtech.com>; Peter Maydell
> <peter.maydell@linaro.org>; Steven Lee <steven_lee@aspeedtech.com>; Troy
> Lee <leetroy@gmail.com>; Jamin Lin <jamin_lin@aspeedtech.com>; Andrew
> Jeffery <andrew@codeconstruct.com.au>; Joel Stanley <joel@jms.id.au>;
> open list:ASPEED BMCs <qemu-arm@nongnu.org>; open list:All patches CC
> here <qemu-devel@nongnu.org>
> Cc: Troy Lee <troy_lee@aspeedtech.com>
> Subject: Re: [PATCH v2 06/17] hw/arm/aspeed: Attach LTPI controller to
> AST1700 model
>
> On 11/5/25 04:58, Kane Chen wrote:
> > From: Kane-Chen-AS <kane_chen@aspeedtech.com>
> >
> > Connect the LTPI controller to the AST1700 model by mapping its MMIO
> > region and wiring its interrupt line.
> >
> > Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
> > ---
> > include/hw/misc/aspeed_ast1700.h | 2 ++
> > hw/misc/aspeed_ast1700.c | 21 +++++++++++++++++++++
> > 2 files changed, 23 insertions(+)
> >
> > diff --git a/include/hw/misc/aspeed_ast1700.h
> > b/include/hw/misc/aspeed_ast1700.h
> > index 624ef61eda..c2bea11346 100644
> > --- a/include/hw/misc/aspeed_ast1700.h
> > +++ b/include/hw/misc/aspeed_ast1700.h
> > @@ -28,6 +28,8 @@ struct AspeedAST1700SoCState {
> > SysBusDevice parent_obj;
> >
> > MemoryRegion iomem;
> > +
> > + AspeedLTPIState ltpi;
> > };
> >
> > #endif /* ASPEED_AST1700_H */
> > diff --git a/hw/misc/aspeed_ast1700.c b/hw/misc/aspeed_ast1700.c index
> > 3125bec795..0ca2b90ff0 100644
> > --- a/hw/misc/aspeed_ast1700.c
> > +++ b/hw/misc/aspeed_ast1700.c
> > @@ -16,6 +16,14 @@
> > #include "hw/misc/aspeed_ast1700.h"
> >
> > #define AST2700_SOC_LTPI_SIZE 0x01000000
> > +
> > +enum {
> > + ASPEED_AST1700_DEV_LTPI_CTRL,
> > +};
> > +
> > +static const hwaddr aspeed_ast1700_io_memmap[] = {
> > + [ASPEED_AST1700_DEV_LTPI_CTRL] = 0x00C34000, };
> > static void aspeed_ast1700_realize(DeviceState *dev, Error **errp)
> > {
> > AspeedAST1700SoCState *s = ASPEED_AST1700(dev); @@ -26,10
> +34,23
> > @@ static void aspeed_ast1700_realize(DeviceState *dev, Error **errp)
> > AST2700_SOC_LTPI_SIZE);
> > sysbus_init_mmio(sbd, &s->iomem);
> >
> > + /* LTPI controller */
> > + if (!sysbus_realize(SYS_BUS_DEVICE(&s->ltpi), errp)) {
> > + return;
> > + }
> > + memory_region_add_subregion(&s->iomem,
> > +
> aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_LTPI_CTRL],
> > +
> > + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->ltpi), 0));
> > }
> >
> > static void aspeed_ast1700_instance_init(Object *obj)
> > {
> > + AspeedAST1700SoCState *s = ASPEED_AST1700(obj);
> > +
> > + /* LTPI controller */
> > + object_initialize_child(obj, "ltpi-ctrl",
> > + &s->ltpi, TYPE_ASPEED_LTPI);
> > +
> > return;
> > }
> >
>
>
> Reviewed-by: Cédric Le Goater <clg@redhat.com>
>
> Thanks,
>
> C.
>
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH v2 07/17] hw/arm/aspeed: Attach UART device to AST1700 model
2025-11-05 3:58 [PATCH v2 00/17] hw/arm/aspeed: AST1700 LTPI support and device hookups Kane Chen via
` (5 preceding siblings ...)
2025-11-05 3:58 ` [PATCH v2 06/17] hw/arm/aspeed: Attach LTPI controller to AST1700 model Kane Chen via
@ 2025-11-05 3:58 ` Kane Chen via
2025-11-10 16:04 ` Cédric Le Goater
2025-11-05 3:58 ` [PATCH v2 08/17] hw/arm/aspeed: Attach SRAM " Kane Chen via
` (11 subsequent siblings)
18 siblings, 1 reply; 46+ messages in thread
From: Kane Chen via @ 2025-11-05 3:58 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, Kane-Chen-AS
From: Kane-Chen-AS <kane_chen@aspeedtech.com>
Connect the UART controller to the AST1700 model by mapping its MMIO
region.
Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
---
include/hw/misc/aspeed_ast1700.h | 2 ++
hw/arm/aspeed_ast27x0.c | 2 ++
hw/misc/aspeed_ast1700.c | 26 ++++++++++++++++++++++++++
3 files changed, 30 insertions(+)
diff --git a/include/hw/misc/aspeed_ast1700.h b/include/hw/misc/aspeed_ast1700.h
index c2bea11346..e105ceb027 100644
--- a/include/hw/misc/aspeed_ast1700.h
+++ b/include/hw/misc/aspeed_ast1700.h
@@ -28,8 +28,10 @@ struct AspeedAST1700SoCState {
SysBusDevice parent_obj;
MemoryRegion iomem;
+ hwaddr mapped_base;
AspeedLTPIState ltpi;
+ SerialMM uart;
};
#endif /* ASPEED_AST1700_H */
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 11625e165a..7151feb35d 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -1070,6 +1070,8 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
/* IO Expander */
for (i = 0; i < sc->ioexp_num; i++) {
+ qdev_prop_set_uint64(DEVICE(&s->ioexp[i]), "mapped-base",
+ sc->memmap[ASPEED_DEV_LTPI_IO0 + i]);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->ioexp[i]), errp)) {
return;
}
diff --git a/hw/misc/aspeed_ast1700.c b/hw/misc/aspeed_ast1700.c
index 0ca2b90ff0..1c2d367cdb 100644
--- a/hw/misc/aspeed_ast1700.c
+++ b/hw/misc/aspeed_ast1700.c
@@ -18,22 +18,39 @@
#define AST2700_SOC_LTPI_SIZE 0x01000000
enum {
+ ASPEED_AST1700_DEV_UART12,
ASPEED_AST1700_DEV_LTPI_CTRL,
};
static const hwaddr aspeed_ast1700_io_memmap[] = {
+ [ASPEED_AST1700_DEV_UART12] = 0x00C33B00,
[ASPEED_AST1700_DEV_LTPI_CTRL] = 0x00C34000,
};
static void aspeed_ast1700_realize(DeviceState *dev, Error **errp)
{
AspeedAST1700SoCState *s = ASPEED_AST1700(dev);
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+ hwaddr uart_base;
/* Occupy memory space for all controllers in AST1700 */
memory_region_init(&s->iomem, OBJECT(s), TYPE_ASPEED_AST1700,
AST2700_SOC_LTPI_SIZE);
sysbus_init_mmio(sbd, &s->iomem);
+ /* UART */
+ uart_base = s->mapped_base +
+ aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_UART12];
+ qdev_prop_set_uint8(DEVICE(&s->uart), "regshift", 2);
+ qdev_prop_set_uint32(DEVICE(&s->uart), "baudbase", 38400);
+ qdev_set_legacy_instance_id(DEVICE(&s->uart), uart_base, 2);
+ qdev_prop_set_uint8(DEVICE(&s->uart), "endianness", DEVICE_LITTLE_ENDIAN);
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart), errp)) {
+ return;
+ }
+ memory_region_add_subregion(&s->iomem,
+ aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_UART12],
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart), 0));
+
/* LTPI controller */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->ltpi), errp)) {
return;
@@ -47,6 +64,10 @@ static void aspeed_ast1700_instance_init(Object *obj)
{
AspeedAST1700SoCState *s = ASPEED_AST1700(obj);
+ /* UART */
+ object_initialize_child(obj, "uart[*]", &s->uart,
+ TYPE_SERIAL_MM);
+
/* LTPI controller */
object_initialize_child(obj, "ltpi-ctrl",
&s->ltpi, TYPE_ASPEED_LTPI);
@@ -54,11 +75,16 @@ static void aspeed_ast1700_instance_init(Object *obj)
return;
}
+static const Property aspeed_ast1700_props[] = {
+ DEFINE_PROP_UINT64("mapped-base", AspeedAST1700SoCState, mapped_base, 0),
+};
+
static void aspeed_ast1700_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = aspeed_ast1700_realize;
+ device_class_set_props(dc, aspeed_ast1700_props);
}
static const TypeInfo aspeed_ast1700_info = {
--
2.43.0
^ permalink raw reply related [flat|nested] 46+ messages in thread* Re: [PATCH v2 07/17] hw/arm/aspeed: Attach UART device to AST1700 model
2025-11-05 3:58 ` [PATCH v2 07/17] hw/arm/aspeed: Attach UART device " Kane Chen via
@ 2025-11-10 16:04 ` Cédric Le Goater
2025-11-11 5:46 ` Jan Kiszka
0 siblings, 1 reply; 46+ messages in thread
From: Cédric Le Goater @ 2025-11-10 16:04 UTC (permalink / raw)
To: Kane Chen, Peter Maydell, Steven Lee, Troy Lee, Jamin Lin,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here, Jan Kiszka, 'Peter Xu',
Fabiano Rosas
Cc: troy_lee
Hi,
This change appears complex due to the use of routine
qdev_set_legacy_instance_id(). It was introduced 15 years ago
by commit 4d2ffa08b601 ("vmstate: Add support for alias ID"),
for the PC world AIUI.
Adding Jan, Peter, Fabiano for feedback on the current relevance
of qdev_set_legacy_instance_id(), particularly in the ARM/BMC world.
I feel we could get rid of it and simplify this patch.
Thanks,
C.
On 11/5/25 04:58, Kane Chen wrote:
> From: Kane-Chen-AS <kane_chen@aspeedtech.com>
>
> Connect the UART controller to the AST1700 model by mapping its MMIO
> region.
>
> Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
> ---
> include/hw/misc/aspeed_ast1700.h | 2 ++
> hw/arm/aspeed_ast27x0.c | 2 ++
> hw/misc/aspeed_ast1700.c | 26 ++++++++++++++++++++++++++
> 3 files changed, 30 insertions(+)
>
> diff --git a/include/hw/misc/aspeed_ast1700.h b/include/hw/misc/aspeed_ast1700.h
> index c2bea11346..e105ceb027 100644
> --- a/include/hw/misc/aspeed_ast1700.h
> +++ b/include/hw/misc/aspeed_ast1700.h
> @@ -28,8 +28,10 @@ struct AspeedAST1700SoCState {
> SysBusDevice parent_obj;
>
> MemoryRegion iomem;
> + hwaddr mapped_base;
>
> AspeedLTPIState ltpi;
> + SerialMM uart;
> };
>
> #endif /* ASPEED_AST1700_H */
> diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
> index 11625e165a..7151feb35d 100644
> --- a/hw/arm/aspeed_ast27x0.c
> +++ b/hw/arm/aspeed_ast27x0.c
> @@ -1070,6 +1070,8 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
>
> /* IO Expander */
> for (i = 0; i < sc->ioexp_num; i++) {
> + qdev_prop_set_uint64(DEVICE(&s->ioexp[i]), "mapped-base",
> + sc->memmap[ASPEED_DEV_LTPI_IO0 + i]);
> if (!sysbus_realize(SYS_BUS_DEVICE(&s->ioexp[i]), errp)) {
> return;
> }
> diff --git a/hw/misc/aspeed_ast1700.c b/hw/misc/aspeed_ast1700.c
> index 0ca2b90ff0..1c2d367cdb 100644
> --- a/hw/misc/aspeed_ast1700.c
> +++ b/hw/misc/aspeed_ast1700.c
> @@ -18,22 +18,39 @@
> #define AST2700_SOC_LTPI_SIZE 0x01000000
>
> enum {
> + ASPEED_AST1700_DEV_UART12,
> ASPEED_AST1700_DEV_LTPI_CTRL,
> };
>
> static const hwaddr aspeed_ast1700_io_memmap[] = {
> + [ASPEED_AST1700_DEV_UART12] = 0x00C33B00,
> [ASPEED_AST1700_DEV_LTPI_CTRL] = 0x00C34000,
> };
> static void aspeed_ast1700_realize(DeviceState *dev, Error **errp)
> {
> AspeedAST1700SoCState *s = ASPEED_AST1700(dev);
> SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
> + hwaddr uart_base;
>
> /* Occupy memory space for all controllers in AST1700 */
> memory_region_init(&s->iomem, OBJECT(s), TYPE_ASPEED_AST1700,
> AST2700_SOC_LTPI_SIZE);
> sysbus_init_mmio(sbd, &s->iomem);
>
> + /* UART */
> + uart_base = s->mapped_base +
> + aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_UART12];
> + qdev_prop_set_uint8(DEVICE(&s->uart), "regshift", 2);
> + qdev_prop_set_uint32(DEVICE(&s->uart), "baudbase", 38400);
> + qdev_set_legacy_instance_id(DEVICE(&s->uart), uart_base, 2);
> + qdev_prop_set_uint8(DEVICE(&s->uart), "endianness", DEVICE_LITTLE_ENDIAN);
> + if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart), errp)) {
> + return;
> + }
> + memory_region_add_subregion(&s->iomem,
> + aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_UART12],
> + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart), 0));
> +
> /* LTPI controller */
> if (!sysbus_realize(SYS_BUS_DEVICE(&s->ltpi), errp)) {
> return;
> @@ -47,6 +64,10 @@ static void aspeed_ast1700_instance_init(Object *obj)
> {
> AspeedAST1700SoCState *s = ASPEED_AST1700(obj);
>
> + /* UART */
> + object_initialize_child(obj, "uart[*]", &s->uart,
> + TYPE_SERIAL_MM);
> +
> /* LTPI controller */
> object_initialize_child(obj, "ltpi-ctrl",
> &s->ltpi, TYPE_ASPEED_LTPI);
> @@ -54,11 +75,16 @@ static void aspeed_ast1700_instance_init(Object *obj)
> return;
> }
>
> +static const Property aspeed_ast1700_props[] = {
> + DEFINE_PROP_UINT64("mapped-base", AspeedAST1700SoCState, mapped_base, 0),
> +};
> +
> static void aspeed_ast1700_class_init(ObjectClass *klass, const void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(klass);
>
> dc->realize = aspeed_ast1700_realize;
> + device_class_set_props(dc, aspeed_ast1700_props);
> }
>
> static const TypeInfo aspeed_ast1700_info = {
^ permalink raw reply [flat|nested] 46+ messages in thread* Re: [PATCH v2 07/17] hw/arm/aspeed: Attach UART device to AST1700 model
2025-11-10 16:04 ` Cédric Le Goater
@ 2025-11-11 5:46 ` Jan Kiszka
0 siblings, 0 replies; 46+ messages in thread
From: Jan Kiszka @ 2025-11-11 5:46 UTC (permalink / raw)
To: Cédric Le Goater, Kane Chen, Peter Maydell, Steven Lee,
Troy Lee, Jamin Lin, Andrew Jeffery, Joel Stanley,
open list:ASPEED BMCs, open list:All patches CC here,
'Peter Xu', Fabiano Rosas
Cc: troy_lee
On 10.11.25 17:04, Cédric Le Goater wrote:
> Hi,
>
> This change appears complex due to the use of routine
> qdev_set_legacy_instance_id(). It was introduced 15 years ago
> by commit 4d2ffa08b601 ("vmstate: Add support for alias ID"),
> for the PC world AIUI.
>
> Adding Jan, Peter, Fabiano for feedback on the current relevance
> of qdev_set_legacy_instance_id(), particularly in the ARM/BMC world.
> I feel we could get rid of it and simplify this patch.
>
I have to dig deep in my memories but if I got it correctly again,
qdev_set_legacy_instance_id is (was) only there to transition an
existing but self-registered vmstate for an existing device model to
qdev-registered vmstate. We neither have a pre-existing device here, nor
do the aspeed machines or devices open-code their vmstate registrations.
Jan
> Thanks,
>
> C.
>
>
>
>
>
> On 11/5/25 04:58, Kane Chen wrote:
>> From: Kane-Chen-AS <kane_chen@aspeedtech.com>
>>
>> Connect the UART controller to the AST1700 model by mapping its MMIO
>> region.
>>
>> Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
>> ---
>> include/hw/misc/aspeed_ast1700.h | 2 ++
>> hw/arm/aspeed_ast27x0.c | 2 ++
>> hw/misc/aspeed_ast1700.c | 26 ++++++++++++++++++++++++++
>> 3 files changed, 30 insertions(+)
>>
>> diff --git a/include/hw/misc/aspeed_ast1700.h b/include/hw/misc/
>> aspeed_ast1700.h
>> index c2bea11346..e105ceb027 100644
>> --- a/include/hw/misc/aspeed_ast1700.h
>> +++ b/include/hw/misc/aspeed_ast1700.h
>> @@ -28,8 +28,10 @@ struct AspeedAST1700SoCState {
>> SysBusDevice parent_obj;
>> MemoryRegion iomem;
>> + hwaddr mapped_base;
>> AspeedLTPIState ltpi;
>> + SerialMM uart;
>> };
>> #endif /* ASPEED_AST1700_H */
>> diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
>> index 11625e165a..7151feb35d 100644
>> --- a/hw/arm/aspeed_ast27x0.c
>> +++ b/hw/arm/aspeed_ast27x0.c
>> @@ -1070,6 +1070,8 @@ static void
>> aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
>> /* IO Expander */
>> for (i = 0; i < sc->ioexp_num; i++) {
>> + qdev_prop_set_uint64(DEVICE(&s->ioexp[i]), "mapped-base",
>> + sc->memmap[ASPEED_DEV_LTPI_IO0 + i]);
>> if (!sysbus_realize(SYS_BUS_DEVICE(&s->ioexp[i]), errp)) {
>> return;
>> }
>> diff --git a/hw/misc/aspeed_ast1700.c b/hw/misc/aspeed_ast1700.c
>> index 0ca2b90ff0..1c2d367cdb 100644
>> --- a/hw/misc/aspeed_ast1700.c
>> +++ b/hw/misc/aspeed_ast1700.c
>> @@ -18,22 +18,39 @@
>> #define AST2700_SOC_LTPI_SIZE 0x01000000
>> enum {
>> + ASPEED_AST1700_DEV_UART12,
>> ASPEED_AST1700_DEV_LTPI_CTRL,
>> };
>> static const hwaddr aspeed_ast1700_io_memmap[] = {
>> + [ASPEED_AST1700_DEV_UART12] = 0x00C33B00,
>> [ASPEED_AST1700_DEV_LTPI_CTRL] = 0x00C34000,
>> };
>> static void aspeed_ast1700_realize(DeviceState *dev, Error **errp)
>> {
>> AspeedAST1700SoCState *s = ASPEED_AST1700(dev);
>> SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
>> + hwaddr uart_base;
>> /* Occupy memory space for all controllers in AST1700 */
>> memory_region_init(&s->iomem, OBJECT(s), TYPE_ASPEED_AST1700,
>> AST2700_SOC_LTPI_SIZE);
>> sysbus_init_mmio(sbd, &s->iomem);
>> + /* UART */
>> + uart_base = s->mapped_base +
>> + aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_UART12];
>> + qdev_prop_set_uint8(DEVICE(&s->uart), "regshift", 2);
>> + qdev_prop_set_uint32(DEVICE(&s->uart), "baudbase", 38400);
>> + qdev_set_legacy_instance_id(DEVICE(&s->uart), uart_base, 2);
>> + qdev_prop_set_uint8(DEVICE(&s->uart), "endianness",
>> DEVICE_LITTLE_ENDIAN);
>> + if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart), errp)) {
>> + return;
>> + }
>> + memory_region_add_subregion(&s->iomem,
>> +
>> aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_UART12],
>> + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s-
>> >uart), 0));
>> +
>> /* LTPI controller */
>> if (!sysbus_realize(SYS_BUS_DEVICE(&s->ltpi), errp)) {
>> return;
>> @@ -47,6 +64,10 @@ static void aspeed_ast1700_instance_init(Object *obj)
>> {
>> AspeedAST1700SoCState *s = ASPEED_AST1700(obj);
>> + /* UART */
>> + object_initialize_child(obj, "uart[*]", &s->uart,
>> + TYPE_SERIAL_MM);
>> +
>> /* LTPI controller */
>> object_initialize_child(obj, "ltpi-ctrl",
>> &s->ltpi, TYPE_ASPEED_LTPI);
>> @@ -54,11 +75,16 @@ static void aspeed_ast1700_instance_init(Object *obj)
>> return;
>> }
>> +static const Property aspeed_ast1700_props[] = {
>> + DEFINE_PROP_UINT64("mapped-base", AspeedAST1700SoCState,
>> mapped_base, 0),
>> +};
>> +
>> static void aspeed_ast1700_class_init(ObjectClass *klass, const void
>> *data)
>> {
>> DeviceClass *dc = DEVICE_CLASS(klass);
>> dc->realize = aspeed_ast1700_realize;
>> + device_class_set_props(dc, aspeed_ast1700_props);
>> }
>> static const TypeInfo aspeed_ast1700_info = {
>
--
Siemens AG, Foundational Technologies
Linux Expert Center
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH v2 08/17] hw/arm/aspeed: Attach SRAM device to AST1700 model
2025-11-05 3:58 [PATCH v2 00/17] hw/arm/aspeed: AST1700 LTPI support and device hookups Kane Chen via
` (6 preceding siblings ...)
2025-11-05 3:58 ` [PATCH v2 07/17] hw/arm/aspeed: Attach UART device " Kane Chen via
@ 2025-11-05 3:58 ` Kane Chen via
2025-11-10 16:08 ` Cédric Le Goater
2025-11-05 3:58 ` [PATCH v2 09/17] hw/arm/aspeed: Attach SPI " Kane Chen via
` (10 subsequent siblings)
18 siblings, 1 reply; 46+ messages in thread
From: Kane Chen via @ 2025-11-05 3:58 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, Kane-Chen-AS
From: Kane-Chen-AS <kane_chen@aspeedtech.com>
Map the SRAM device to AST1700 model
Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
---
include/hw/misc/aspeed_ast1700.h | 1 +
hw/misc/aspeed_ast1700.c | 25 +++++++++++++++++++++++++
2 files changed, 26 insertions(+)
diff --git a/include/hw/misc/aspeed_ast1700.h b/include/hw/misc/aspeed_ast1700.h
index e105ceb027..391c8687f5 100644
--- a/include/hw/misc/aspeed_ast1700.h
+++ b/include/hw/misc/aspeed_ast1700.h
@@ -32,6 +32,7 @@ struct AspeedAST1700SoCState {
AspeedLTPIState ltpi;
SerialMM uart;
+ MemoryRegion sram;
};
#endif /* ASPEED_AST1700_H */
diff --git a/hw/misc/aspeed_ast1700.c b/hw/misc/aspeed_ast1700.c
index 1c2d367cdb..6f7ff625b5 100644
--- a/hw/misc/aspeed_ast1700.c
+++ b/hw/misc/aspeed_ast1700.c
@@ -15,14 +15,18 @@
#include "migration/vmstate.h"
#include "hw/misc/aspeed_ast1700.h"
+#define AST1700_BOARD1_MEM_ADDR 0x30000000
#define AST2700_SOC_LTPI_SIZE 0x01000000
+#define AST1700_SOC_SRAM_SIZE 0x00040000
enum {
+ ASPEED_AST1700_DEV_SRAM,
ASPEED_AST1700_DEV_UART12,
ASPEED_AST1700_DEV_LTPI_CTRL,
};
static const hwaddr aspeed_ast1700_io_memmap[] = {
+ [ASPEED_AST1700_DEV_SRAM] = 0x00BC0000,
[ASPEED_AST1700_DEV_UART12] = 0x00C33B00,
[ASPEED_AST1700_DEV_LTPI_CTRL] = 0x00C34000,
};
@@ -31,12 +35,33 @@ static void aspeed_ast1700_realize(DeviceState *dev, Error **errp)
AspeedAST1700SoCState *s = ASPEED_AST1700(dev);
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
hwaddr uart_base;
+ Error *err = NULL;
+ int board_idx;
+ char sram_name[32];
+
+ if (s->mapped_base == AST1700_BOARD1_MEM_ADDR) {
+ board_idx = 0;
+ } else {
+ board_idx = 1;
+ }
/* Occupy memory space for all controllers in AST1700 */
memory_region_init(&s->iomem, OBJECT(s), TYPE_ASPEED_AST1700,
AST2700_SOC_LTPI_SIZE);
sysbus_init_mmio(sbd, &s->iomem);
+ /* SRAM */
+ snprintf(sram_name, sizeof(sram_name), "aspeed.ioexp-sram.%d", board_idx);
+ memory_region_init_ram(&s->sram, OBJECT(s), sram_name,
+ AST1700_SOC_SRAM_SIZE, &err);
+ if (err != NULL) {
+ error_propagate(errp, err);
+ return;
+ }
+ memory_region_add_subregion(&s->iomem,
+ aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_SRAM],
+ &s->sram);
+
/* UART */
uart_base = s->mapped_base +
aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_UART12];
--
2.43.0
^ permalink raw reply related [flat|nested] 46+ messages in thread* Re: [PATCH v2 08/17] hw/arm/aspeed: Attach SRAM device to AST1700 model
2025-11-05 3:58 ` [PATCH v2 08/17] hw/arm/aspeed: Attach SRAM " Kane Chen via
@ 2025-11-10 16:08 ` Cédric Le Goater
2025-11-11 1:42 ` Kane Chen
0 siblings, 1 reply; 46+ messages in thread
From: Cédric Le Goater @ 2025-11-10 16:08 UTC (permalink / raw)
To: Kane Chen, Peter Maydell, Steven Lee, Troy Lee, Jamin Lin,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee
On 11/5/25 04:58, Kane Chen wrote:
> From: Kane-Chen-AS <kane_chen@aspeedtech.com>
>
> Map the SRAM device to AST1700 model
>
> Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
> ---
> include/hw/misc/aspeed_ast1700.h | 1 +
> hw/misc/aspeed_ast1700.c | 25 +++++++++++++++++++++++++
> 2 files changed, 26 insertions(+)
>
> diff --git a/include/hw/misc/aspeed_ast1700.h b/include/hw/misc/aspeed_ast1700.h
> index e105ceb027..391c8687f5 100644
> --- a/include/hw/misc/aspeed_ast1700.h
> +++ b/include/hw/misc/aspeed_ast1700.h
> @@ -32,6 +32,7 @@ struct AspeedAST1700SoCState {
>
> AspeedLTPIState ltpi;
> SerialMM uart;
> + MemoryRegion sram;
> };
>
> #endif /* ASPEED_AST1700_H */
> diff --git a/hw/misc/aspeed_ast1700.c b/hw/misc/aspeed_ast1700.c
> index 1c2d367cdb..6f7ff625b5 100644
> --- a/hw/misc/aspeed_ast1700.c
> +++ b/hw/misc/aspeed_ast1700.c
> @@ -15,14 +15,18 @@
> #include "migration/vmstate.h"
> #include "hw/misc/aspeed_ast1700.h"
>
> +#define AST1700_BOARD1_MEM_ADDR 0x30000000
> #define AST2700_SOC_LTPI_SIZE 0x01000000
> +#define AST1700_SOC_SRAM_SIZE 0x00040000
>
> enum {
> + ASPEED_AST1700_DEV_SRAM,
> ASPEED_AST1700_DEV_UART12,
> ASPEED_AST1700_DEV_LTPI_CTRL,
> };
>
> static const hwaddr aspeed_ast1700_io_memmap[] = {
> + [ASPEED_AST1700_DEV_SRAM] = 0x00BC0000,
> [ASPEED_AST1700_DEV_UART12] = 0x00C33B00,
> [ASPEED_AST1700_DEV_LTPI_CTRL] = 0x00C34000,
> };
> @@ -31,12 +35,33 @@ static void aspeed_ast1700_realize(DeviceState *dev, Error **errp)
> AspeedAST1700SoCState *s = ASPEED_AST1700(dev);
> SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
> hwaddr uart_base;
> + Error *err = NULL;
This variable could be avoided.
> + int board_idx;
> + char sram_name[32];
> +
> + if (s->mapped_base == AST1700_BOARD1_MEM_ADDR) {
> + board_idx = 0;
> + } else {
> + board_idx = 1;
> + }
That's a bit hacky.
An "index" property set at the SoC level would avoid this weak heuristic.
>
> /* Occupy memory space for all controllers in AST1700 */
> memory_region_init(&s->iomem, OBJECT(s), TYPE_ASPEED_AST1700,
> AST2700_SOC_LTPI_SIZE);
> sysbus_init_mmio(sbd, &s->iomem);
>
> + /* SRAM */
> + snprintf(sram_name, sizeof(sram_name), "aspeed.ioexp-sram.%d", board_idx);
> + memory_region_init_ram(&s->sram, OBJECT(s), sram_name,
> + AST1700_SOC_SRAM_SIZE, &err);
Just pass 'errp' and test the return value of memory_region_init_ram()
Thanks,
C.
> + if (err != NULL) {
> + error_propagate(errp, err);
> + return;
> + }
> + memory_region_add_subregion(&s->iomem,
> + aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_SRAM],
> + &s->sram);
> +
> /* UART */
> uart_base = s->mapped_base +
> aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_UART12];
^ permalink raw reply [flat|nested] 46+ messages in thread* RE: [PATCH v2 08/17] hw/arm/aspeed: Attach SRAM device to AST1700 model
2025-11-10 16:08 ` Cédric Le Goater
@ 2025-11-11 1:42 ` Kane Chen
0 siblings, 0 replies; 46+ messages in thread
From: Kane Chen @ 2025-11-11 1:42 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee
Hi Cédric,
Thanks for reviewing. I will adjust the code based the feedback.
Best Regards,
Kane
> -----Original Message-----
> From: Cédric Le Goater <clg@kaod.org>
> Sent: Tuesday, November 11, 2025 12:08 AM
> To: Kane Chen <kane_chen@aspeedtech.com>; Peter Maydell
> <peter.maydell@linaro.org>; Steven Lee <steven_lee@aspeedtech.com>; Troy
> Lee <leetroy@gmail.com>; Jamin Lin <jamin_lin@aspeedtech.com>; Andrew
> Jeffery <andrew@codeconstruct.com.au>; Joel Stanley <joel@jms.id.au>;
> open list:ASPEED BMCs <qemu-arm@nongnu.org>; open list:All patches CC
> here <qemu-devel@nongnu.org>
> Cc: Troy Lee <troy_lee@aspeedtech.com>
> Subject: Re: [PATCH v2 08/17] hw/arm/aspeed: Attach SRAM device to
> AST1700 model
>
> On 11/5/25 04:58, Kane Chen wrote:
> > From: Kane-Chen-AS <kane_chen@aspeedtech.com>
> >
> > Map the SRAM device to AST1700 model
> >
> > Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
> > ---
> > include/hw/misc/aspeed_ast1700.h | 1 +
> > hw/misc/aspeed_ast1700.c | 25
> +++++++++++++++++++++++++
> > 2 files changed, 26 insertions(+)
> >
> > diff --git a/include/hw/misc/aspeed_ast1700.h
> > b/include/hw/misc/aspeed_ast1700.h
> > index e105ceb027..391c8687f5 100644
> > --- a/include/hw/misc/aspeed_ast1700.h
> > +++ b/include/hw/misc/aspeed_ast1700.h
> > @@ -32,6 +32,7 @@ struct AspeedAST1700SoCState {
> >
> > AspeedLTPIState ltpi;
> > SerialMM uart;
> > + MemoryRegion sram;
> > };
> >
> > #endif /* ASPEED_AST1700_H */
> > diff --git a/hw/misc/aspeed_ast1700.c b/hw/misc/aspeed_ast1700.c index
> > 1c2d367cdb..6f7ff625b5 100644
> > --- a/hw/misc/aspeed_ast1700.c
> > +++ b/hw/misc/aspeed_ast1700.c
> > @@ -15,14 +15,18 @@
> > #include "migration/vmstate.h"
> > #include "hw/misc/aspeed_ast1700.h"
> >
> > +#define AST1700_BOARD1_MEM_ADDR 0x30000000
> > #define AST2700_SOC_LTPI_SIZE 0x01000000
> > +#define AST1700_SOC_SRAM_SIZE 0x00040000
> >
> > enum {
> > + ASPEED_AST1700_DEV_SRAM,
> > ASPEED_AST1700_DEV_UART12,
> > ASPEED_AST1700_DEV_LTPI_CTRL,
> > };
> >
> > static const hwaddr aspeed_ast1700_io_memmap[] = {
> > + [ASPEED_AST1700_DEV_SRAM] = 0x00BC0000,
> > [ASPEED_AST1700_DEV_UART12] = 0x00C33B00,
> > [ASPEED_AST1700_DEV_LTPI_CTRL] = 0x00C34000,
> > };
> > @@ -31,12 +35,33 @@ static void aspeed_ast1700_realize(DeviceState
> *dev, Error **errp)
> > AspeedAST1700SoCState *s = ASPEED_AST1700(dev);
> > SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
> > hwaddr uart_base;
> > + Error *err = NULL;
>
> This variable could be avoided.
>
> > + int board_idx;
> > + char sram_name[32];
> > +
> > + if (s->mapped_base == AST1700_BOARD1_MEM_ADDR) {
> > + board_idx = 0;
> > + } else {
> > + board_idx = 1;
> > + }
>
> That's a bit hacky.
>
> An "index" property set at the SoC level would avoid this weak heuristic.
>
>
> >
> > /* Occupy memory space for all controllers in AST1700 */
> > memory_region_init(&s->iomem, OBJECT(s),
> TYPE_ASPEED_AST1700,
> > AST2700_SOC_LTPI_SIZE);
> > sysbus_init_mmio(sbd, &s->iomem);
> >
> > + /* SRAM */
> > + snprintf(sram_name, sizeof(sram_name), "aspeed.ioexp-sram.%d",
> board_idx);
> > + memory_region_init_ram(&s->sram, OBJECT(s), sram_name,
> > + AST1700_SOC_SRAM_SIZE, &err);
>
> Just pass 'errp' and test the return value of memory_region_init_ram()
>
>
> Thanks,
>
> C.
>
>
>
> > + if (err != NULL) {
> > + error_propagate(errp, err);
> > + return;
> > + }
> > + memory_region_add_subregion(&s->iomem,
> > +
> aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_SRAM],
> > + &s->sram);
> > +
> > /* UART */
> > uart_base = s->mapped_base +
> >
> aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_UART12];
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH v2 09/17] hw/arm/aspeed: Attach SPI device to AST1700 model
2025-11-05 3:58 [PATCH v2 00/17] hw/arm/aspeed: AST1700 LTPI support and device hookups Kane Chen via
` (7 preceding siblings ...)
2025-11-05 3:58 ` [PATCH v2 08/17] hw/arm/aspeed: Attach SRAM " Kane Chen via
@ 2025-11-05 3:58 ` Kane Chen via
2025-11-05 21:20 ` Nabih Estefan
2025-11-05 3:58 ` [PATCH v2 10/17] hw/arm/aspeed: Attach ADC " Kane Chen via
` (9 subsequent siblings)
18 siblings, 1 reply; 46+ messages in thread
From: Kane Chen via @ 2025-11-05 3:58 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, Kane-Chen-AS
From: Kane-Chen-AS <kane_chen@aspeedtech.com>
Connect the SPI device to AST1700 model.
Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
---
include/hw/misc/aspeed_ast1700.h | 1 +
hw/misc/aspeed_ast1700.c | 28 ++++++++++++++++++++++++++++
2 files changed, 29 insertions(+)
diff --git a/include/hw/misc/aspeed_ast1700.h b/include/hw/misc/aspeed_ast1700.h
index 391c8687f5..e55deea67a 100644
--- a/include/hw/misc/aspeed_ast1700.h
+++ b/include/hw/misc/aspeed_ast1700.h
@@ -33,6 +33,7 @@ struct AspeedAST1700SoCState {
AspeedLTPIState ltpi;
SerialMM uart;
MemoryRegion sram;
+ AspeedSMCState spi;
};
#endif /* ASPEED_AST1700_H */
diff --git a/hw/misc/aspeed_ast1700.c b/hw/misc/aspeed_ast1700.c
index 6f7ff625b5..ba44e484e8 100644
--- a/hw/misc/aspeed_ast1700.c
+++ b/hw/misc/aspeed_ast1700.c
@@ -20,15 +20,19 @@
#define AST1700_SOC_SRAM_SIZE 0x00040000
enum {
+ ASPEED_AST1700_DEV_SPI0,
ASPEED_AST1700_DEV_SRAM,
ASPEED_AST1700_DEV_UART12,
ASPEED_AST1700_DEV_LTPI_CTRL,
+ ASPEED_AST1700_DEV_SPI0_MEM,
};
static const hwaddr aspeed_ast1700_io_memmap[] = {
+ [ASPEED_AST1700_DEV_SPI0] = 0x00030000,
[ASPEED_AST1700_DEV_SRAM] = 0x00BC0000,
[ASPEED_AST1700_DEV_UART12] = 0x00C33B00,
[ASPEED_AST1700_DEV_LTPI_CTRL] = 0x00C34000,
+ [ASPEED_AST1700_DEV_SPI0_MEM] = 0x04000000,
};
static void aspeed_ast1700_realize(DeviceState *dev, Error **errp)
{
@@ -76,6 +80,20 @@ static void aspeed_ast1700_realize(DeviceState *dev, Error **errp)
aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_UART12],
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart), 0));
+ /* SPI */
+ object_property_set_link(OBJECT(&s->spi), "dram",
+ OBJECT(&s->iomem), &error_abort);
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi), errp)) {
+ return;
+ }
+ memory_region_add_subregion(&s->iomem,
+ aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_SPI0],
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->spi), 0));
+
+ memory_region_add_subregion(&s->iomem,
+ aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_SPI0_MEM],
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->spi), 1));
+
/* LTPI controller */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->ltpi), errp)) {
return;
@@ -88,11 +106,21 @@ static void aspeed_ast1700_realize(DeviceState *dev, Error **errp)
static void aspeed_ast1700_instance_init(Object *obj)
{
AspeedAST1700SoCState *s = ASPEED_AST1700(obj);
+ char socname[8];
+ char typename[64];
+
+ if (sscanf(object_get_typename(obj), "aspeed.ast1700-%7s", socname) != 1) {
+ g_assert_not_reached();
+ }
/* UART */
object_initialize_child(obj, "uart[*]", &s->uart,
TYPE_SERIAL_MM);
+ /* SPI */
+ snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", 0, socname);
+ object_initialize_child(obj, "ioexp-spi[*]", &s->spi,
+ typename);
/* LTPI controller */
object_initialize_child(obj, "ltpi-ctrl",
&s->ltpi, TYPE_ASPEED_LTPI);
--
2.43.0
^ permalink raw reply related [flat|nested] 46+ messages in thread* Re: [PATCH v2 09/17] hw/arm/aspeed: Attach SPI device to AST1700 model
2025-11-05 3:58 ` [PATCH v2 09/17] hw/arm/aspeed: Attach SPI " Kane Chen via
@ 2025-11-05 21:20 ` Nabih Estefan
2025-11-06 10:11 ` Kane Chen
0 siblings, 1 reply; 46+ messages in thread
From: Nabih Estefan @ 2025-11-05 21:20 UTC (permalink / raw)
To: Kane Chen
Cc: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here, troy_lee
This patch seems to break qtest-arm
```
37/56 qemu:qtest+qtest-arm / qtest-arm/device-introspect-test ERROR
5.18s killed by signal 6 SIGABRT
>>> QTEST_QEMU_IMG=./qemu-img G_TEST_DBUS_DAEMON=/b/f/w/src/git/qemu/tests/dbus-vmstate-daemon.sh QTEST_QEMU_BINARY=./qemu-system-arm PYTHON=/b/f/w/src/git/qemu/build/pyvenv/bin/python3 MSAN_OPTIONS=halt_on_error=1:abort_on_error=1:print_summary=1:print_stacktrace=1 MESON_TEST_ITERATION=1 UBSAN_OPTIONS=halt_on_error=1:abort_on_error=1:print_summary=1:print_stacktrace=1 QTEST_QEMU_STORAGE_DAEMON_BINARY=./storage-daemon/qemu-storage-daemon RUST_BACKTRACE=1 ASAN_OPTIONS=halt_on_error=1:abort_on_error=1:print_summary=1 MALLOC_PERTURB_=175 /b/f/w/src/git/qemu/build/tests/qtest/device-introspect-test --tap -k
――――――――――――――――――――――――――――――――――――― ✀ ―――――――――――――――――――――――――――――――――――――
stderr:
**
ERROR:../hw/misc/aspeed_ast1700.c:113:aspeed_ast1700_instance_init:
code should not be reached
Broken pipe
../tests/qtest/libqtest.c:208: kill_qemu() detected QEMU death from
signal 6 (Aborted) (core dumped)
(test program exited with status code -6)
```
Failed by running:
```
./configure \
--target-list=arm-softmmu,arm-linux-user,aarch64-softmmu,aarch64-linux-user,i386-softmmu
\
--cc=clang-18 --extra-cflags=-Wno-deprecated-declarations \
--cxx=clang++-18 --extra-cxxflags=-Wno-deprecated-declarations
make -j 32 all check-report-unit.junit.xml
check-report-qtest-arm.junit.xml check-report-qtest-aarch64.junit.xml
check-report-qtest-i386.junit.xml
Thanks,
Nabih
Nabih Estefan (he/him) | Software Engineer |
nabihestefan@google.com | 857-308-9574
On Tue, Nov 4, 2025 at 8:03 PM Kane Chen via <qemu-devel@nongnu.org> wrote:
>
> From: Kane-Chen-AS <kane_chen@aspeedtech.com>
>
> Connect the SPI device to AST1700 model.
>
> Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
> ---
> include/hw/misc/aspeed_ast1700.h | 1 +
> hw/misc/aspeed_ast1700.c | 28 ++++++++++++++++++++++++++++
> 2 files changed, 29 insertions(+)
>
> diff --git a/include/hw/misc/aspeed_ast1700.h b/include/hw/misc/aspeed_ast1700.h
> index 391c8687f5..e55deea67a 100644
> --- a/include/hw/misc/aspeed_ast1700.h
> +++ b/include/hw/misc/aspeed_ast1700.h
> @@ -33,6 +33,7 @@ struct AspeedAST1700SoCState {
> AspeedLTPIState ltpi;
> SerialMM uart;
> MemoryRegion sram;
> + AspeedSMCState spi;
> };
>
> #endif /* ASPEED_AST1700_H */
> diff --git a/hw/misc/aspeed_ast1700.c b/hw/misc/aspeed_ast1700.c
> index 6f7ff625b5..ba44e484e8 100644
> --- a/hw/misc/aspeed_ast1700.c
> +++ b/hw/misc/aspeed_ast1700.c
> @@ -20,15 +20,19 @@
> #define AST1700_SOC_SRAM_SIZE 0x00040000
>
> enum {
> + ASPEED_AST1700_DEV_SPI0,
> ASPEED_AST1700_DEV_SRAM,
> ASPEED_AST1700_DEV_UART12,
> ASPEED_AST1700_DEV_LTPI_CTRL,
> + ASPEED_AST1700_DEV_SPI0_MEM,
> };
>
> static const hwaddr aspeed_ast1700_io_memmap[] = {
> + [ASPEED_AST1700_DEV_SPI0] = 0x00030000,
> [ASPEED_AST1700_DEV_SRAM] = 0x00BC0000,
> [ASPEED_AST1700_DEV_UART12] = 0x00C33B00,
> [ASPEED_AST1700_DEV_LTPI_CTRL] = 0x00C34000,
> + [ASPEED_AST1700_DEV_SPI0_MEM] = 0x04000000,
> };
> static void aspeed_ast1700_realize(DeviceState *dev, Error **errp)
> {
> @@ -76,6 +80,20 @@ static void aspeed_ast1700_realize(DeviceState *dev, Error **errp)
> aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_UART12],
> sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart), 0));
>
> + /* SPI */
> + object_property_set_link(OBJECT(&s->spi), "dram",
> + OBJECT(&s->iomem), &error_abort);
> + if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi), errp)) {
> + return;
> + }
> + memory_region_add_subregion(&s->iomem,
> + aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_SPI0],
> + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->spi), 0));
> +
> + memory_region_add_subregion(&s->iomem,
> + aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_SPI0_MEM],
> + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->spi), 1));
> +
> /* LTPI controller */
> if (!sysbus_realize(SYS_BUS_DEVICE(&s->ltpi), errp)) {
> return;
> @@ -88,11 +106,21 @@ static void aspeed_ast1700_realize(DeviceState *dev, Error **errp)
> static void aspeed_ast1700_instance_init(Object *obj)
> {
> AspeedAST1700SoCState *s = ASPEED_AST1700(obj);
> + char socname[8];
> + char typename[64];
> +
> + if (sscanf(object_get_typename(obj), "aspeed.ast1700-%7s", socname) != 1) {
> + g_assert_not_reached();
> + }
>
> /* UART */
> object_initialize_child(obj, "uart[*]", &s->uart,
> TYPE_SERIAL_MM);
>
> + /* SPI */
> + snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", 0, socname);
> + object_initialize_child(obj, "ioexp-spi[*]", &s->spi,
> + typename);
> /* LTPI controller */
> object_initialize_child(obj, "ltpi-ctrl",
> &s->ltpi, TYPE_ASPEED_LTPI);
> --
> 2.43.0
>
>
^ permalink raw reply [flat|nested] 46+ messages in thread* RE: [PATCH v2 09/17] hw/arm/aspeed: Attach SPI device to AST1700 model
2025-11-05 21:20 ` Nabih Estefan
@ 2025-11-06 10:11 ` Kane Chen
2025-11-06 10:21 ` Cédric Le Goater
0 siblings, 1 reply; 46+ messages in thread
From: Kane Chen @ 2025-11-06 10:11 UTC (permalink / raw)
To: Nabih Estefan
Cc: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here, Troy Lee
Hi Nabih,
Thanks for pointing this out. It seems I need to add the abstract attribute to the aspeed_ast1700_info
structure, as shown below:
diff --git a/hw/misc/aspeed_ast1700.c b/hw/misc/aspeed_ast1700.c
index 3d9a920a7a..ec95217f16 100644
--- a/hw/misc/aspeed_ast1700.c
+++ b/hw/misc/aspeed_ast1700.c
@@ -286,6 +286,7 @@ static const TypeInfo aspeed_ast1700_info = {
.instance_size = sizeof(AspeedAST1700SoCState),
.class_init = aspeed_ast1700_class_init,
.instance_init = aspeed_ast1700_instance_init,
+ .abstract = true,
};
On the other hand, I encountered a timeout error while running the make check-functional test.
I need to investigate why the test case failed.
Once this issue is clarified, I’ll submit another patch for further review.
Best Regards,
Kane
> -----Original Message-----
> From: Nabih Estefan <nabihestefan@google.com>
> Sent: Thursday, November 6, 2025 5:20 AM
> To: Kane Chen <kane_chen@aspeedtech.com>
> Cc: Cédric Le Goater <clg@kaod.org>; Peter Maydell
> <peter.maydell@linaro.org>; Steven Lee <steven_lee@aspeedtech.com>; Troy
> Lee <leetroy@gmail.com>; Jamin Lin <jamin_lin@aspeedtech.com>; Andrew
> Jeffery <andrew@codeconstruct.com.au>; Joel Stanley <joel@jms.id.au>;
> open list:ASPEED BMCs <qemu-arm@nongnu.org>; open list:All patches CC
> here <qemu-devel@nongnu.org>; Troy Lee <troy_lee@aspeedtech.com>
> Subject: Re: [PATCH v2 09/17] hw/arm/aspeed: Attach SPI device to AST1700
> model
>
> This patch seems to break qtest-arm
> ```
> 37/56 qemu:qtest+qtest-arm / qtest-arm/device-introspect-test ERROR 5.18s
> killed by signal 6 SIGABRT
> >>> QTEST_QEMU_IMG=./qemu-img
> >>>
> G_TEST_DBUS_DAEMON=/b/f/w/src/git/qemu/tests/dbus-vmstate-daemon.s
> h
> >>> QTEST_QEMU_BINARY=./qemu-system-arm
> >>> PYTHON=/b/f/w/src/git/qemu/build/pyvenv/bin/python3
> >>>
> MSAN_OPTIONS=halt_on_error=1:abort_on_error=1:print_summary=1:print_
> >>> stacktrace=1 MESON_TEST_ITERATION=1
> >>>
> UBSAN_OPTIONS=halt_on_error=1:abort_on_error=1:print_summary=1:print
> >>> _stacktrace=1
> >>>
> QTEST_QEMU_STORAGE_DAEMON_BINARY=./storage-daemon/qemu-storag
> e-daemo
> >>> n RUST_BACKTRACE=1
> >>> ASAN_OPTIONS=halt_on_error=1:abort_on_error=1:print_summary=1
> >>> MALLOC_PERTURB_=175
> >>> /b/f/w/src/git/qemu/build/tests/qtest/device-introspect-test --tap
> >>> -k
> ――――――――――――――――――――――――――――――――――――― ✀
> ―――――――――――――――――――――――――――――――――――――
> stderr:
> **
> ERROR:../hw/misc/aspeed_ast1700.c:113:aspeed_ast1700_instance_init:
> code should not be reached
> Broken pipe
> ../tests/qtest/libqtest.c:208: kill_qemu() detected QEMU death from signal 6
> (Aborted) (core dumped)
>
> (test program exited with status code -6) ```
>
> Failed by running:
> ```
> ./configure \
>
> --target-list=arm-softmmu,arm-linux-user,aarch64-softmmu,aarch64-linux-us
> er,i386-softmmu
> \
> --cc=clang-18 --extra-cflags=-Wno-deprecated-declarations \
> --cxx=clang++-18 --extra-cxxflags=-Wno-deprecated-declarations
> make -j 32 all check-report-unit.junit.xml check-report-qtest-arm.junit.xml
> check-report-qtest-aarch64.junit.xml
> check-report-qtest-i386.junit.xml
>
> Thanks,
> Nabih
>
> Nabih Estefan (he/him) | Software Engineer | nabihestefan@google.com |
> 857-308-9574
>
>
>
> On Tue, Nov 4, 2025 at 8:03 PM Kane Chen via <qemu-devel@nongnu.org>
> wrote:
> >
> > From: Kane-Chen-AS <kane_chen@aspeedtech.com>
> >
> > Connect the SPI device to AST1700 model.
> >
> > Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
> > ---
> > include/hw/misc/aspeed_ast1700.h | 1 +
> > hw/misc/aspeed_ast1700.c | 28
> ++++++++++++++++++++++++++++
> > 2 files changed, 29 insertions(+)
> >
> > diff --git a/include/hw/misc/aspeed_ast1700.h
> > b/include/hw/misc/aspeed_ast1700.h
> > index 391c8687f5..e55deea67a 100644
> > --- a/include/hw/misc/aspeed_ast1700.h
> > +++ b/include/hw/misc/aspeed_ast1700.h
> > @@ -33,6 +33,7 @@ struct AspeedAST1700SoCState {
> > AspeedLTPIState ltpi;
> > SerialMM uart;
> > MemoryRegion sram;
> > + AspeedSMCState spi;
> > };
> >
> > #endif /* ASPEED_AST1700_H */
> > diff --git a/hw/misc/aspeed_ast1700.c b/hw/misc/aspeed_ast1700.c index
> > 6f7ff625b5..ba44e484e8 100644
> > --- a/hw/misc/aspeed_ast1700.c
> > +++ b/hw/misc/aspeed_ast1700.c
> > @@ -20,15 +20,19 @@
> > #define AST1700_SOC_SRAM_SIZE 0x00040000
> >
> > enum {
> > + ASPEED_AST1700_DEV_SPI0,
> > ASPEED_AST1700_DEV_SRAM,
> > ASPEED_AST1700_DEV_UART12,
> > ASPEED_AST1700_DEV_LTPI_CTRL,
> > + ASPEED_AST1700_DEV_SPI0_MEM,
> > };
> >
> > static const hwaddr aspeed_ast1700_io_memmap[] = {
> > + [ASPEED_AST1700_DEV_SPI0] = 0x00030000,
> > [ASPEED_AST1700_DEV_SRAM] = 0x00BC0000,
> > [ASPEED_AST1700_DEV_UART12] = 0x00C33B00,
> > [ASPEED_AST1700_DEV_LTPI_CTRL] = 0x00C34000,
> > + [ASPEED_AST1700_DEV_SPI0_MEM] = 0x04000000,
> > };
> > static void aspeed_ast1700_realize(DeviceState *dev, Error **errp) {
> > @@ -76,6 +80,20 @@ static void aspeed_ast1700_realize(DeviceState *dev,
> Error **errp)
> >
> aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_UART12],
> >
> > sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart), 0));
> >
> > + /* SPI */
> > + object_property_set_link(OBJECT(&s->spi), "dram",
> > + OBJECT(&s->iomem), &error_abort);
> > + if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi), errp)) {
> > + return;
> > + }
> > + memory_region_add_subregion(&s->iomem,
> > +
> aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_SPI0],
> > +
> > + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->spi), 0));
> > +
> > + memory_region_add_subregion(&s->iomem,
> > +
> aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_SPI0_MEM],
> > +
> > + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->spi), 1));
> > +
> > /* LTPI controller */
> > if (!sysbus_realize(SYS_BUS_DEVICE(&s->ltpi), errp)) {
> > return;
> > @@ -88,11 +106,21 @@ static void aspeed_ast1700_realize(DeviceState
> > *dev, Error **errp) static void aspeed_ast1700_instance_init(Object
> > *obj) {
> > AspeedAST1700SoCState *s = ASPEED_AST1700(obj);
> > + char socname[8];
> > + char typename[64];
> > +
> > + if (sscanf(object_get_typename(obj), "aspeed.ast1700-%7s",
> socname) != 1) {
> > + g_assert_not_reached();
> > + }
> >
> > /* UART */
> > object_initialize_child(obj, "uart[*]", &s->uart,
> > TYPE_SERIAL_MM);
> >
> > + /* SPI */
> > + snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", 0,
> socname);
> > + object_initialize_child(obj, "ioexp-spi[*]", &s->spi,
> > + typename);
> > /* LTPI controller */
> > object_initialize_child(obj, "ltpi-ctrl",
> > &s->ltpi, TYPE_ASPEED_LTPI);
> > --
> > 2.43.0
> >
> >
^ permalink raw reply related [flat|nested] 46+ messages in thread* Re: [PATCH v2 09/17] hw/arm/aspeed: Attach SPI device to AST1700 model
2025-11-06 10:11 ` Kane Chen
@ 2025-11-06 10:21 ` Cédric Le Goater
2025-11-07 5:39 ` Kane Chen
0 siblings, 1 reply; 46+ messages in thread
From: Cédric Le Goater @ 2025-11-06 10:21 UTC (permalink / raw)
To: Kane Chen, Nabih Estefan
Cc: Peter Maydell, Steven Lee, Troy Lee, Jamin Lin, Andrew Jeffery,
Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here, Troy Lee
On 11/6/25 11:11, Kane Chen wrote:
> Hi Nabih,
>
> Thanks for pointing this out. It seems I need to add the abstract attribute to the aspeed_ast1700_info
> structure, as shown below:
>
> diff --git a/hw/misc/aspeed_ast1700.c b/hw/misc/aspeed_ast1700.c
> index 3d9a920a7a..ec95217f16 100644
> --- a/hw/misc/aspeed_ast1700.c
> +++ b/hw/misc/aspeed_ast1700.c
> @@ -286,6 +286,7 @@ static const TypeInfo aspeed_ast1700_info = {
> .instance_size = sizeof(AspeedAST1700SoCState),
> .class_init = aspeed_ast1700_class_init,
> .instance_init = aspeed_ast1700_instance_init,
> + .abstract = true,
> };
Hmm,
Please rework all typenames in aspeed_ast1700_instance_init(): remove
all snprintf() and use directly strings like "aspeed.gpio-ast2700".
For now, It should be fine. We will see if extensions are needed
in the future.
Also, I don't see why you need :
static const TypeInfo aspeed_ast1700_ast2700_info = {
.name = TYPE_ASPEED_AST1700_AST2700,
.parent = TYPE_ASPEED_AST1700,
};
Can't you use directly TYPE_ASPEED_AST1700 instead ?
> On the other hand, I encountered a timeout error while running the make check-functional test.
> I need to investigate why the test case failed.
> Once this issue is clarified, I’ll submit another patch for further review.
Wait for some feedback from me before resending.
Thanks,
C.
^ permalink raw reply [flat|nested] 46+ messages in thread* RE: [PATCH v2 09/17] hw/arm/aspeed: Attach SPI device to AST1700 model
2025-11-06 10:21 ` Cédric Le Goater
@ 2025-11-07 5:39 ` Kane Chen
2025-11-07 7:54 ` Cédric Le Goater
0 siblings, 1 reply; 46+ messages in thread
From: Kane Chen @ 2025-11-07 5:39 UTC (permalink / raw)
To: Cédric Le Goater, Nabih Estefan
Cc: Peter Maydell, Steven Lee, Troy Lee, Jamin Lin, Andrew Jeffery,
Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here, Troy Lee
Hi Cédric,
The reason I registered TypeInfo aspeed_ast1700_ast2700_info is that AST1700
may be connected to another SoC in the future. As you mentioned, at the current
stage it should be fine to use a fixed type name, since we only have AST2700
supporting AST1700. I'll update the related code and remove aspeed_ast1700_ast2700_info
accordingly.
If you have any other comments on the remaining patches, please let me know.
I'll wait for feedback from you or others before proceeding further.
Best Regards,
Kane
> -----Original Message-----
> From: Cédric Le Goater <clg@kaod.org>
> Sent: Thursday, November 6, 2025 6:22 PM
> To: Kane Chen <kane_chen@aspeedtech.com>; Nabih Estefan
> <nabihestefan@google.com>
> Cc: Peter Maydell <peter.maydell@linaro.org>; Steven Lee
> <steven_lee@aspeedtech.com>; Troy Lee <leetroy@gmail.com>; Jamin Lin
> <jamin_lin@aspeedtech.com>; Andrew Jeffery
> <andrew@codeconstruct.com.au>; Joel Stanley <joel@jms.id.au>; open
> list:ASPEED BMCs <qemu-arm@nongnu.org>; open list:All patches CC here
> <qemu-devel@nongnu.org>; Troy Lee <troy_lee@aspeedtech.com>
> Subject: Re: [PATCH v2 09/17] hw/arm/aspeed: Attach SPI device to AST1700
> model
>
> On 11/6/25 11:11, Kane Chen wrote:
> > Hi Nabih,
> >
> > Thanks for pointing this out. It seems I need to add the abstract
> > attribute to the aspeed_ast1700_info structure, as shown below:
> >
> > diff --git a/hw/misc/aspeed_ast1700.c b/hw/misc/aspeed_ast1700.c index
> > 3d9a920a7a..ec95217f16 100644
> > --- a/hw/misc/aspeed_ast1700.c
> > +++ b/hw/misc/aspeed_ast1700.c
> > @@ -286,6 +286,7 @@ static const TypeInfo aspeed_ast1700_info = {
> > .instance_size = sizeof(AspeedAST1700SoCState),
> > .class_init = aspeed_ast1700_class_init,
> > .instance_init = aspeed_ast1700_instance_init,
> > + .abstract = true,
> > };
>
> Hmm,
>
> Please rework all typenames in aspeed_ast1700_instance_init(): remove all
> snprintf() and use directly strings like "aspeed.gpio-ast2700".
> For now, It should be fine. We will see if extensions are needed in the future.
>
> Also, I don't see why you need :
>
> static const TypeInfo aspeed_ast1700_ast2700_info = {
> .name = TYPE_ASPEED_AST1700_AST2700,
> .parent = TYPE_ASPEED_AST1700,
> };
>
> Can't you use directly TYPE_ASPEED_AST1700 instead ?
>
> > On the other hand, I encountered a timeout error while running the make
> check-functional test.
> > I need to investigate why the test case failed.
> > Once this issue is clarified, I’ll submit another patch for further review.
>
> Wait for some feedback from me before resending.
>
> Thanks,
>
> C.
^ permalink raw reply [flat|nested] 46+ messages in thread* Re: [PATCH v2 09/17] hw/arm/aspeed: Attach SPI device to AST1700 model
2025-11-07 5:39 ` Kane Chen
@ 2025-11-07 7:54 ` Cédric Le Goater
0 siblings, 0 replies; 46+ messages in thread
From: Cédric Le Goater @ 2025-11-07 7:54 UTC (permalink / raw)
To: Kane Chen, Nabih Estefan
Cc: Peter Maydell, Steven Lee, Troy Lee, Jamin Lin, Andrew Jeffery,
Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here, Troy Lee
Hello Kane,
On 11/7/25 06:39, Kane Chen wrote:
> Hi Cédric,
>
> The reason I registered TypeInfo aspeed_ast1700_ast2700_info is that AST1700
> may be connected to another SoC in the future. As you mentioned, at the current
> stage it should be fine to use a fixed type name, since we only have AST2700
> supporting AST1700.
It is good to prepare ground but it's a bit early. Let's keep it simple for
now.
> I'll update the related code and remove aspeed_ast1700_ast2700_info
> accordingly.
>
> If you have any other comments on the remaining patches, please let me know.
> I'll wait for feedback from you or others before proceeding further.
I will review in the following weeks.
Current focus is on QEMU 10.2 fixes. Please test !
Thanks,
C.
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH v2 10/17] hw/arm/aspeed: Attach ADC device to AST1700 model
2025-11-05 3:58 [PATCH v2 00/17] hw/arm/aspeed: AST1700 LTPI support and device hookups Kane Chen via
` (8 preceding siblings ...)
2025-11-05 3:58 ` [PATCH v2 09/17] hw/arm/aspeed: Attach SPI " Kane Chen via
@ 2025-11-05 3:58 ` Kane Chen via
2025-11-05 3:58 ` [PATCH v2 11/17] hw/arm/aspeed: Attach SCU " Kane Chen via
` (8 subsequent siblings)
18 siblings, 0 replies; 46+ messages in thread
From: Kane Chen via @ 2025-11-05 3:58 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, Kane-Chen-AS
From: Kane-Chen-AS <kane_chen@aspeedtech.com>
Connect the ADC device to AST1700 model.
Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
---
include/hw/misc/aspeed_ast1700.h | 1 +
hw/arm/aspeed_ast27x0.c | 4 ++++
hw/misc/aspeed_ast1700.c | 15 +++++++++++++++
3 files changed, 20 insertions(+)
diff --git a/include/hw/misc/aspeed_ast1700.h b/include/hw/misc/aspeed_ast1700.h
index e55deea67a..dc9aa08c24 100644
--- a/include/hw/misc/aspeed_ast1700.h
+++ b/include/hw/misc/aspeed_ast1700.h
@@ -34,6 +34,7 @@ struct AspeedAST1700SoCState {
SerialMM uart;
MemoryRegion sram;
AspeedSMCState spi;
+ AspeedADCState adc;
};
#endif /* ASPEED_AST1700_H */
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 7151feb35d..75bb18b9c1 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -1092,6 +1092,10 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc[2 + i]), j,
irq);
}
+
+ /* ADC */
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->ioexp[i].adc), 0,
+ aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_ADC));
}
aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->dpmcu),
diff --git a/hw/misc/aspeed_ast1700.c b/hw/misc/aspeed_ast1700.c
index ba44e484e8..d06603a048 100644
--- a/hw/misc/aspeed_ast1700.c
+++ b/hw/misc/aspeed_ast1700.c
@@ -22,6 +22,7 @@
enum {
ASPEED_AST1700_DEV_SPI0,
ASPEED_AST1700_DEV_SRAM,
+ ASPEED_AST1700_DEV_ADC,
ASPEED_AST1700_DEV_UART12,
ASPEED_AST1700_DEV_LTPI_CTRL,
ASPEED_AST1700_DEV_SPI0_MEM,
@@ -30,6 +31,7 @@ enum {
static const hwaddr aspeed_ast1700_io_memmap[] = {
[ASPEED_AST1700_DEV_SPI0] = 0x00030000,
[ASPEED_AST1700_DEV_SRAM] = 0x00BC0000,
+ [ASPEED_AST1700_DEV_ADC] = 0x00C00000,
[ASPEED_AST1700_DEV_UART12] = 0x00C33B00,
[ASPEED_AST1700_DEV_LTPI_CTRL] = 0x00C34000,
[ASPEED_AST1700_DEV_SPI0_MEM] = 0x04000000,
@@ -94,6 +96,14 @@ static void aspeed_ast1700_realize(DeviceState *dev, Error **errp)
aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_SPI0_MEM],
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->spi), 1));
+ /* ADC */
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) {
+ return;
+ }
+ memory_region_add_subregion(&s->iomem,
+ aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_ADC],
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->adc), 0));
+
/* LTPI controller */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->ltpi), errp)) {
return;
@@ -121,6 +131,11 @@ static void aspeed_ast1700_instance_init(Object *obj)
snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", 0, socname);
object_initialize_child(obj, "ioexp-spi[*]", &s->spi,
typename);
+
+ /* ADC */
+ snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname);
+ object_initialize_child(obj, "ioexp-adc[*]", &s->adc,
+ typename);
/* LTPI controller */
object_initialize_child(obj, "ltpi-ctrl",
&s->ltpi, TYPE_ASPEED_LTPI);
--
2.43.0
^ permalink raw reply related [flat|nested] 46+ messages in thread* [PATCH v2 11/17] hw/arm/aspeed: Attach SCU device to AST1700 model
2025-11-05 3:58 [PATCH v2 00/17] hw/arm/aspeed: AST1700 LTPI support and device hookups Kane Chen via
` (9 preceding siblings ...)
2025-11-05 3:58 ` [PATCH v2 10/17] hw/arm/aspeed: Attach ADC " Kane Chen via
@ 2025-11-05 3:58 ` Kane Chen via
2025-11-05 3:58 ` [PATCH v2 12/17] hw/arm/aspeed: Attach GPIO " Kane Chen via
` (7 subsequent siblings)
18 siblings, 0 replies; 46+ messages in thread
From: Kane Chen via @ 2025-11-05 3:58 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, Kane-Chen-AS
From: Kane-Chen-AS <kane_chen@aspeedtech.com>
Connect the SCU device to AST1700 model.
Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
---
include/hw/misc/aspeed_ast1700.h | 2 ++
hw/arm/aspeed_ast27x0.c | 2 ++
hw/misc/aspeed_ast1700.c | 17 +++++++++++++++++
3 files changed, 21 insertions(+)
diff --git a/include/hw/misc/aspeed_ast1700.h b/include/hw/misc/aspeed_ast1700.h
index dc9aa08c24..c54600281e 100644
--- a/include/hw/misc/aspeed_ast1700.h
+++ b/include/hw/misc/aspeed_ast1700.h
@@ -29,12 +29,14 @@ struct AspeedAST1700SoCState {
MemoryRegion iomem;
hwaddr mapped_base;
+ uint32_t silicon_rev;
AspeedLTPIState ltpi;
SerialMM uart;
MemoryRegion sram;
AspeedSMCState spi;
AspeedADCState adc;
+ AspeedSCUState scu;
};
#endif /* ASPEED_AST1700_H */
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 75bb18b9c1..312a1a7eea 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -560,6 +560,8 @@ static void aspeed_soc_ast2700_init(Object *obj)
/* AST1700 IOEXP */
object_initialize_child(obj, "ioexp[*]", &s->ioexp[i],
TYPE_ASPEED_AST1700_AST2700);
+ qdev_prop_set_uint32(DEVICE(&s->ioexp[i]), "silicon-rev",
+ sc->silicon_rev);
}
object_initialize_child(obj, "dpmcu", &s->dpmcu,
diff --git a/hw/misc/aspeed_ast1700.c b/hw/misc/aspeed_ast1700.c
index d06603a048..9b203afb9c 100644
--- a/hw/misc/aspeed_ast1700.c
+++ b/hw/misc/aspeed_ast1700.c
@@ -23,6 +23,7 @@ enum {
ASPEED_AST1700_DEV_SPI0,
ASPEED_AST1700_DEV_SRAM,
ASPEED_AST1700_DEV_ADC,
+ ASPEED_AST1700_DEV_SCU,
ASPEED_AST1700_DEV_UART12,
ASPEED_AST1700_DEV_LTPI_CTRL,
ASPEED_AST1700_DEV_SPI0_MEM,
@@ -32,6 +33,7 @@ static const hwaddr aspeed_ast1700_io_memmap[] = {
[ASPEED_AST1700_DEV_SPI0] = 0x00030000,
[ASPEED_AST1700_DEV_SRAM] = 0x00BC0000,
[ASPEED_AST1700_DEV_ADC] = 0x00C00000,
+ [ASPEED_AST1700_DEV_SCU] = 0x00C02000,
[ASPEED_AST1700_DEV_UART12] = 0x00C33B00,
[ASPEED_AST1700_DEV_LTPI_CTRL] = 0x00C34000,
[ASPEED_AST1700_DEV_SPI0_MEM] = 0x04000000,
@@ -104,6 +106,16 @@ static void aspeed_ast1700_realize(DeviceState *dev, Error **errp)
aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_ADC],
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->adc), 0));
+ /* SCU */
+ qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
+ s->silicon_rev);
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
+ return;
+ }
+ memory_region_add_subregion(&s->iomem,
+ aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_SCU],
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->scu), 0));
+
/* LTPI controller */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->ltpi), errp)) {
return;
@@ -136,6 +148,10 @@ static void aspeed_ast1700_instance_init(Object *obj)
snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname);
object_initialize_child(obj, "ioexp-adc[*]", &s->adc,
typename);
+
+ /* SCU */
+ object_initialize_child(obj, "ioexp-scu[*]", &s->scu,
+ TYPE_ASPEED_2700_SCU);
/* LTPI controller */
object_initialize_child(obj, "ltpi-ctrl",
&s->ltpi, TYPE_ASPEED_LTPI);
@@ -145,6 +161,7 @@ static void aspeed_ast1700_instance_init(Object *obj)
static const Property aspeed_ast1700_props[] = {
DEFINE_PROP_UINT64("mapped-base", AspeedAST1700SoCState, mapped_base, 0),
+ DEFINE_PROP_UINT32("silicon-rev", AspeedAST1700SoCState, silicon_rev, 0),
};
static void aspeed_ast1700_class_init(ObjectClass *klass, const void *data)
--
2.43.0
^ permalink raw reply related [flat|nested] 46+ messages in thread* [PATCH v2 12/17] hw/arm/aspeed: Attach GPIO device to AST1700 model
2025-11-05 3:58 [PATCH v2 00/17] hw/arm/aspeed: AST1700 LTPI support and device hookups Kane Chen via
` (10 preceding siblings ...)
2025-11-05 3:58 ` [PATCH v2 11/17] hw/arm/aspeed: Attach SCU " Kane Chen via
@ 2025-11-05 3:58 ` Kane Chen via
2025-11-05 3:58 ` [PATCH v2 13/17] hw/arm/aspeed: Attach I2C " Kane Chen via
` (6 subsequent siblings)
18 siblings, 0 replies; 46+ messages in thread
From: Kane Chen via @ 2025-11-05 3:58 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, Kane-Chen-AS
From: Kane-Chen-AS <kane_chen@aspeedtech.com>
Connect the GPIO controller to the AST1700 model by mapping its MMIO
region and wiring its interrupt line.
Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
---
include/hw/misc/aspeed_ast1700.h | 1 +
hw/arm/aspeed_ast27x0.c | 4 ++++
hw/misc/aspeed_ast1700.c | 14 ++++++++++++++
3 files changed, 19 insertions(+)
diff --git a/include/hw/misc/aspeed_ast1700.h b/include/hw/misc/aspeed_ast1700.h
index c54600281e..37bbb7932f 100644
--- a/include/hw/misc/aspeed_ast1700.h
+++ b/include/hw/misc/aspeed_ast1700.h
@@ -37,6 +37,7 @@ struct AspeedAST1700SoCState {
AspeedSMCState spi;
AspeedADCState adc;
AspeedSCUState scu;
+ AspeedGPIOState gpio;
};
#endif /* ASPEED_AST1700_H */
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 312a1a7eea..fb03fbebfd 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -1098,6 +1098,10 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
/* ADC */
sysbus_connect_irq(SYS_BUS_DEVICE(&s->ioexp[i].adc), 0,
aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_ADC));
+
+ /* GPIO */
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->ioexp[i].gpio), 0,
+ aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_GPIO));
}
aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->dpmcu),
diff --git a/hw/misc/aspeed_ast1700.c b/hw/misc/aspeed_ast1700.c
index 9b203afb9c..2b2934155b 100644
--- a/hw/misc/aspeed_ast1700.c
+++ b/hw/misc/aspeed_ast1700.c
@@ -24,6 +24,7 @@ enum {
ASPEED_AST1700_DEV_SRAM,
ASPEED_AST1700_DEV_ADC,
ASPEED_AST1700_DEV_SCU,
+ ASPEED_AST1700_DEV_GPIO,
ASPEED_AST1700_DEV_UART12,
ASPEED_AST1700_DEV_LTPI_CTRL,
ASPEED_AST1700_DEV_SPI0_MEM,
@@ -34,6 +35,7 @@ static const hwaddr aspeed_ast1700_io_memmap[] = {
[ASPEED_AST1700_DEV_SRAM] = 0x00BC0000,
[ASPEED_AST1700_DEV_ADC] = 0x00C00000,
[ASPEED_AST1700_DEV_SCU] = 0x00C02000,
+ [ASPEED_AST1700_DEV_GPIO] = 0x00C0B000,
[ASPEED_AST1700_DEV_UART12] = 0x00C33B00,
[ASPEED_AST1700_DEV_LTPI_CTRL] = 0x00C34000,
[ASPEED_AST1700_DEV_SPI0_MEM] = 0x04000000,
@@ -116,6 +118,14 @@ static void aspeed_ast1700_realize(DeviceState *dev, Error **errp)
aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_SCU],
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->scu), 0));
+ /* GPIO */
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
+ return;
+ }
+ memory_region_add_subregion(&s->iomem,
+ aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_GPIO],
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gpio), 0));
+
/* LTPI controller */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->ltpi), errp)) {
return;
@@ -152,6 +162,10 @@ static void aspeed_ast1700_instance_init(Object *obj)
/* SCU */
object_initialize_child(obj, "ioexp-scu[*]", &s->scu,
TYPE_ASPEED_2700_SCU);
+
+ /* GPIO */
+ snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname);
+ object_initialize_child(obj, "ioexp-gpio[*]", &s->gpio, typename);
/* LTPI controller */
object_initialize_child(obj, "ltpi-ctrl",
&s->ltpi, TYPE_ASPEED_LTPI);
--
2.43.0
^ permalink raw reply related [flat|nested] 46+ messages in thread* [PATCH v2 13/17] hw/arm/aspeed: Attach I2C device to AST1700 model
2025-11-05 3:58 [PATCH v2 00/17] hw/arm/aspeed: AST1700 LTPI support and device hookups Kane Chen via
` (11 preceding siblings ...)
2025-11-05 3:58 ` [PATCH v2 12/17] hw/arm/aspeed: Attach GPIO " Kane Chen via
@ 2025-11-05 3:58 ` Kane Chen via
2025-11-05 3:58 ` [PATCH v2 14/17] hw/arm/aspeed: Attach WDT " Kane Chen via
` (5 subsequent siblings)
18 siblings, 0 replies; 46+ messages in thread
From: Kane Chen via @ 2025-11-05 3:58 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, Kane-Chen-AS
From: Kane-Chen-AS <kane_chen@aspeedtech.com>
Connect the I2C controller to the AST1700 model by mapping its MMIO
region and wiring its interrupt line.
Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
---
include/hw/arm/aspeed_soc.h | 2 ++
include/hw/misc/aspeed_ast1700.h | 1 +
hw/arm/aspeed_ast27x0.c | 39 ++++++++++++++++++++++++++++++--
hw/misc/aspeed_ast1700.c | 17 ++++++++++++++
4 files changed, 57 insertions(+), 2 deletions(-)
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index 66a6a073f6..464ef2d755 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -283,6 +283,8 @@ enum {
ASPEED_DEV_IPC1,
ASPEED_DEV_LTPI_CTRL1,
ASPEED_DEV_LTPI_CTRL2,
+ ASPEED_DEV_IOEXP0_I2C,
+ ASPEED_DEV_IOEXP1_I2C,
ASPEED_DEV_IOEXP0_INTCIO,
ASPEED_DEV_IOEXP1_INTCIO,
};
diff --git a/include/hw/misc/aspeed_ast1700.h b/include/hw/misc/aspeed_ast1700.h
index 37bbb7932f..4aefb7ea35 100644
--- a/include/hw/misc/aspeed_ast1700.h
+++ b/include/hw/misc/aspeed_ast1700.h
@@ -38,6 +38,7 @@ struct AspeedAST1700SoCState {
AspeedADCState adc;
AspeedSCUState scu;
AspeedGPIOState gpio;
+ AspeedI2CState i2c;
};
#endif /* ASPEED_AST1700_H */
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index fb03fbebfd..a5d98f541b 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -199,6 +199,8 @@ static const int aspeed_soc_ast2700a1_irqmap[] = {
[ASPEED_DEV_ETH3] = 196,
[ASPEED_DEV_PECI] = 197,
[ASPEED_DEV_SDHCI] = 197,
+ [ASPEED_DEV_IOEXP0_I2C] = 198,
+ [ASPEED_DEV_IOEXP1_I2C] = 200,
};
/* GICINT 128 */
@@ -259,6 +261,17 @@ static const int ast2700_gic133_gic197_intcmap[] = {
[ASPEED_DEV_PECI] = 4,
};
+/* Primary AST1700 Interrupts */
+/* A1: GICINT 198 */
+static const int ast2700_gic198_intcmap[] = {
+ [ASPEED_DEV_IOEXP0_I2C] = 0, /* 0 - 15 */
+};
+
+/* Secondary AST1700 Interrupts */
+/* A1: GINTC 200 */
+static const int ast2700_gic200_intcmap[] = {
+ [ASPEED_DEV_IOEXP1_I2C] = 0, /* 0 - 15 */
+};
/* GICINT 128 ~ 136 */
/* GICINT 192 ~ 201 */
struct gic_intc_irq_info {
@@ -275,9 +288,9 @@ static const struct gic_intc_irq_info ast2700_gic_intcmap[] = {
{195, 1, 3, ast2700_gic131_gic195_intcmap},
{196, 1, 4, ast2700_gic132_gic196_intcmap},
{197, 1, 5, ast2700_gic133_gic197_intcmap},
- {198, 1, 6, NULL},
+ {198, 2, 0, ast2700_gic198_intcmap},
{199, 1, 7, NULL},
- {200, 1, 8, NULL},
+ {200, 3, 0, ast2700_gic200_intcmap},
{201, 1, 9, NULL},
{128, 0, 1, ast2700_gic128_gic192_intcmap},
{129, 0, 2, NULL},
@@ -708,6 +721,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
qemu_irq irq;
int uart;
int j;
+ AspeedI2CClass *i2c_ctl;
AspeedLTPIState *ltpi_ctrl;
hwaddr ltpi_base;
@@ -1102,6 +1116,27 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
/* GPIO */
sysbus_connect_irq(SYS_BUS_DEVICE(&s->ioexp[i].gpio), 0,
aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_GPIO));
+
+ /* I2C */
+ i2c_ctl = ASPEED_I2C_GET_CLASS(&s->ioexp[i].i2c);
+ for (j = 0; j < i2c_ctl->num_busses; j++) {
+ /*
+ * For I2C on AST1700:
+ * I2C bus interrupts are connected to the OR gate from bit 0 to bit
+ * 15, and the OR gate output pin is connected to the input pin of
+ * GICINT192 of IO expander Interrupt controller (INTC2/3). Then,
+ * the output pin is connected to the INTC (CPU Die) input pin, and
+ * its output pin is connected to the GIC.
+ *
+ * I2C bus 0 is connected to the OR gate at bit 0.
+ * I2C bus 15 is connected to the OR gate at bit 15.
+ */
+ irq = aspeed_soc_ast2700_get_irq_index(s,
+ ASPEED_DEV_IOEXP0_I2C + i,
+ j);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->ioexp[i].i2c.busses[j]),
+ 0, irq);
+ }
}
aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->dpmcu),
diff --git a/hw/misc/aspeed_ast1700.c b/hw/misc/aspeed_ast1700.c
index 2b2934155b..6c7483c88c 100644
--- a/hw/misc/aspeed_ast1700.c
+++ b/hw/misc/aspeed_ast1700.c
@@ -25,6 +25,7 @@ enum {
ASPEED_AST1700_DEV_ADC,
ASPEED_AST1700_DEV_SCU,
ASPEED_AST1700_DEV_GPIO,
+ ASPEED_AST1700_DEV_I2C,
ASPEED_AST1700_DEV_UART12,
ASPEED_AST1700_DEV_LTPI_CTRL,
ASPEED_AST1700_DEV_SPI0_MEM,
@@ -36,6 +37,7 @@ static const hwaddr aspeed_ast1700_io_memmap[] = {
[ASPEED_AST1700_DEV_ADC] = 0x00C00000,
[ASPEED_AST1700_DEV_SCU] = 0x00C02000,
[ASPEED_AST1700_DEV_GPIO] = 0x00C0B000,
+ [ASPEED_AST1700_DEV_I2C] = 0x00C0F000,
[ASPEED_AST1700_DEV_UART12] = 0x00C33B00,
[ASPEED_AST1700_DEV_LTPI_CTRL] = 0x00C34000,
[ASPEED_AST1700_DEV_SPI0_MEM] = 0x04000000,
@@ -126,6 +128,16 @@ static void aspeed_ast1700_realize(DeviceState *dev, Error **errp)
aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_GPIO],
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gpio), 0));
+ /* I2C */
+ object_property_set_link(OBJECT(&s->i2c), "dram",
+ OBJECT(&s->iomem), &error_abort);
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) {
+ return;
+ }
+ memory_region_add_subregion(&s->iomem,
+ aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_I2C],
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->i2c), 0));
+
/* LTPI controller */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->ltpi), errp)) {
return;
@@ -166,6 +178,11 @@ static void aspeed_ast1700_instance_init(Object *obj)
/* GPIO */
snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname);
object_initialize_child(obj, "ioexp-gpio[*]", &s->gpio, typename);
+
+ /* I2C */
+ snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname);
+ object_initialize_child(obj, "ioexp-i2c[*]", &s->i2c,
+ typename);
/* LTPI controller */
object_initialize_child(obj, "ltpi-ctrl",
&s->ltpi, TYPE_ASPEED_LTPI);
--
2.43.0
^ permalink raw reply related [flat|nested] 46+ messages in thread* [PATCH v2 14/17] hw/arm/aspeed: Attach WDT device to AST1700 model
2025-11-05 3:58 [PATCH v2 00/17] hw/arm/aspeed: AST1700 LTPI support and device hookups Kane Chen via
` (12 preceding siblings ...)
2025-11-05 3:58 ` [PATCH v2 13/17] hw/arm/aspeed: Attach I2C " Kane Chen via
@ 2025-11-05 3:58 ` Kane Chen via
2025-11-05 3:58 ` [PATCH v2 15/17] hw/arm/aspeed: Model AST1700 I3C block as unimplemented device Kane Chen via
` (4 subsequent siblings)
18 siblings, 0 replies; 46+ messages in thread
From: Kane Chen via @ 2025-11-05 3:58 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, Kane-Chen-AS
From: Kane-Chen-AS <kane_chen@aspeedtech.com>
Connect the WDT device to AST1700 model.
Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
---
include/hw/misc/aspeed_ast1700.h | 3 +++
hw/misc/aspeed_ast1700.c | 28 ++++++++++++++++++++++++++++
2 files changed, 31 insertions(+)
diff --git a/include/hw/misc/aspeed_ast1700.h b/include/hw/misc/aspeed_ast1700.h
index 4aefb7ea35..f89de44539 100644
--- a/include/hw/misc/aspeed_ast1700.h
+++ b/include/hw/misc/aspeed_ast1700.h
@@ -19,6 +19,8 @@
#include "hw/char/serial-mm.h"
#include "hw/misc/unimp.h"
+#define AST1700_WDT_NUM 9
+
#define TYPE_ASPEED_AST1700 "aspeed.ast1700"
#define TYPE_ASPEED_AST1700_AST2700 "aspeed.ast1700-ast2700"
@@ -39,6 +41,7 @@ struct AspeedAST1700SoCState {
AspeedSCUState scu;
AspeedGPIOState gpio;
AspeedI2CState i2c;
+ AspeedWDTState wdt[AST1700_WDT_NUM];
};
#endif /* ASPEED_AST1700_H */
diff --git a/hw/misc/aspeed_ast1700.c b/hw/misc/aspeed_ast1700.c
index 6c7483c88c..c2dc834b4f 100644
--- a/hw/misc/aspeed_ast1700.c
+++ b/hw/misc/aspeed_ast1700.c
@@ -28,6 +28,7 @@ enum {
ASPEED_AST1700_DEV_I2C,
ASPEED_AST1700_DEV_UART12,
ASPEED_AST1700_DEV_LTPI_CTRL,
+ ASPEED_AST1700_DEV_WDT,
ASPEED_AST1700_DEV_SPI0_MEM,
};
@@ -40,10 +41,13 @@ static const hwaddr aspeed_ast1700_io_memmap[] = {
[ASPEED_AST1700_DEV_I2C] = 0x00C0F000,
[ASPEED_AST1700_DEV_UART12] = 0x00C33B00,
[ASPEED_AST1700_DEV_LTPI_CTRL] = 0x00C34000,
+ [ASPEED_AST1700_DEV_WDT] = 0x00C37000,
[ASPEED_AST1700_DEV_SPI0_MEM] = 0x04000000,
};
+
static void aspeed_ast1700_realize(DeviceState *dev, Error **errp)
{
+ int i;
AspeedAST1700SoCState *s = ASPEED_AST1700(dev);
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
hwaddr uart_base;
@@ -145,10 +149,27 @@ static void aspeed_ast1700_realize(DeviceState *dev, Error **errp)
memory_region_add_subregion(&s->iomem,
aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_LTPI_CTRL],
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->ltpi), 0));
+
+ /* WDT */
+ for (i = 0; i < AST1700_WDT_NUM; i++) {
+ AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
+ hwaddr wdt_offset = aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_WDT] +
+ i * awc->iosize;
+
+ object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu),
+ &error_abort);
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) {
+ return;
+ }
+ memory_region_add_subregion(&s->iomem,
+ wdt_offset,
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->wdt[i]), 0));
+ }
}
static void aspeed_ast1700_instance_init(Object *obj)
{
+ int i;
AspeedAST1700SoCState *s = ASPEED_AST1700(obj);
char socname[8];
char typename[64];
@@ -187,6 +208,13 @@ static void aspeed_ast1700_instance_init(Object *obj)
object_initialize_child(obj, "ltpi-ctrl",
&s->ltpi, TYPE_ASPEED_LTPI);
+ /* WDT */
+ for (i = 0; i < AST1700_WDT_NUM; i++) {
+ snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname);
+ object_initialize_child(obj, "ioexp-wdt[*]",
+ &s->wdt[i], typename);
+ }
+
return;
}
--
2.43.0
^ permalink raw reply related [flat|nested] 46+ messages in thread* [PATCH v2 15/17] hw/arm/aspeed: Model AST1700 I3C block as unimplemented device
2025-11-05 3:58 [PATCH v2 00/17] hw/arm/aspeed: AST1700 LTPI support and device hookups Kane Chen via
` (13 preceding siblings ...)
2025-11-05 3:58 ` [PATCH v2 14/17] hw/arm/aspeed: Attach WDT " Kane Chen via
@ 2025-11-05 3:58 ` Kane Chen via
2025-11-07 8:06 ` Cédric Le Goater
2025-11-05 3:58 ` [PATCH v2 16/17] hw/arm/aspeed: Model AST1700 SGPIOM " Kane Chen via
` (3 subsequent siblings)
18 siblings, 1 reply; 46+ messages in thread
From: Kane Chen via @ 2025-11-05 3:58 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, Kane-Chen-AS
From: Kane-Chen-AS <kane_chen@aspeedtech.com>
AST1700 exposes more I3C buses than the current dummy I3C model
provides. When Linux probes the I3C devices on AST1700 this mismatch
can trigger a kernel panic. Model the I3C block as an unimplemented
device to make the missing functionality explicit and avoid unexpected
side effects.
This wires up the I3C interrupt lines for the IO expanders and adds the
corresponding device entries for the AST1700 model.
No functional I3C emulation is provided yet; this only prevents crashes and
documents the missing piece.
Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
---
include/hw/arm/aspeed_soc.h | 2 ++
include/hw/misc/aspeed_ast1700.h | 2 ++
hw/arm/aspeed_ast27x0.c | 19 +++++++++++++++++--
hw/misc/aspeed_ast1700.c | 17 +++++++++++++++++
4 files changed, 38 insertions(+), 2 deletions(-)
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index 464ef2d755..c58c861841 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -287,6 +287,8 @@ enum {
ASPEED_DEV_IOEXP1_I2C,
ASPEED_DEV_IOEXP0_INTCIO,
ASPEED_DEV_IOEXP1_INTCIO,
+ ASPEED_DEV_IOEXP0_I3C,
+ ASPEED_DEV_IOEXP1_I3C,
};
const char *aspeed_soc_cpu_type(const char * const *valid_cpu_types);
diff --git a/include/hw/misc/aspeed_ast1700.h b/include/hw/misc/aspeed_ast1700.h
index f89de44539..4048d31154 100644
--- a/include/hw/misc/aspeed_ast1700.h
+++ b/include/hw/misc/aspeed_ast1700.h
@@ -42,6 +42,8 @@ struct AspeedAST1700SoCState {
AspeedGPIOState gpio;
AspeedI2CState i2c;
AspeedWDTState wdt[AST1700_WDT_NUM];
+
+ UnimplementedDeviceState i3c;
};
#endif /* ASPEED_AST1700_H */
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index a5d98f541b..f8dd4f6a3a 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -200,7 +200,9 @@ static const int aspeed_soc_ast2700a1_irqmap[] = {
[ASPEED_DEV_PECI] = 197,
[ASPEED_DEV_SDHCI] = 197,
[ASPEED_DEV_IOEXP0_I2C] = 198,
+ [ASPEED_DEV_IOEXP0_I3C] = 199,
[ASPEED_DEV_IOEXP1_I2C] = 200,
+ [ASPEED_DEV_IOEXP1_I3C] = 201,
};
/* GICINT 128 */
@@ -267,11 +269,24 @@ static const int ast2700_gic198_intcmap[] = {
[ASPEED_DEV_IOEXP0_I2C] = 0, /* 0 - 15 */
};
+/* Primary AST1700 Interrupts */
+/* A1: GINTC 199 */
+static const int ast2700_gic199_intcmap[] = {
+ [ASPEED_DEV_IOEXP0_I3C] = 0, /* 0 - 15 */
+};
+
/* Secondary AST1700 Interrupts */
/* A1: GINTC 200 */
static const int ast2700_gic200_intcmap[] = {
[ASPEED_DEV_IOEXP1_I2C] = 0, /* 0 - 15 */
};
+
+/* Secondary AST1700 Interrupts */
+/* A1: GINTC 201 */
+static const int ast2700_gic201_intcmap[] = {
+ [ASPEED_DEV_IOEXP1_I3C] = 0, /* 0 - 15 */
+};
+
/* GICINT 128 ~ 136 */
/* GICINT 192 ~ 201 */
struct gic_intc_irq_info {
@@ -289,9 +304,9 @@ static const struct gic_intc_irq_info ast2700_gic_intcmap[] = {
{196, 1, 4, ast2700_gic132_gic196_intcmap},
{197, 1, 5, ast2700_gic133_gic197_intcmap},
{198, 2, 0, ast2700_gic198_intcmap},
- {199, 1, 7, NULL},
+ {199, 2, 1, ast2700_gic199_intcmap},
{200, 3, 0, ast2700_gic200_intcmap},
- {201, 1, 9, NULL},
+ {201, 3, 1, ast2700_gic201_intcmap},
{128, 0, 1, ast2700_gic128_gic192_intcmap},
{129, 0, 2, NULL},
{130, 0, 3, ast2700_gic130_gic194_intcmap},
diff --git a/hw/misc/aspeed_ast1700.c b/hw/misc/aspeed_ast1700.c
index c2dc834b4f..37b2946fc0 100644
--- a/hw/misc/aspeed_ast1700.c
+++ b/hw/misc/aspeed_ast1700.c
@@ -18,6 +18,7 @@
#define AST1700_BOARD1_MEM_ADDR 0x30000000
#define AST2700_SOC_LTPI_SIZE 0x01000000
#define AST1700_SOC_SRAM_SIZE 0x00040000
+#define AST1700_SOC_I3C_SIZE 0x00010000
enum {
ASPEED_AST1700_DEV_SPI0,
@@ -26,6 +27,7 @@ enum {
ASPEED_AST1700_DEV_SCU,
ASPEED_AST1700_DEV_GPIO,
ASPEED_AST1700_DEV_I2C,
+ ASPEED_AST1700_DEV_I3C,
ASPEED_AST1700_DEV_UART12,
ASPEED_AST1700_DEV_LTPI_CTRL,
ASPEED_AST1700_DEV_WDT,
@@ -39,6 +41,7 @@ static const hwaddr aspeed_ast1700_io_memmap[] = {
[ASPEED_AST1700_DEV_SCU] = 0x00C02000,
[ASPEED_AST1700_DEV_GPIO] = 0x00C0B000,
[ASPEED_AST1700_DEV_I2C] = 0x00C0F000,
+ [ASPEED_AST1700_DEV_I3C] = 0x00C20000,
[ASPEED_AST1700_DEV_UART12] = 0x00C33B00,
[ASPEED_AST1700_DEV_LTPI_CTRL] = 0x00C34000,
[ASPEED_AST1700_DEV_WDT] = 0x00C37000,
@@ -142,6 +145,15 @@ static void aspeed_ast1700_realize(DeviceState *dev, Error **errp)
aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_I2C],
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->i2c), 0));
+ /* I3C */
+ qdev_prop_set_string(DEVICE(&s->i3c), "name", "ioexp-i3c");
+ qdev_prop_set_uint64(DEVICE(&s->i3c), "size", AST1700_SOC_I3C_SIZE);
+ sysbus_realize(SYS_BUS_DEVICE(&s->i3c), errp);
+ memory_region_add_subregion_overlap(&s->iomem,
+ aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_I3C],
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->i3c), 0),
+ -1000);
+
/* LTPI controller */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->ltpi), errp)) {
return;
@@ -204,6 +216,11 @@ static void aspeed_ast1700_instance_init(Object *obj)
snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname);
object_initialize_child(obj, "ioexp-i2c[*]", &s->i2c,
typename);
+
+ /* I3C */
+ object_initialize_child(obj, "ioexp-i3c[*]", &s->i3c,
+ TYPE_UNIMPLEMENTED_DEVICE);
+
/* LTPI controller */
object_initialize_child(obj, "ltpi-ctrl",
&s->ltpi, TYPE_ASPEED_LTPI);
--
2.43.0
^ permalink raw reply related [flat|nested] 46+ messages in thread* Re: [PATCH v2 15/17] hw/arm/aspeed: Model AST1700 I3C block as unimplemented device
2025-11-05 3:58 ` [PATCH v2 15/17] hw/arm/aspeed: Model AST1700 I3C block as unimplemented device Kane Chen via
@ 2025-11-07 8:06 ` Cédric Le Goater
2025-11-07 8:41 ` Kane Chen
0 siblings, 1 reply; 46+ messages in thread
From: Cédric Le Goater @ 2025-11-07 8:06 UTC (permalink / raw)
To: Kane Chen, Peter Maydell, Steven Lee, Troy Lee, Jamin Lin,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here, Joe Komlodi, Patrick Leis
Cc: troy_lee
Hello,
+ Joe, Patrick
On 11/5/25 04:58, Kane Chen wrote:
> From: Kane-Chen-AS <kane_chen@aspeedtech.com>
>
> AST1700 exposes more I3C buses than the current dummy I3C model
> provides. When Linux probes the I3C devices on AST1700 this mismatch
> can trigger a kernel panic. Model the I3C block as an unimplemented
> device to make the missing functionality explicit and avoid unexpected
> side effects.
>
> This wires up the I3C interrupt lines for the IO expanders and adds the
> corresponding device entries for the AST1700 model.
>
> No functional I3C emulation is provided yet; this only prevents crashes and
> documents the missing piece.
>
> Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
> ---
> include/hw/arm/aspeed_soc.h | 2 ++
> include/hw/misc/aspeed_ast1700.h | 2 ++
> hw/arm/aspeed_ast27x0.c | 19 +++++++++++++++++--
> hw/misc/aspeed_ast1700.c | 17 +++++++++++++++++
> 4 files changed, 38 insertions(+), 2 deletions(-)
Joe sent (twice) changes adding I3C support [1].
I’ve been maintaining it in my branch, and from both a code and testing
perspective, it looks solid. I believe it’s ready to be merged. We now
just need maintainers and reviewers to step in.
Would it be useful for this model ? If so, that would be an additional
reason.
Thanks,
C.
[1] https://lore.kernel.org/qemu-devel/20250613000411.1516521-1-komlodi@google.com/
^ permalink raw reply [flat|nested] 46+ messages in thread
* RE: [PATCH v2 15/17] hw/arm/aspeed: Model AST1700 I3C block as unimplemented device
2025-11-07 8:06 ` Cédric Le Goater
@ 2025-11-07 8:41 ` Kane Chen
0 siblings, 0 replies; 46+ messages in thread
From: Kane Chen @ 2025-11-07 8:41 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here, Joe Komlodi, Patrick Leis
Cc: Troy Lee
Hi Cédric,
If I use the current I3C model, it causes a kernel crash because the value of
ASPEED_I3C_NR_DEVICES is smaller than what AST1700 supports:
https://github.com/qemu/qemu/blob/master/include/hw/misc/aspeed_i3c.h#L21
The AST1700 can support up to 16 I3C buses. In the current I3C model (and in Joe's patches),
the value of ASPEED_I3C_NR_DEVICES remains 6, so I would encounter the same issue if
I used them directly.
I plan to either increase the value of ASPEED_I3C_NR_DEVICES or add a configurable method
to set the number of I3C buses after Joe's patches are merged.
After that, I'll update the AST1700 I3C model to use the new I3C framework.
If you have any comments or suggestions, please let me know.
Best Regards,
Kane
> -----Original Message-----
> From: Cédric Le Goater <clg@kaod.org>
> Sent: Friday, November 7, 2025 4:06 PM
> To: Kane Chen <kane_chen@aspeedtech.com>; Peter Maydell
> <peter.maydell@linaro.org>; Steven Lee <steven_lee@aspeedtech.com>; Troy
> Lee <leetroy@gmail.com>; Jamin Lin <jamin_lin@aspeedtech.com>; Andrew
> Jeffery <andrew@codeconstruct.com.au>; Joel Stanley <joel@jms.id.au>;
> open list:ASPEED BMCs <qemu-arm@nongnu.org>; open list:All patches CC
> here <qemu-devel@nongnu.org>; Joe Komlodi <komlodi@google.com>;
> Patrick Leis <venture@google.com>
> Cc: Troy Lee <troy_lee@aspeedtech.com>
> Subject: Re: [PATCH v2 15/17] hw/arm/aspeed: Model AST1700 I3C block as
> unimplemented device
>
> Hello,
>
> + Joe, Patrick
>
> On 11/5/25 04:58, Kane Chen wrote:
> > From: Kane-Chen-AS <kane_chen@aspeedtech.com>
> >
> > AST1700 exposes more I3C buses than the current dummy I3C model
> > provides. When Linux probes the I3C devices on AST1700 this mismatch
> > can trigger a kernel panic. Model the I3C block as an unimplemented
> > device to make the missing functionality explicit and avoid unexpected
> > side effects.
> >
> > This wires up the I3C interrupt lines for the IO expanders and adds
> > the corresponding device entries for the AST1700 model.
> >
> > No functional I3C emulation is provided yet; this only prevents
> > crashes and documents the missing piece.
> >
> > Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
> > ---
> > include/hw/arm/aspeed_soc.h | 2 ++
> > include/hw/misc/aspeed_ast1700.h | 2 ++
> > hw/arm/aspeed_ast27x0.c | 19 +++++++++++++++++--
> > hw/misc/aspeed_ast1700.c | 17 +++++++++++++++++
> > 4 files changed, 38 insertions(+), 2 deletions(-)
>
> Joe sent (twice) changes adding I3C support [1].
>
> I’ve been maintaining it in my branch, and from both a code and testing
> perspective, it looks solid. I believe it’s ready to be merged. We now just need
> maintainers and reviewers to step in.
>
> Would it be useful for this model ? If so, that would be an additional reason.
>
> Thanks,
>
> C.
>
> [1]
> https://lore.kernel.org/qemu-devel/20250613000411.1516521-1-komlodi@g
> oogle.com/
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH v2 16/17] hw/arm/aspeed: Model AST1700 SGPIOM block as unimplemented device
2025-11-05 3:58 [PATCH v2 00/17] hw/arm/aspeed: AST1700 LTPI support and device hookups Kane Chen via
` (14 preceding siblings ...)
2025-11-05 3:58 ` [PATCH v2 15/17] hw/arm/aspeed: Model AST1700 I3C block as unimplemented device Kane Chen via
@ 2025-11-05 3:58 ` Kane Chen via
2025-11-10 16:14 ` Cédric Le Goater
2025-11-05 3:58 ` [PATCH v2 17/17] hw/arm/aspeed: Model AST1700 PWM " Kane Chen via
` (2 subsequent siblings)
18 siblings, 1 reply; 46+ messages in thread
From: Kane Chen via @ 2025-11-05 3:58 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, Kane-Chen-AS
From: Kane-Chen-AS <kane_chen@aspeedtech.com>
AST1700 includes an SGPIOM block, but QEMU has no functional model yet.
Expose it as an unimplemented device so the address space is reserved and
the missing functionality is explicit to users/guests.
Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
---
include/hw/misc/aspeed_ast1700.h | 1 +
hw/misc/aspeed_ast1700.c | 16 ++++++++++++++++
2 files changed, 17 insertions(+)
diff --git a/include/hw/misc/aspeed_ast1700.h b/include/hw/misc/aspeed_ast1700.h
index 4048d31154..8ada3a7775 100644
--- a/include/hw/misc/aspeed_ast1700.h
+++ b/include/hw/misc/aspeed_ast1700.h
@@ -44,6 +44,7 @@ struct AspeedAST1700SoCState {
AspeedWDTState wdt[AST1700_WDT_NUM];
UnimplementedDeviceState i3c;
+ UnimplementedDeviceState sgpiom;
};
#endif /* ASPEED_AST1700_H */
diff --git a/hw/misc/aspeed_ast1700.c b/hw/misc/aspeed_ast1700.c
index 37b2946fc0..66a5f21d27 100644
--- a/hw/misc/aspeed_ast1700.c
+++ b/hw/misc/aspeed_ast1700.c
@@ -19,6 +19,7 @@
#define AST2700_SOC_LTPI_SIZE 0x01000000
#define AST1700_SOC_SRAM_SIZE 0x00040000
#define AST1700_SOC_I3C_SIZE 0x00010000
+#define AST1700_SOC_SGPIOM_SIZE 0x00002000
enum {
ASPEED_AST1700_DEV_SPI0,
@@ -26,6 +27,7 @@ enum {
ASPEED_AST1700_DEV_ADC,
ASPEED_AST1700_DEV_SCU,
ASPEED_AST1700_DEV_GPIO,
+ ASPEED_AST1700_DEV_SGPIOM,
ASPEED_AST1700_DEV_I2C,
ASPEED_AST1700_DEV_I3C,
ASPEED_AST1700_DEV_UART12,
@@ -40,6 +42,7 @@ static const hwaddr aspeed_ast1700_io_memmap[] = {
[ASPEED_AST1700_DEV_ADC] = 0x00C00000,
[ASPEED_AST1700_DEV_SCU] = 0x00C02000,
[ASPEED_AST1700_DEV_GPIO] = 0x00C0B000,
+ [ASPEED_AST1700_DEV_SGPIOM] = 0x00C0C000,
[ASPEED_AST1700_DEV_I2C] = 0x00C0F000,
[ASPEED_AST1700_DEV_I3C] = 0x00C20000,
[ASPEED_AST1700_DEV_UART12] = 0x00C33B00,
@@ -162,6 +165,15 @@ static void aspeed_ast1700_realize(DeviceState *dev, Error **errp)
aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_LTPI_CTRL],
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->ltpi), 0));
+ /* SGPIOM */
+ qdev_prop_set_string(DEVICE(&s->sgpiom), "name", "ioexp-sgpiom");
+ qdev_prop_set_uint64(DEVICE(&s->sgpiom), "size", AST1700_SOC_SGPIOM_SIZE);
+ sysbus_realize(SYS_BUS_DEVICE(&s->sgpiom), errp);
+ memory_region_add_subregion_overlap(&s->iomem,
+ aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_SGPIOM],
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->sgpiom), 0),
+ -1000);
+
/* WDT */
for (i = 0; i < AST1700_WDT_NUM; i++) {
AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
@@ -225,6 +237,10 @@ static void aspeed_ast1700_instance_init(Object *obj)
object_initialize_child(obj, "ltpi-ctrl",
&s->ltpi, TYPE_ASPEED_LTPI);
+ /* SGPIOM */
+ object_initialize_child(obj, "ioexp-sgpiom[*]", &s->sgpiom,
+ TYPE_UNIMPLEMENTED_DEVICE);
+
/* WDT */
for (i = 0; i < AST1700_WDT_NUM; i++) {
snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname);
--
2.43.0
^ permalink raw reply related [flat|nested] 46+ messages in thread* Re: [PATCH v2 16/17] hw/arm/aspeed: Model AST1700 SGPIOM block as unimplemented device
2025-11-05 3:58 ` [PATCH v2 16/17] hw/arm/aspeed: Model AST1700 SGPIOM " Kane Chen via
@ 2025-11-10 16:14 ` Cédric Le Goater
2025-11-11 1:33 ` Kane Chen
0 siblings, 1 reply; 46+ messages in thread
From: Cédric Le Goater @ 2025-11-10 16:14 UTC (permalink / raw)
To: Kane Chen, Peter Maydell, Steven Lee, Troy Lee, Jamin Lin,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here, Yubin Zou
Cc: troy_lee
Hello,
On 11/5/25 04:58, Kane Chen wrote:
> From: Kane-Chen-AS <kane_chen@aspeedtech.com>
>
> AST1700 includes an SGPIOM block, but QEMU has no functional model yet.
Does the series "hw/gpio: Add Aspeed Serial GPIO (SGPIO) controller" [1] proposed
by Yubin Zou fill this gap ?
Thanks,
C.
[1] https://lore.kernel.org//qemu-devel/20251106-aspeed-sgpio-v1-0-b026093716fa@google.com
> Expose it as an unimplemented device so the address space is reserved and
> the missing functionality is explicit to users/guests.
>
> Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
> ---
> include/hw/misc/aspeed_ast1700.h | 1 +
> hw/misc/aspeed_ast1700.c | 16 ++++++++++++++++
> 2 files changed, 17 insertions(+)
>
> diff --git a/include/hw/misc/aspeed_ast1700.h b/include/hw/misc/aspeed_ast1700.h
> index 4048d31154..8ada3a7775 100644
> --- a/include/hw/misc/aspeed_ast1700.h
> +++ b/include/hw/misc/aspeed_ast1700.h
> @@ -44,6 +44,7 @@ struct AspeedAST1700SoCState {
> AspeedWDTState wdt[AST1700_WDT_NUM];
>
> UnimplementedDeviceState i3c;
> + UnimplementedDeviceState sgpiom;
> };
>
> #endif /* ASPEED_AST1700_H */
> diff --git a/hw/misc/aspeed_ast1700.c b/hw/misc/aspeed_ast1700.c
> index 37b2946fc0..66a5f21d27 100644
> --- a/hw/misc/aspeed_ast1700.c
> +++ b/hw/misc/aspeed_ast1700.c
> @@ -19,6 +19,7 @@
> #define AST2700_SOC_LTPI_SIZE 0x01000000
> #define AST1700_SOC_SRAM_SIZE 0x00040000
> #define AST1700_SOC_I3C_SIZE 0x00010000
> +#define AST1700_SOC_SGPIOM_SIZE 0x00002000
>
> enum {
> ASPEED_AST1700_DEV_SPI0,
> @@ -26,6 +27,7 @@ enum {
> ASPEED_AST1700_DEV_ADC,
> ASPEED_AST1700_DEV_SCU,
> ASPEED_AST1700_DEV_GPIO,
> + ASPEED_AST1700_DEV_SGPIOM,
> ASPEED_AST1700_DEV_I2C,
> ASPEED_AST1700_DEV_I3C,
> ASPEED_AST1700_DEV_UART12,
> @@ -40,6 +42,7 @@ static const hwaddr aspeed_ast1700_io_memmap[] = {
> [ASPEED_AST1700_DEV_ADC] = 0x00C00000,
> [ASPEED_AST1700_DEV_SCU] = 0x00C02000,
> [ASPEED_AST1700_DEV_GPIO] = 0x00C0B000,
> + [ASPEED_AST1700_DEV_SGPIOM] = 0x00C0C000,
> [ASPEED_AST1700_DEV_I2C] = 0x00C0F000,
> [ASPEED_AST1700_DEV_I3C] = 0x00C20000,
> [ASPEED_AST1700_DEV_UART12] = 0x00C33B00,
> @@ -162,6 +165,15 @@ static void aspeed_ast1700_realize(DeviceState *dev, Error **errp)
> aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_LTPI_CTRL],
> sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->ltpi), 0));
>
> + /* SGPIOM */
> + qdev_prop_set_string(DEVICE(&s->sgpiom), "name", "ioexp-sgpiom");
> + qdev_prop_set_uint64(DEVICE(&s->sgpiom), "size", AST1700_SOC_SGPIOM_SIZE);
> + sysbus_realize(SYS_BUS_DEVICE(&s->sgpiom), errp);
> + memory_region_add_subregion_overlap(&s->iomem,
> + aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_SGPIOM],
> + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->sgpiom), 0),
> + -1000);
> +
> /* WDT */
> for (i = 0; i < AST1700_WDT_NUM; i++) {
> AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
> @@ -225,6 +237,10 @@ static void aspeed_ast1700_instance_init(Object *obj)
> object_initialize_child(obj, "ltpi-ctrl",
> &s->ltpi, TYPE_ASPEED_LTPI);
>
> + /* SGPIOM */
> + object_initialize_child(obj, "ioexp-sgpiom[*]", &s->sgpiom,
> + TYPE_UNIMPLEMENTED_DEVICE);
> +
> /* WDT */
> for (i = 0; i < AST1700_WDT_NUM; i++) {
> snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname);
^ permalink raw reply [flat|nested] 46+ messages in thread* RE: [PATCH v2 16/17] hw/arm/aspeed: Model AST1700 SGPIOM block as unimplemented device
2025-11-10 16:14 ` Cédric Le Goater
@ 2025-11-11 1:33 ` Kane Chen
2025-11-12 7:06 ` Cédric Le Goater
0 siblings, 1 reply; 46+ messages in thread
From: Kane Chen @ 2025-11-11 1:33 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here, Yubin Zou
Cc: Troy Lee
Hi Cédric,
Thanks for the information. I'll investigate this model and integrate it.
Best Regards,
Kane
> -----Original Message-----
> From: Cédric Le Goater <clg@kaod.org>
> Sent: Tuesday, November 11, 2025 12:15 AM
> To: Kane Chen <kane_chen@aspeedtech.com>; Peter Maydell
> <peter.maydell@linaro.org>; Steven Lee <steven_lee@aspeedtech.com>; Troy
> Lee <leetroy@gmail.com>; Jamin Lin <jamin_lin@aspeedtech.com>; Andrew
> Jeffery <andrew@codeconstruct.com.au>; Joel Stanley <joel@jms.id.au>;
> open list:ASPEED BMCs <qemu-arm@nongnu.org>; open list:All patches CC
> here <qemu-devel@nongnu.org>; Yubin Zou <yubinz@google.com>
> Cc: Troy Lee <troy_lee@aspeedtech.com>
> Subject: Re: [PATCH v2 16/17] hw/arm/aspeed: Model AST1700 SGPIOM block
> as unimplemented device
>
> Hello,
>
> On 11/5/25 04:58, Kane Chen wrote:
> > From: Kane-Chen-AS <kane_chen@aspeedtech.com>
> >
> > AST1700 includes an SGPIOM block, but QEMU has no functional model yet.
>
> Does the series "hw/gpio: Add Aspeed Serial GPIO (SGPIO) controller" [1]
> proposed by Yubin Zou fill this gap ?
>
> Thanks,
>
> C.
>
> [1]
> https://lore.kernel.org//qemu-devel/20251106-aspeed-sgpio-v1-0-b0260937
> 16fa@google.com
>
>
> > Expose it as an unimplemented device so the address space is reserved
> > and the missing functionality is explicit to users/guests.
> >
> > Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
> > ---
> > include/hw/misc/aspeed_ast1700.h | 1 +
> > hw/misc/aspeed_ast1700.c | 16 ++++++++++++++++
> > 2 files changed, 17 insertions(+)
> >
> > diff --git a/include/hw/misc/aspeed_ast1700.h
> > b/include/hw/misc/aspeed_ast1700.h
> > index 4048d31154..8ada3a7775 100644
> > --- a/include/hw/misc/aspeed_ast1700.h
> > +++ b/include/hw/misc/aspeed_ast1700.h
> > @@ -44,6 +44,7 @@ struct AspeedAST1700SoCState {
> > AspeedWDTState wdt[AST1700_WDT_NUM];
> >
> > UnimplementedDeviceState i3c;
> > + UnimplementedDeviceState sgpiom;
> > };
> >
> > #endif /* ASPEED_AST1700_H */
> > diff --git a/hw/misc/aspeed_ast1700.c b/hw/misc/aspeed_ast1700.c index
> > 37b2946fc0..66a5f21d27 100644
> > --- a/hw/misc/aspeed_ast1700.c
> > +++ b/hw/misc/aspeed_ast1700.c
> > @@ -19,6 +19,7 @@
> > #define AST2700_SOC_LTPI_SIZE 0x01000000
> > #define AST1700_SOC_SRAM_SIZE 0x00040000
> > #define AST1700_SOC_I3C_SIZE 0x00010000
> > +#define AST1700_SOC_SGPIOM_SIZE 0x00002000
> >
> > enum {
> > ASPEED_AST1700_DEV_SPI0,
> > @@ -26,6 +27,7 @@ enum {
> > ASPEED_AST1700_DEV_ADC,
> > ASPEED_AST1700_DEV_SCU,
> > ASPEED_AST1700_DEV_GPIO,
> > + ASPEED_AST1700_DEV_SGPIOM,
> > ASPEED_AST1700_DEV_I2C,
> > ASPEED_AST1700_DEV_I3C,
> > ASPEED_AST1700_DEV_UART12,
> > @@ -40,6 +42,7 @@ static const hwaddr aspeed_ast1700_io_memmap[] =
> {
> > [ASPEED_AST1700_DEV_ADC] = 0x00C00000,
> > [ASPEED_AST1700_DEV_SCU] = 0x00C02000,
> > [ASPEED_AST1700_DEV_GPIO] = 0x00C0B000,
> > + [ASPEED_AST1700_DEV_SGPIOM] = 0x00C0C000,
> > [ASPEED_AST1700_DEV_I2C] = 0x00C0F000,
> > [ASPEED_AST1700_DEV_I3C] = 0x00C20000,
> > [ASPEED_AST1700_DEV_UART12] = 0x00C33B00,
> > @@ -162,6 +165,15 @@ static void aspeed_ast1700_realize(DeviceState
> *dev, Error **errp)
> >
> aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_LTPI_CTRL],
> >
> > sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->ltpi), 0));
> >
> > + /* SGPIOM */
> > + qdev_prop_set_string(DEVICE(&s->sgpiom), "name", "ioexp-sgpiom");
> > + qdev_prop_set_uint64(DEVICE(&s->sgpiom), "size",
> AST1700_SOC_SGPIOM_SIZE);
> > + sysbus_realize(SYS_BUS_DEVICE(&s->sgpiom), errp);
> > + memory_region_add_subregion_overlap(&s->iomem,
> > +
> aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_SGPIOM],
> > +
> sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->sgpiom), 0),
> > + -1000);
> > +
> > /* WDT */
> > for (i = 0; i < AST1700_WDT_NUM; i++) {
> > AspeedWDTClass *awc =
> ASPEED_WDT_GET_CLASS(&s->wdt[i]); @@
> > -225,6 +237,10 @@ static void aspeed_ast1700_instance_init(Object *obj)
> > object_initialize_child(obj, "ltpi-ctrl",
> > &s->ltpi, TYPE_ASPEED_LTPI);
> >
> > + /* SGPIOM */
> > + object_initialize_child(obj, "ioexp-sgpiom[*]", &s->sgpiom,
> > + TYPE_UNIMPLEMENTED_DEVICE);
> > +
> > /* WDT */
> > for (i = 0; i < AST1700_WDT_NUM; i++) {
> > snprintf(typename, sizeof(typename), "aspeed.wdt-%s",
> > socname);
^ permalink raw reply [flat|nested] 46+ messages in thread* Re: [PATCH v2 16/17] hw/arm/aspeed: Model AST1700 SGPIOM block as unimplemented device
2025-11-11 1:33 ` Kane Chen
@ 2025-11-12 7:06 ` Cédric Le Goater
0 siblings, 0 replies; 46+ messages in thread
From: Cédric Le Goater @ 2025-11-12 7:06 UTC (permalink / raw)
To: Kane Chen, Peter Maydell, Steven Lee, Troy Lee, Jamin Lin,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here, Yubin Zou
Cc: Troy Lee
Hello,
On 11/11/25 02:33, Kane Chen wrote:
> Hi Cédric,
>
> Thanks for the information. I'll investigate this model and integrate it.
Help with reviewing is welcome !
Thanks,
C.
>
> Best Regards,
> Kane
>> -----Original Message-----
>> From: Cédric Le Goater <clg@kaod.org>
>> Sent: Tuesday, November 11, 2025 12:15 AM
>> To: Kane Chen <kane_chen@aspeedtech.com>; Peter Maydell
>> <peter.maydell@linaro.org>; Steven Lee <steven_lee@aspeedtech.com>; Troy
>> Lee <leetroy@gmail.com>; Jamin Lin <jamin_lin@aspeedtech.com>; Andrew
>> Jeffery <andrew@codeconstruct.com.au>; Joel Stanley <joel@jms.id.au>;
>> open list:ASPEED BMCs <qemu-arm@nongnu.org>; open list:All patches CC
>> here <qemu-devel@nongnu.org>; Yubin Zou <yubinz@google.com>
>> Cc: Troy Lee <troy_lee@aspeedtech.com>
>> Subject: Re: [PATCH v2 16/17] hw/arm/aspeed: Model AST1700 SGPIOM block
>> as unimplemented device
>>
>> Hello,
>>
>> On 11/5/25 04:58, Kane Chen wrote:
>>> From: Kane-Chen-AS <kane_chen@aspeedtech.com>
>>>
>>> AST1700 includes an SGPIOM block, but QEMU has no functional model yet.
>>
>> Does the series "hw/gpio: Add Aspeed Serial GPIO (SGPIO) controller" [1]
>> proposed by Yubin Zou fill this gap ?
>>
>> Thanks,
>>
>> C.
>>
>> [1]
>> https://lore.kernel.org//qemu-devel/20251106-aspeed-sgpio-v1-0-b0260937
>> 16fa@google.com
>>
>>
>>> Expose it as an unimplemented device so the address space is reserved
>>> and the missing functionality is explicit to users/guests.
>>>
>>> Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
>>> ---
>>> include/hw/misc/aspeed_ast1700.h | 1 +
>>> hw/misc/aspeed_ast1700.c | 16 ++++++++++++++++
>>> 2 files changed, 17 insertions(+)
>>>
>>> diff --git a/include/hw/misc/aspeed_ast1700.h
>>> b/include/hw/misc/aspeed_ast1700.h
>>> index 4048d31154..8ada3a7775 100644
>>> --- a/include/hw/misc/aspeed_ast1700.h
>>> +++ b/include/hw/misc/aspeed_ast1700.h
>>> @@ -44,6 +44,7 @@ struct AspeedAST1700SoCState {
>>> AspeedWDTState wdt[AST1700_WDT_NUM];
>>>
>>> UnimplementedDeviceState i3c;
>>> + UnimplementedDeviceState sgpiom;
>>> };
>>>
>>> #endif /* ASPEED_AST1700_H */
>>> diff --git a/hw/misc/aspeed_ast1700.c b/hw/misc/aspeed_ast1700.c index
>>> 37b2946fc0..66a5f21d27 100644
>>> --- a/hw/misc/aspeed_ast1700.c
>>> +++ b/hw/misc/aspeed_ast1700.c
>>> @@ -19,6 +19,7 @@
>>> #define AST2700_SOC_LTPI_SIZE 0x01000000
>>> #define AST1700_SOC_SRAM_SIZE 0x00040000
>>> #define AST1700_SOC_I3C_SIZE 0x00010000
>>> +#define AST1700_SOC_SGPIOM_SIZE 0x00002000
>>>
>>> enum {
>>> ASPEED_AST1700_DEV_SPI0,
>>> @@ -26,6 +27,7 @@ enum {
>>> ASPEED_AST1700_DEV_ADC,
>>> ASPEED_AST1700_DEV_SCU,
>>> ASPEED_AST1700_DEV_GPIO,
>>> + ASPEED_AST1700_DEV_SGPIOM,
>>> ASPEED_AST1700_DEV_I2C,
>>> ASPEED_AST1700_DEV_I3C,
>>> ASPEED_AST1700_DEV_UART12,
>>> @@ -40,6 +42,7 @@ static const hwaddr aspeed_ast1700_io_memmap[] =
>> {
>>> [ASPEED_AST1700_DEV_ADC] = 0x00C00000,
>>> [ASPEED_AST1700_DEV_SCU] = 0x00C02000,
>>> [ASPEED_AST1700_DEV_GPIO] = 0x00C0B000,
>>> + [ASPEED_AST1700_DEV_SGPIOM] = 0x00C0C000,
>>> [ASPEED_AST1700_DEV_I2C] = 0x00C0F000,
>>> [ASPEED_AST1700_DEV_I3C] = 0x00C20000,
>>> [ASPEED_AST1700_DEV_UART12] = 0x00C33B00,
>>> @@ -162,6 +165,15 @@ static void aspeed_ast1700_realize(DeviceState
>> *dev, Error **errp)
>>>
>> aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_LTPI_CTRL],
>>>
>>> sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->ltpi), 0));
>>>
>>> + /* SGPIOM */
>>> + qdev_prop_set_string(DEVICE(&s->sgpiom), "name", "ioexp-sgpiom");
>>> + qdev_prop_set_uint64(DEVICE(&s->sgpiom), "size",
>> AST1700_SOC_SGPIOM_SIZE);
>>> + sysbus_realize(SYS_BUS_DEVICE(&s->sgpiom), errp);
>>> + memory_region_add_subregion_overlap(&s->iomem,
>>> +
>> aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_SGPIOM],
>>> +
>> sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->sgpiom), 0),
>>> + -1000);
>>> +
>>> /* WDT */
>>> for (i = 0; i < AST1700_WDT_NUM; i++) {
>>> AspeedWDTClass *awc =
>> ASPEED_WDT_GET_CLASS(&s->wdt[i]); @@
>>> -225,6 +237,10 @@ static void aspeed_ast1700_instance_init(Object *obj)
>>> object_initialize_child(obj, "ltpi-ctrl",
>>> &s->ltpi, TYPE_ASPEED_LTPI);
>>>
>>> + /* SGPIOM */
>>> + object_initialize_child(obj, "ioexp-sgpiom[*]", &s->sgpiom,
>>> + TYPE_UNIMPLEMENTED_DEVICE);
>>> +
>>> /* WDT */
>>> for (i = 0; i < AST1700_WDT_NUM; i++) {
>>> snprintf(typename, sizeof(typename), "aspeed.wdt-%s",
>>> socname);
>
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH v2 17/17] hw/arm/aspeed: Model AST1700 PWM block as unimplemented device
2025-11-05 3:58 [PATCH v2 00/17] hw/arm/aspeed: AST1700 LTPI support and device hookups Kane Chen via
` (15 preceding siblings ...)
2025-11-05 3:58 ` [PATCH v2 16/17] hw/arm/aspeed: Model AST1700 SGPIOM " Kane Chen via
@ 2025-11-05 3:58 ` Kane Chen via
2025-11-10 16:16 ` Cédric Le Goater
2025-11-05 10:27 ` [PATCH v2 00/17] hw/arm/aspeed: AST1700 LTPI support and device hookups Cédric Le Goater
2025-11-10 16:43 ` Cédric Le Goater
18 siblings, 1 reply; 46+ messages in thread
From: Kane Chen via @ 2025-11-05 3:58 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, Kane-Chen-AS
From: Kane-Chen-AS <kane_chen@aspeedtech.com>
AST1700 includes an PWM block, but QEMU has no functional model for
aspeed product yet. Expose it as an unimplemented device so the
address space is reserved and the missing functionality is explicit
to users/guests.
Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
---
include/hw/misc/aspeed_ast1700.h | 1 +
hw/misc/aspeed_ast1700.c | 16 ++++++++++++++++
2 files changed, 17 insertions(+)
diff --git a/include/hw/misc/aspeed_ast1700.h b/include/hw/misc/aspeed_ast1700.h
index 8ada3a7775..9d432a7db0 100644
--- a/include/hw/misc/aspeed_ast1700.h
+++ b/include/hw/misc/aspeed_ast1700.h
@@ -45,6 +45,7 @@ struct AspeedAST1700SoCState {
UnimplementedDeviceState i3c;
UnimplementedDeviceState sgpiom;
+ UnimplementedDeviceState pwm;
};
#endif /* ASPEED_AST1700_H */
diff --git a/hw/misc/aspeed_ast1700.c b/hw/misc/aspeed_ast1700.c
index 66a5f21d27..3d9a920a7a 100644
--- a/hw/misc/aspeed_ast1700.c
+++ b/hw/misc/aspeed_ast1700.c
@@ -20,9 +20,11 @@
#define AST1700_SOC_SRAM_SIZE 0x00040000
#define AST1700_SOC_I3C_SIZE 0x00010000
#define AST1700_SOC_SGPIOM_SIZE 0x00002000
+#define AST1700_SOC_PWM_SIZE 0x00000200
enum {
ASPEED_AST1700_DEV_SPI0,
+ ASPEED_AST1700_DEV_PWM,
ASPEED_AST1700_DEV_SRAM,
ASPEED_AST1700_DEV_ADC,
ASPEED_AST1700_DEV_SCU,
@@ -38,6 +40,7 @@ enum {
static const hwaddr aspeed_ast1700_io_memmap[] = {
[ASPEED_AST1700_DEV_SPI0] = 0x00030000,
+ [ASPEED_AST1700_DEV_PWM] = 0x000C0000,
[ASPEED_AST1700_DEV_SRAM] = 0x00BC0000,
[ASPEED_AST1700_DEV_ADC] = 0x00C00000,
[ASPEED_AST1700_DEV_SCU] = 0x00C02000,
@@ -174,6 +177,15 @@ static void aspeed_ast1700_realize(DeviceState *dev, Error **errp)
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->sgpiom), 0),
-1000);
+ /* PWM */
+ qdev_prop_set_string(DEVICE(&s->pwm), "name", "ioexp-pwm");
+ qdev_prop_set_uint64(DEVICE(&s->pwm), "size", AST1700_SOC_PWM_SIZE);
+ sysbus_realize(SYS_BUS_DEVICE(&s->pwm), errp);
+ memory_region_add_subregion_overlap(&s->iomem,
+ aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_PWM],
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->pwm), 0),
+ -1000);
+
/* WDT */
for (i = 0; i < AST1700_WDT_NUM; i++) {
AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
@@ -241,6 +253,10 @@ static void aspeed_ast1700_instance_init(Object *obj)
object_initialize_child(obj, "ioexp-sgpiom[*]", &s->sgpiom,
TYPE_UNIMPLEMENTED_DEVICE);
+ /* PWM */
+ object_initialize_child(obj, "ioexp-pwm", &s->pwm,
+ TYPE_UNIMPLEMENTED_DEVICE);
+
/* WDT */
for (i = 0; i < AST1700_WDT_NUM; i++) {
snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname);
--
2.43.0
^ permalink raw reply related [flat|nested] 46+ messages in thread* Re: [PATCH v2 17/17] hw/arm/aspeed: Model AST1700 PWM block as unimplemented device
2025-11-05 3:58 ` [PATCH v2 17/17] hw/arm/aspeed: Model AST1700 PWM " Kane Chen via
@ 2025-11-10 16:16 ` Cédric Le Goater
2025-11-11 1:27 ` Kane Chen
0 siblings, 1 reply; 46+ messages in thread
From: Cédric Le Goater @ 2025-11-10 16:16 UTC (permalink / raw)
To: Kane Chen, Peter Maydell, Steven Lee, Troy Lee, Jamin Lin,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee
On 11/5/25 04:58, Kane Chen wrote:
> From: Kane-Chen-AS <kane_chen@aspeedtech.com>
>
> AST1700 includes an PWM block, but QEMU has no functional model for
> aspeed product yet.
We could start with a dummy PWM model :
https://github.com/legoater/qemu/commit/9d77c84b04c2d9ae5685b3ccb5c434873666ca78
Feel free to add to your series.
Thanks,
C.
Expose it as an unimplemented device so the
> address space is reserved and the missing functionality is explicit
> to users/guests.
>
> Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
> ---
> include/hw/misc/aspeed_ast1700.h | 1 +
> hw/misc/aspeed_ast1700.c | 16 ++++++++++++++++
> 2 files changed, 17 insertions(+)
>
> diff --git a/include/hw/misc/aspeed_ast1700.h b/include/hw/misc/aspeed_ast1700.h
> index 8ada3a7775..9d432a7db0 100644
> --- a/include/hw/misc/aspeed_ast1700.h
> +++ b/include/hw/misc/aspeed_ast1700.h
> @@ -45,6 +45,7 @@ struct AspeedAST1700SoCState {
>
> UnimplementedDeviceState i3c;
> UnimplementedDeviceState sgpiom;
> + UnimplementedDeviceState pwm;
> };
>
> #endif /* ASPEED_AST1700_H */
> diff --git a/hw/misc/aspeed_ast1700.c b/hw/misc/aspeed_ast1700.c
> index 66a5f21d27..3d9a920a7a 100644
> --- a/hw/misc/aspeed_ast1700.c
> +++ b/hw/misc/aspeed_ast1700.c
> @@ -20,9 +20,11 @@
> #define AST1700_SOC_SRAM_SIZE 0x00040000
> #define AST1700_SOC_I3C_SIZE 0x00010000
> #define AST1700_SOC_SGPIOM_SIZE 0x00002000
> +#define AST1700_SOC_PWM_SIZE 0x00000200
>
> enum {
> ASPEED_AST1700_DEV_SPI0,
> + ASPEED_AST1700_DEV_PWM,
> ASPEED_AST1700_DEV_SRAM,
> ASPEED_AST1700_DEV_ADC,
> ASPEED_AST1700_DEV_SCU,
> @@ -38,6 +40,7 @@ enum {
>
> static const hwaddr aspeed_ast1700_io_memmap[] = {
> [ASPEED_AST1700_DEV_SPI0] = 0x00030000,
> + [ASPEED_AST1700_DEV_PWM] = 0x000C0000,
> [ASPEED_AST1700_DEV_SRAM] = 0x00BC0000,
> [ASPEED_AST1700_DEV_ADC] = 0x00C00000,
> [ASPEED_AST1700_DEV_SCU] = 0x00C02000,
> @@ -174,6 +177,15 @@ static void aspeed_ast1700_realize(DeviceState *dev, Error **errp)
> sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->sgpiom), 0),
> -1000);
>
> + /* PWM */
> + qdev_prop_set_string(DEVICE(&s->pwm), "name", "ioexp-pwm");
> + qdev_prop_set_uint64(DEVICE(&s->pwm), "size", AST1700_SOC_PWM_SIZE);
> + sysbus_realize(SYS_BUS_DEVICE(&s->pwm), errp);
> + memory_region_add_subregion_overlap(&s->iomem,
> + aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_PWM],
> + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->pwm), 0),
> + -1000);
> +
> /* WDT */
> for (i = 0; i < AST1700_WDT_NUM; i++) {
> AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
> @@ -241,6 +253,10 @@ static void aspeed_ast1700_instance_init(Object *obj)
> object_initialize_child(obj, "ioexp-sgpiom[*]", &s->sgpiom,
> TYPE_UNIMPLEMENTED_DEVICE);
>
> + /* PWM */
> + object_initialize_child(obj, "ioexp-pwm", &s->pwm,
> + TYPE_UNIMPLEMENTED_DEVICE);
> +
> /* WDT */
> for (i = 0; i < AST1700_WDT_NUM; i++) {
> snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname);
^ permalink raw reply [flat|nested] 46+ messages in thread* RE: [PATCH v2 17/17] hw/arm/aspeed: Model AST1700 PWM block as unimplemented device
2025-11-10 16:16 ` Cédric Le Goater
@ 2025-11-11 1:27 ` Kane Chen
0 siblings, 0 replies; 46+ messages in thread
From: Kane Chen @ 2025-11-11 1:27 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee
Hi Cédric,
Thanks for the information. I'll try integrating this PWM model.
Best Regards,
Kane
> -----Original Message-----
> From: Cédric Le Goater <clg@kaod.org>
> Sent: Tuesday, November 11, 2025 12:17 AM
> To: Kane Chen <kane_chen@aspeedtech.com>; Peter Maydell
> <peter.maydell@linaro.org>; Steven Lee <steven_lee@aspeedtech.com>; Troy
> Lee <leetroy@gmail.com>; Jamin Lin <jamin_lin@aspeedtech.com>; Andrew
> Jeffery <andrew@codeconstruct.com.au>; Joel Stanley <joel@jms.id.au>;
> open list:ASPEED BMCs <qemu-arm@nongnu.org>; open list:All patches CC
> here <qemu-devel@nongnu.org>
> Cc: Troy Lee <troy_lee@aspeedtech.com>
> Subject: Re: [PATCH v2 17/17] hw/arm/aspeed: Model AST1700 PWM block as
> unimplemented device
>
> On 11/5/25 04:58, Kane Chen wrote:
> > From: Kane-Chen-AS <kane_chen@aspeedtech.com>
> >
> > AST1700 includes an PWM block, but QEMU has no functional model for
> > aspeed product yet.
>
> We could start with a dummy PWM model :
>
>
> https://github.com/legoater/qemu/commit/9d77c84b04c2d9ae5685b3ccb5c4
> 34873666ca78
>
> Feel free to add to your series.
>
> Thanks,
>
> C.
>
>
>
> Expose it as an unimplemented device so the
> > address space is reserved and the missing functionality is explicit to
> > users/guests.
> >
> > Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
> > ---
> > include/hw/misc/aspeed_ast1700.h | 1 +
> > hw/misc/aspeed_ast1700.c | 16 ++++++++++++++++
> > 2 files changed, 17 insertions(+)
> >
> > diff --git a/include/hw/misc/aspeed_ast1700.h
> > b/include/hw/misc/aspeed_ast1700.h
> > index 8ada3a7775..9d432a7db0 100644
> > --- a/include/hw/misc/aspeed_ast1700.h
> > +++ b/include/hw/misc/aspeed_ast1700.h
> > @@ -45,6 +45,7 @@ struct AspeedAST1700SoCState {
> >
> > UnimplementedDeviceState i3c;
> > UnimplementedDeviceState sgpiom;
> > + UnimplementedDeviceState pwm;
> > };
> >
> > #endif /* ASPEED_AST1700_H */
> > diff --git a/hw/misc/aspeed_ast1700.c b/hw/misc/aspeed_ast1700.c index
> > 66a5f21d27..3d9a920a7a 100644
> > --- a/hw/misc/aspeed_ast1700.c
> > +++ b/hw/misc/aspeed_ast1700.c
> > @@ -20,9 +20,11 @@
> > #define AST1700_SOC_SRAM_SIZE 0x00040000
> > #define AST1700_SOC_I3C_SIZE 0x00010000
> > #define AST1700_SOC_SGPIOM_SIZE 0x00002000
> > +#define AST1700_SOC_PWM_SIZE 0x00000200
> >
> > enum {
> > ASPEED_AST1700_DEV_SPI0,
> > + ASPEED_AST1700_DEV_PWM,
> > ASPEED_AST1700_DEV_SRAM,
> > ASPEED_AST1700_DEV_ADC,
> > ASPEED_AST1700_DEV_SCU,
> > @@ -38,6 +40,7 @@ enum {
> >
> > static const hwaddr aspeed_ast1700_io_memmap[] = {
> > [ASPEED_AST1700_DEV_SPI0] = 0x00030000,
> > + [ASPEED_AST1700_DEV_PWM] = 0x000C0000,
> > [ASPEED_AST1700_DEV_SRAM] = 0x00BC0000,
> > [ASPEED_AST1700_DEV_ADC] = 0x00C00000,
> > [ASPEED_AST1700_DEV_SCU] = 0x00C02000,
> > @@ -174,6 +177,15 @@ static void aspeed_ast1700_realize(DeviceState
> *dev, Error **errp)
> >
> sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->sgpiom), 0),
> > -1000);
> >
> > + /* PWM */
> > + qdev_prop_set_string(DEVICE(&s->pwm), "name", "ioexp-pwm");
> > + qdev_prop_set_uint64(DEVICE(&s->pwm), "size",
> AST1700_SOC_PWM_SIZE);
> > + sysbus_realize(SYS_BUS_DEVICE(&s->pwm), errp);
> > + memory_region_add_subregion_overlap(&s->iomem,
> > +
> aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_PWM],
> > +
> sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->pwm), 0),
> > + -1000);
> > +
> > /* WDT */
> > for (i = 0; i < AST1700_WDT_NUM; i++) {
> > AspeedWDTClass *awc =
> ASPEED_WDT_GET_CLASS(&s->wdt[i]); @@
> > -241,6 +253,10 @@ static void aspeed_ast1700_instance_init(Object *obj)
> > object_initialize_child(obj, "ioexp-sgpiom[*]", &s->sgpiom,
> > TYPE_UNIMPLEMENTED_DEVICE);
> >
> > + /* PWM */
> > + object_initialize_child(obj, "ioexp-pwm", &s->pwm,
> > + TYPE_UNIMPLEMENTED_DEVICE);
> > +
> > /* WDT */
> > for (i = 0; i < AST1700_WDT_NUM; i++) {
> > snprintf(typename, sizeof(typename), "aspeed.wdt-%s",
> > socname);
^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PATCH v2 00/17] hw/arm/aspeed: AST1700 LTPI support and device hookups
2025-11-05 3:58 [PATCH v2 00/17] hw/arm/aspeed: AST1700 LTPI support and device hookups Kane Chen via
` (16 preceding siblings ...)
2025-11-05 3:58 ` [PATCH v2 17/17] hw/arm/aspeed: Model AST1700 PWM " Kane Chen via
@ 2025-11-05 10:27 ` Cédric Le Goater
2025-11-05 10:34 ` Kane Chen
2025-11-10 16:43 ` Cédric Le Goater
18 siblings, 1 reply; 46+ messages in thread
From: Cédric Le Goater @ 2025-11-05 10:27 UTC (permalink / raw)
To: Kane Chen, Peter Maydell, Steven Lee, Troy Lee, Jamin Lin,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee
On 11/5/25 04:58, Kane Chen wrote:
> From: Kane-Chen-AS <kane_chen@aspeedtech.com>
>
> Hi all,
>
> LTPI (LVDS Tunneling Protocol & Interface) is defined in the OCP DC-SCM
> 2.0 specification (see Figure 2):
> https://www.opencompute.org/documents/ocp-dc-scm-2-0-ltpi-ver-1-0-pdf
>
> LTPI provides a protocol and physical interface for tunneling various
> low-speed signals between the Host Processor Module (HPM) and the
> Satellite Controller Module (SCM). In Figure 2 of the specification,
> the AST27x0 SoC (left) integrates two LTPI controllers, allowing it to
> connect to up to two AST1700 boards. On the other side, the AST1700
> consolidates HPM FPGA functions and multiple peripheral interfaces
> (GPIO, UART, I2C, I3C, etc.) onto a single board.
>
> Because the AST1700 exposes additional I/O interfaces (GPIO, I2C, I3C,
> and others), it acts as an I/O expander. Once connected over LTPI,
> the AST27x0 can control additional downstream devices through this link.
>
> This patch series introduces a basic LTPI controller model and wires it
> into the AST27x0 SoC. It also adds the AST1700-specific LTPI expander
> device and gradually connects common peripherals on the AST1700 model.
> For blocks that are not yet functionally implemented (I3C, SGPIOM, PWM),
> their MMIO regions are modeled as unimplemented devices to reserve
> address space and make the missing functionality explicit, ensuring that
> guest probing remains stable.
>
> In the official release images, the AST1700 functions are not included
> by default. To test the AST1700-related functionality, please include
> the following DTS files for probing:
> https://github.com/AspeedTech-BMC/linux/blob/aspeed-master-v6.6/arch/arm64/boot/dts/aspeed/aspeed-ltpi0.dtsi
> https://github.com/AspeedTech-BMC/linux/blob/aspeed-master-v6.6/arch/arm64/boot/dts/aspeed/aspeed-ltpi1.dtsi
>
> After including these DTS files in the BMC image, you can verify LTPI
> functionality using the following scenarios:
>
> 1. In U-Boot:
> Run the ltpi command to trigger the LTPI connection and display the
> current connection status.
> 2. In BMC Linux:
> Run i2cdetect -y <16-38> to scan and test the I2C buses exposed by
> the AST1700.
>
> Any feedback or suggestions are appreciated!
>
Thanks for the update. The models look better. Let's consider them
for QEMU 11.0.
Did you run "make check" and "make check-functional" ?
Thanks,
C.
^ permalink raw reply [flat|nested] 46+ messages in thread* RE: [PATCH v2 00/17] hw/arm/aspeed: AST1700 LTPI support and device hookups
2025-11-05 10:27 ` [PATCH v2 00/17] hw/arm/aspeed: AST1700 LTPI support and device hookups Cédric Le Goater
@ 2025-11-05 10:34 ` Kane Chen
0 siblings, 0 replies; 46+ messages in thread
From: Kane Chen @ 2025-11-05 10:34 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee
Hi Cédric,
I haven't run the "make check" or "make check-functional" tests yet, but I did verify that QEMU could boot the official image properly after applying each patch.
I'll run the tests soon, and if I find anything, I'll let you know.
Best Regards,
Kane
> -----Original Message-----
> From: Cédric Le Goater <clg@redhat.com>
> Sent: Wednesday, November 5, 2025 6:27 PM
> To: Kane Chen <kane_chen@aspeedtech.com>; Peter Maydell
> <peter.maydell@linaro.org>; Steven Lee <steven_lee@aspeedtech.com>; Troy
> Lee <leetroy@gmail.com>; Jamin Lin <jamin_lin@aspeedtech.com>; Andrew
> Jeffery <andrew@codeconstruct.com.au>; Joel Stanley <joel@jms.id.au>;
> open list:ASPEED BMCs <qemu-arm@nongnu.org>; open list:All patches CC
> here <qemu-devel@nongnu.org>
> Cc: Troy Lee <troy_lee@aspeedtech.com>
> Subject: Re: [PATCH v2 00/17] hw/arm/aspeed: AST1700 LTPI support and
> device hookups
>
> On 11/5/25 04:58, Kane Chen wrote:
> > From: Kane-Chen-AS <kane_chen@aspeedtech.com>
> >
> > Hi all,
> >
> > LTPI (LVDS Tunneling Protocol & Interface) is defined in the OCP
> > DC-SCM
> > 2.0 specification (see Figure 2):
> > https://www.opencompute.org/documents/ocp-dc-scm-2-0-ltpi-ver-1-0-pdf
> >
> > LTPI provides a protocol and physical interface for tunneling various
> > low-speed signals between the Host Processor Module (HPM) and the
> > Satellite Controller Module (SCM). In Figure 2 of the specification,
> > the AST27x0 SoC (left) integrates two LTPI controllers, allowing it to
> > connect to up to two AST1700 boards. On the other side, the AST1700
> > consolidates HPM FPGA functions and multiple peripheral interfaces
> > (GPIO, UART, I2C, I3C, etc.) onto a single board.
> >
> > Because the AST1700 exposes additional I/O interfaces (GPIO, I2C, I3C,
> > and others), it acts as an I/O expander. Once connected over LTPI, the
> > AST27x0 can control additional downstream devices through this link.
> >
> > This patch series introduces a basic LTPI controller model and wires
> > it into the AST27x0 SoC. It also adds the AST1700-specific LTPI
> > expander device and gradually connects common peripherals on the
> AST1700 model.
> > For blocks that are not yet functionally implemented (I3C, SGPIOM,
> > PWM), their MMIO regions are modeled as unimplemented devices to
> > reserve address space and make the missing functionality explicit,
> > ensuring that guest probing remains stable.
> >
> > In the official release images, the AST1700 functions are not included
> > by default. To test the AST1700-related functionality, please include
> > the following DTS files for probing:
> >
> https://github.com/AspeedTech-BMC/linux/blob/aspeed-master-v6.6/arch/a
> > rm64/boot/dts/aspeed/aspeed-ltpi0.dtsi
> >
> https://github.com/AspeedTech-BMC/linux/blob/aspeed-master-v6.6/arch/a
> > rm64/boot/dts/aspeed/aspeed-ltpi1.dtsi
> >
> > After including these DTS files in the BMC image, you can verify LTPI
> > functionality using the following scenarios:
> >
> > 1. In U-Boot:
> > Run the ltpi command to trigger the LTPI connection and display the
> > current connection status.
> > 2. In BMC Linux:
> > Run i2cdetect -y <16-38> to scan and test the I2C buses exposed by
> > the AST1700.
> >
> > Any feedback or suggestions are appreciated!
> >
>
> Thanks for the update. The models look better. Let's consider them for QEMU
> 11.0.
>
>
> Did you run "make check" and "make check-functional" ?
>
> Thanks,
>
> C.
^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PATCH v2 00/17] hw/arm/aspeed: AST1700 LTPI support and device hookups
2025-11-05 3:58 [PATCH v2 00/17] hw/arm/aspeed: AST1700 LTPI support and device hookups Kane Chen via
` (17 preceding siblings ...)
2025-11-05 10:27 ` [PATCH v2 00/17] hw/arm/aspeed: AST1700 LTPI support and device hookups Cédric Le Goater
@ 2025-11-10 16:43 ` Cédric Le Goater
2025-11-11 2:32 ` Kane Chen
18 siblings, 1 reply; 46+ messages in thread
From: Cédric Le Goater @ 2025-11-10 16:43 UTC (permalink / raw)
To: Kane Chen, Peter Maydell, Steven Lee, Troy Lee, Jamin Lin,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee
On 11/5/25 04:58, Kane Chen wrote:
> From: Kane-Chen-AS <kane_chen@aspeedtech.com>
>
> Hi all,
>
> LTPI (LVDS Tunneling Protocol & Interface) is defined in the OCP DC-SCM
> 2.0 specification (see Figure 2):
> https://www.opencompute.org/documents/ocp-dc-scm-2-0-ltpi-ver-1-0-pdf
>
> LTPI provides a protocol and physical interface for tunneling various
> low-speed signals between the Host Processor Module (HPM) and the
> Satellite Controller Module (SCM). In Figure 2 of the specification,
> the AST27x0 SoC (left) integrates two LTPI controllers, allowing it to
> connect to up to two AST1700 boards. On the other side, the AST1700
> consolidates HPM FPGA functions and multiple peripheral interfaces
> (GPIO, UART, I2C, I3C, etc.) onto a single board.
>
> Because the AST1700 exposes additional I/O interfaces (GPIO, I2C, I3C,
> and others), it acts as an I/O expander. Once connected over LTPI,
> the AST27x0 can control additional downstream devices through this link.
>
> This patch series introduces a basic LTPI controller model and wires it
> into the AST27x0 SoC. It also adds the AST1700-specific LTPI expander
> device and gradually connects common peripherals on the AST1700 model.
> For blocks that are not yet functionally implemented (I3C, SGPIOM, PWM),
> their MMIO regions are modeled as unimplemented devices to reserve
> address space and make the missing functionality explicit, ensuring that
> guest probing remains stable.
Thanks for the improved cover letter.
> In the official release images, the AST1700 functions are not included
> by default. To test the AST1700-related functionality, please include
> the following DTS files for probing:
> https://github.com/AspeedTech-BMC/linux/blob/aspeed-master-v6.6/arch/arm64/boot/dts/aspeed/aspeed-ltpi0.dtsi
> https://github.com/AspeedTech-BMC/linux/blob/aspeed-master-v6.6/arch/arm64/boot/dts/aspeed/aspeed-ltpi1.dtsi
Is a release planned ?
> After including these DTS files in the BMC image, you can verify LTPI
> functionality using the following scenarios:
>
> 1. In U-Boot:
> Run the ltpi command to trigger the LTPI connection and display the
> current connection status.
> 2. In BMC Linux:
> Run i2cdetect -y <16-38> to scan and test the I2C buses exposed by
> the AST1700.
because this would be good to have for functional tests.
>
> Any feedback or suggestions are appreciated!
The AST1700 model is rather big and very similar to a SoC, without CPUs.
Perhaps we should move the model under hw/arm instead ?
Thanks,
C.
>
> Kane
> ---
>
> ChangeLog
> ---------
> v2:
> - Separate the AST1700 model into a standalone implementation
> - Refine the mechanism for assigning the AST1700 board number
>
> v1:
> - Initial version
> ---
>
> Kane-Chen-AS (17):
> hw/arm/aspeed: Add LTPI controller
> hw/arm/aspeed: Attach LTPI controller to AST27X0 platform
> hw/arm/aspeed: Add AST1700 LTPI expander device model
> hw/arm/aspeed: Integrate AST1700 device into AST27X0
> hw/arm/aspeed: Integrate interrupt controller for AST1700
> hw/arm/aspeed: Attach LTPI controller to AST1700 model
> hw/arm/aspeed: Attach UART device to AST1700 model
> hw/arm/aspeed: Attach SRAM device to AST1700 model
> hw/arm/aspeed: Attach SPI device to AST1700 model
> hw/arm/aspeed: Attach ADC device to AST1700 model
> hw/arm/aspeed: Attach SCU device to AST1700 model
> hw/arm/aspeed: Attach GPIO device to AST1700 model
> hw/arm/aspeed: Attach I2C device to AST1700 model
> hw/arm/aspeed: Attach WDT device to AST1700 model
> hw/arm/aspeed: Model AST1700 I3C block as unimplemented device
> hw/arm/aspeed: Model AST1700 SGPIOM block as unimplemented device
> hw/arm/aspeed: Model AST1700 PWM block as unimplemented device
>
> include/hw/arm/aspeed_soc.h | 20 +-
> include/hw/intc/aspeed_intc.h | 2 +
> include/hw/misc/aspeed_ast1700.h | 51 ++++++
> include/hw/misc/aspeed_ltpi.h | 25 +++
> hw/arm/aspeed_ast27x0.c | 154 ++++++++++++++--
> hw/intc/aspeed_intc.c | 60 ++++++
> hw/misc/aspeed_ast1700.c | 303 +++++++++++++++++++++++++++++++
> hw/misc/aspeed_ltpi.c | 98 ++++++++++
> hw/misc/meson.build | 2 +
> 9 files changed, 700 insertions(+), 15 deletions(-)
> create mode 100644 include/hw/misc/aspeed_ast1700.h
> create mode 100644 include/hw/misc/aspeed_ltpi.h
> create mode 100644 hw/misc/aspeed_ast1700.c
> create mode 100644 hw/misc/aspeed_ltpi.c
>
^ permalink raw reply [flat|nested] 46+ messages in thread* RE: [PATCH v2 00/17] hw/arm/aspeed: AST1700 LTPI support and device hookups
2025-11-10 16:43 ` Cédric Le Goater
@ 2025-11-11 2:32 ` Kane Chen
0 siblings, 0 replies; 46+ messages in thread
From: Kane Chen @ 2025-11-11 2:32 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee
Hi Cédric,
In the short term, there's no plan to release an image that includes the AST1700.
Once such an image becomes available, I'll submit a patch series for functional
testing.
I'll also try moving the AST1700 code to the hw/arm directory. If I encounter any
Issues during this process, I'll let you know.
Best regards,
Kane
> -----Original Message-----
> From: Cédric Le Goater <clg@kaod.org>
> Sent: Tuesday, November 11, 2025 12:44 AM
> To: Kane Chen <kane_chen@aspeedtech.com>; Peter Maydell
> <peter.maydell@linaro.org>; Steven Lee <steven_lee@aspeedtech.com>; Troy
> Lee <leetroy@gmail.com>; Jamin Lin <jamin_lin@aspeedtech.com>; Andrew
> Jeffery <andrew@codeconstruct.com.au>; Joel Stanley <joel@jms.id.au>;
> open list:ASPEED BMCs <qemu-arm@nongnu.org>; open list:All patches CC
> here <qemu-devel@nongnu.org>
> Cc: Troy Lee <troy_lee@aspeedtech.com>
> Subject: Re: [PATCH v2 00/17] hw/arm/aspeed: AST1700 LTPI support and
> device hookups
>
> On 11/5/25 04:58, Kane Chen wrote:
> > From: Kane-Chen-AS <kane_chen@aspeedtech.com>
> >
> > Hi all,
> >
> > LTPI (LVDS Tunneling Protocol & Interface) is defined in the OCP
> > DC-SCM
> > 2.0 specification (see Figure 2):
> > https://www.opencompute.org/documents/ocp-dc-scm-2-0-ltpi-ver-1-0-pdf
> >
> > LTPI provides a protocol and physical interface for tunneling various
> > low-speed signals between the Host Processor Module (HPM) and the
> > Satellite Controller Module (SCM). In Figure 2 of the specification,
> > the AST27x0 SoC (left) integrates two LTPI controllers, allowing it to
> > connect to up to two AST1700 boards. On the other side, the AST1700
> > consolidates HPM FPGA functions and multiple peripheral interfaces
> > (GPIO, UART, I2C, I3C, etc.) onto a single board.
> >
> > Because the AST1700 exposes additional I/O interfaces (GPIO, I2C, I3C,
> > and others), it acts as an I/O expander. Once connected over LTPI, the
> > AST27x0 can control additional downstream devices through this link.
> >
> > This patch series introduces a basic LTPI controller model and wires
> > it into the AST27x0 SoC. It also adds the AST1700-specific LTPI
> > expander device and gradually connects common peripherals on the
> AST1700 model.
> > For blocks that are not yet functionally implemented (I3C, SGPIOM,
> > PWM), their MMIO regions are modeled as unimplemented devices to
> > reserve address space and make the missing functionality explicit,
> > ensuring that guest probing remains stable.
>
> Thanks for the improved cover letter.
>
> > In the official release images, the AST1700 functions are not included
> > by default. To test the AST1700-related functionality, please include
> > the following DTS files for probing:
> >
> https://github.com/AspeedTech-BMC/linux/blob/aspeed-master-v6.6/arch/a
> > rm64/boot/dts/aspeed/aspeed-ltpi0.dtsi
> >
> https://github.com/AspeedTech-BMC/linux/blob/aspeed-master-v6.6/arch/a
> > rm64/boot/dts/aspeed/aspeed-ltpi1.dtsi
>
> Is a release planned ?
>
> > After including these DTS files in the BMC image, you can verify LTPI
> > functionality using the following scenarios:
> >
> > 1. In U-Boot:
> > Run the ltpi command to trigger the LTPI connection and display the
> > current connection status.
> > 2. In BMC Linux:
> > Run i2cdetect -y <16-38> to scan and test the I2C buses exposed by
> > the AST1700.
>
> because this would be good to have for functional tests.
>
> >
> > Any feedback or suggestions are appreciated!
>
> The AST1700 model is rather big and very similar to a SoC, without CPUs.
> Perhaps we should move the model under hw/arm instead ?
>
>
> Thanks,
>
> C.
>
>
> >
> > Kane
> > ---
> >
> > ChangeLog
> > ---------
> > v2:
> > - Separate the AST1700 model into a standalone implementation
> > - Refine the mechanism for assigning the AST1700 board number
> >
> > v1:
> > - Initial version
> > ---
> >
> > Kane-Chen-AS (17):
> > hw/arm/aspeed: Add LTPI controller
> > hw/arm/aspeed: Attach LTPI controller to AST27X0 platform
> > hw/arm/aspeed: Add AST1700 LTPI expander device model
> > hw/arm/aspeed: Integrate AST1700 device into AST27X0
> > hw/arm/aspeed: Integrate interrupt controller for AST1700
> > hw/arm/aspeed: Attach LTPI controller to AST1700 model
> > hw/arm/aspeed: Attach UART device to AST1700 model
> > hw/arm/aspeed: Attach SRAM device to AST1700 model
> > hw/arm/aspeed: Attach SPI device to AST1700 model
> > hw/arm/aspeed: Attach ADC device to AST1700 model
> > hw/arm/aspeed: Attach SCU device to AST1700 model
> > hw/arm/aspeed: Attach GPIO device to AST1700 model
> > hw/arm/aspeed: Attach I2C device to AST1700 model
> > hw/arm/aspeed: Attach WDT device to AST1700 model
> > hw/arm/aspeed: Model AST1700 I3C block as unimplemented device
> > hw/arm/aspeed: Model AST1700 SGPIOM block as unimplemented
> device
> > hw/arm/aspeed: Model AST1700 PWM block as unimplemented device
> >
> > include/hw/arm/aspeed_soc.h | 20 +-
> > include/hw/intc/aspeed_intc.h | 2 +
> > include/hw/misc/aspeed_ast1700.h | 51 ++++++
> > include/hw/misc/aspeed_ltpi.h | 25 +++
> > hw/arm/aspeed_ast27x0.c | 154 ++++++++++++++--
> > hw/intc/aspeed_intc.c | 60 ++++++
> > hw/misc/aspeed_ast1700.c | 303
> +++++++++++++++++++++++++++++++
> > hw/misc/aspeed_ltpi.c | 98 ++++++++++
> > hw/misc/meson.build | 2 +
> > 9 files changed, 700 insertions(+), 15 deletions(-)
> > create mode 100644 include/hw/misc/aspeed_ast1700.h
> > create mode 100644 include/hw/misc/aspeed_ltpi.h
> > create mode 100644 hw/misc/aspeed_ast1700.c
> > create mode 100644 hw/misc/aspeed_ltpi.c
> >
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