From: "Cédric Le Goater" <clg@kaod.org>
To: Nicholas Piggin <npiggin@gmail.com>, qemu-ppc@nongnu.org
Cc: "Frédéric Barrat" <fbarrat@linux.ibm.com>,
"Harsh Prateek Bora" <harshpb@linux.ibm.com>,
qemu-devel@nongnu.org
Subject: Re: [PATCH 10/18] ppc: Add has_smt_siblings property to CPUPPCState
Date: Thu, 11 Jul 2024 18:34:18 +0200 [thread overview]
Message-ID: <e13f36ed-bac5-40cf-b0cc-65934c664d26@kaod.org> (raw)
In-Reply-To: <20240711141851.406677-11-npiggin@gmail.com>
On 7/11/24 16:18, Nicholas Piggin wrote:
> The decision to branch out to a slower SMT path in instruction
> emulation will become a bit more complicated with the way that
> "big-core" topology that will be implemented in subsequent changes.
> Hide these details from the wider CPU emulation code with a bool
> has_smt_siblings flag that can be set by machine initialisation.
>
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
The distinction between what's done in pnv_core_realize() and
pnv_core_cpu_realize() is not clear. Not this patch fault though.
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Thanks,
C.
> ---
> target/ppc/cpu.h | 3 ++-
> hw/ppc/pnv_core.c | 3 +++
> hw/ppc/spapr_cpu_core.c | 15 +++++++++++----
> 3 files changed, 16 insertions(+), 5 deletions(-)
>
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index a74b753c99..35a1cb65cb 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -1248,6 +1248,7 @@ struct CPUArchState {
> int access_type;
>
> /* For SMT processors */
> + bool has_smt_siblings;
> int core_index;
>
> #if !defined(CONFIG_USER_ONLY)
> @@ -1516,7 +1517,7 @@ struct PowerPCCPUClass {
>
> static inline bool ppc_cpu_core_single_threaded(CPUState *cs)
> {
> - return cs->nr_threads == 1;
> + return !POWERPC_CPU(cs)->env.has_smt_siblings;
> }
>
> static inline bool ppc_cpu_lpar_single_threaded(CPUState *cs)
> diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
> index 7bda29b9c7..8cfa94fbfa 100644
> --- a/hw/ppc/pnv_core.c
> +++ b/hw/ppc/pnv_core.c
> @@ -288,6 +288,9 @@ static void pnv_core_realize(DeviceState *dev, Error **errp)
> cpu = POWERPC_CPU(obj);
>
> pc->threads[i] = POWERPC_CPU(obj);
> + if (cc->nr_threads > 1) {
> + cpu->env.has_smt_siblings = true;
> + }
>
> snprintf(name, sizeof(name), "thread[%d]", i);
> object_property_add_child(OBJECT(pc), name, obj);
> diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c
> index d9116c8409..2c6eeb41a4 100644
> --- a/hw/ppc/spapr_cpu_core.c
> +++ b/hw/ppc/spapr_cpu_core.c
> @@ -314,12 +314,13 @@ static PowerPCCPU *spapr_create_vcpu(SpaprCpuCore *sc, int i, Error **errp)
> * and the rest are explicitly started up by the guest using an RTAS call.
> */
> qdev_prop_set_bit(DEVICE(obj), "start-powered-off", true);
> - env->core_index = cc->core_id;
> cs->cpu_index = cc->core_id + i;
> if (!spapr_set_vcpu_id(cpu, cs->cpu_index, errp)) {
> return NULL;
> }
>
> + env->core_index = cc->core_id;
> +
> cpu->node_id = sc->node_id;
>
> id = g_strdup_printf("thread[%d]", i);
> @@ -350,9 +351,15 @@ static void spapr_cpu_core_realize(DeviceState *dev, Error **errp)
> qemu_register_reset(spapr_cpu_core_reset_handler, sc);
> sc->threads = g_new0(PowerPCCPU *, cc->nr_threads);
> for (i = 0; i < cc->nr_threads; i++) {
> - sc->threads[i] = spapr_create_vcpu(sc, i, errp);
> - if (!sc->threads[i] ||
> - !spapr_realize_vcpu(sc->threads[i], spapr, sc, i, errp)) {
> + PowerPCCPU *cpu;
> +
> + cpu = spapr_create_vcpu(sc, i, errp);
> + sc->threads[i] = cpu;
> + if (cpu && cc->nr_threads > 1) {
> + cpu->env.has_smt_siblings = true;
> + }
> +
> + if (!cpu || !spapr_realize_vcpu(cpu, spapr, sc, i, errp)) {
> spapr_cpu_core_unrealize(dev);
> return;
> }
next prev parent reply other threads:[~2024-07-11 16:35 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-11 14:18 [PATCH 00/18] ppc/pnv: Better big-core model, lpar-per-core, PC unit Nicholas Piggin
2024-07-11 14:18 ` [PATCH 01/18] target/ppc: Fix msgsnd for POWER8 Nicholas Piggin
2024-07-11 15:38 ` Cédric Le Goater
2024-07-11 14:18 ` [PATCH 02/18] ppc/pnv: Add pointer from PnvCPUState to PnvCore Nicholas Piggin
2024-07-11 14:18 ` [PATCH 03/18] ppc/pnv: Add a pointer from PnvChip to PnvMachineState Nicholas Piggin
2024-07-11 16:09 ` Cédric Le Goater
2024-07-11 14:18 ` [PATCH 04/18] ppc/pnv: Move timebase state into PnvCore Nicholas Piggin
2024-07-11 14:18 ` [PATCH 05/18] target/ppc: Move SPR indirect registers " Nicholas Piggin
2024-07-11 14:18 ` [PATCH 06/18] ppc/pnv: specialise init for powernv8/9/10 machines Nicholas Piggin
2024-07-11 16:21 ` Cédric Le Goater
2024-07-11 14:18 ` [PATCH 07/18] ppc/pnv: Extend chip_pir class method to TIR as well Nicholas Piggin
2024-07-11 16:22 ` Cédric Le Goater
2024-07-11 14:18 ` [PATCH 08/18] ppc: Add a core_index to CPUPPCState for SMT vCPUs Nicholas Piggin
2024-07-11 16:24 ` Cédric Le Goater
2024-07-11 14:18 ` [PATCH 09/18] target/ppc: Add helpers to check for SMT sibling threads Nicholas Piggin
2024-07-11 14:18 ` [PATCH 10/18] ppc: Add has_smt_siblings property to CPUPPCState Nicholas Piggin
2024-07-11 16:34 ` Cédric Le Goater [this message]
2024-07-11 14:18 ` [PATCH 11/18] ppc/pnv: Add a big-core mode that joins two regular cores Nicholas Piggin
2024-07-11 16:36 ` Cédric Le Goater
2024-07-11 14:18 ` [PATCH 12/18] ppc/pnv: Add allow for big-core differences in DT generation Nicholas Piggin
2024-07-11 14:18 ` [PATCH 13/18] ppc/pnv: Implement big-core PVR for Power9/10 Nicholas Piggin
2024-07-11 14:18 ` [PATCH 14/18] ppc/pnv: Implement Power9 CPU core thread state indirect register Nicholas Piggin
2024-07-11 14:18 ` [PATCH 15/18] ppc/pnv: Add POWER10 ChipTOD quirk for big-core Nicholas Piggin
2024-07-11 14:18 ` [PATCH 16/18] ppc/pnv: Add big-core machine property Nicholas Piggin
2024-07-11 14:18 ` [PATCH 17/18] ppc/pnv: Implement POWER10 PC xscom registers for direct controls Nicholas Piggin
2024-07-11 16:43 ` Cédric Le Goater
2024-07-11 14:18 ` [PATCH 18/18] ppc/pnv: Add an LPAR per core machine option Nicholas Piggin
2024-07-11 17:00 ` Cédric Le Goater
2024-07-11 17:20 ` [PATCH 00/18] ppc/pnv: Better big-core model, lpar-per-core, PC unit Cédric Le Goater
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