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[176.184.23.7]) by smtp.gmail.com with ESMTPSA id l14-20020a7bc44e000000b00411d1ce4f9dsm14151504wmi.34.2024.02.20.03.54.11 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 20 Feb 2024 03:54:11 -0800 (PST) Message-ID: Date: Tue, 20 Feb 2024 12:54:09 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] target/riscv: Add missing include guard in pmu.h Content-Language: en-US To: frank.chang@sifive.com, qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei References: <20240220110907.10479-1-frank.chang@sifive.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20240220110907.10479-1-frank.chang@sifive.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::233; envelope-from=philmd@linaro.org; helo=mail-lj1-x233.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 20/2/24 12:08, frank.chang@sifive.com wrote: > From: Frank Chang > > Add missing include guard in pmu.h to avoid the problem of double > inclusion. > In case it needs to be backported to stable releases: Fixes: 3780e33732 ("target/riscv: Support mcycle/minstret write operation") Reviewed-by: Philippe Mathieu-Daudé > Signed-off-by: Frank Chang > --- > target/riscv/pmu.h | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/target/riscv/pmu.h b/target/riscv/pmu.h > index 505fc850d3..7c0ad661e0 100644 > --- a/target/riscv/pmu.h > +++ b/target/riscv/pmu.h > @@ -16,6 +16,9 @@ > * this program. If not, see . > */ > > +#ifndef RISCV_PMU_H > +#define RISCV_PMU_H > + > #include "cpu.h" > #include "qapi/error.h" > > @@ -31,3 +34,5 @@ int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_event_idx event_idx); > void riscv_pmu_generate_fdt_node(void *fdt, uint32_t cmask, char *pmu_name); > int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value, > uint32_t ctr_idx); > + > +#endif /* RISCV_PMU_H */