From: Richard Henderson <richard.henderson@linaro.org>
To: Max Chou <max.chou@sifive.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: dbarboza@ventanamicro.com,
Nazar Kazakov <nazar.kazakov@codethink.co.uk>,
Lawrence Hunter <lawrence.hunter@codethink.co.uk>,
William Salmon <will.salmon@codethink.co.uk>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bin.meng@windriver.com>,
Weiwei Li <liweiwei@iscas.ac.cn>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,
Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
Subject: Re: [PATCH v6 09/15] target/riscv: Add Zvkned ISA extension support
Date: Thu, 29 Jun 2023 18:25:14 +0200 [thread overview]
Message-ID: <e163fb6a-56d1-082f-5330-3c88cb949d25@linaro.org> (raw)
In-Reply-To: <c7860d59-2166-292b-4689-0d25ff7b7469@sifive.com>
On 6/29/23 17:10, Max Chou wrote:
> On 2023/6/28 5:07 PM, Richard Henderson wrote:
>> You can eliminate the vstart % EGS test, and the vstart < vl test, when VSTART_EQ_ZERO.
>> You can eliminate the vl % EGS test when VL_EQ_VLMAX.
>>
>> You could move all of these tests out of line, into a helper_foo_chk() function which
>> performs the checks and then calls helper_foo().
> Hi Richard
>
> Thank you for the suggestion.
> I'll provide the v7 patch set with this suggestion.
>
> But I have an question about the vstart < vl test.
> I think that we can't eliminate the vstart < vl test when both the vstart and vl are equal
> to zero.
> Although this situation means that the instructions will do nothing.
We know vlmax != 0 (there's some architectural minimum).
Therefore if VL_EQ_VLMAX, vl != 0 and if VSTART_EQ_ZERO, then vstart < vl.
r~
next prev parent reply other threads:[~2023-06-29 16:26 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-27 17:45 [PATCH v5 00/15] Add RISC-V vector cryptographic instruction set support Max Chou
2023-06-27 17:45 ` [PATCH v6 01/15] target/riscv: Refactor some of the generic vector functionality Max Chou
2023-06-27 17:45 ` [PATCH v6 02/15] target/riscv: Refactor vector-vector translation macro Max Chou
2023-06-27 17:45 ` [PATCH v6 03/15] target/riscv: Remove redundant "cpu_vl == 0" checks Max Chou
2023-06-27 17:45 ` [PATCH v6 04/15] target/riscv: Add Zvbc ISA extension support Max Chou
2023-06-27 17:45 ` [PATCH v6 05/15] target/riscv: Move vector translation checks Max Chou
2023-06-27 17:45 ` [PATCH v6 06/15] target/riscv: Refactor translation of vector-widening instruction Max Chou
2023-06-27 17:45 ` [PATCH v6 07/15] target/riscv: Refactor some of the generic vector functionality Max Chou
2023-06-27 17:45 ` [PATCH v6 08/15] target/riscv: Add Zvbb ISA extension support Max Chou
2023-06-27 17:45 ` [PATCH v6 09/15] target/riscv: Add Zvkned " Max Chou
2023-06-28 9:07 ` Richard Henderson
2023-06-29 15:10 ` Max Chou
2023-06-29 16:25 ` Richard Henderson [this message]
2023-06-27 17:45 ` [PATCH v6 10/15] target/riscv: Add Zvknh " Max Chou
2023-06-28 9:14 ` Richard Henderson
2023-06-29 11:06 ` Max Chou
2023-06-27 17:45 ` [PATCH v6 11/15] target/riscv: Add Zvksh " Max Chou
2023-06-27 17:45 ` [PATCH v6 12/15] target/riscv: Add Zvkg " Max Chou
2023-06-27 17:45 ` [PATCH v6 13/15] crypto: Create sm4_subword Max Chou
2023-06-27 17:45 ` [PATCH v6 14/15] crypto: Add SM4 constant parameter CK Max Chou
2023-06-27 17:45 ` [PATCH v6 15/15] target/riscv: Add Zvksed ISA extension support Max Chou
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