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Thu, 02 Oct 2025 12:08:58 -0700 (PDT) Received: from [192.168.1.87] ([38.41.223.211]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-339a6e9d2d4sm5819029a91.2.2025.10.02.12.08.57 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 02 Oct 2025 12:08:58 -0700 (PDT) Message-ID: Date: Thu, 2 Oct 2025 12:08:57 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 05/33] target/riscv: Combine mhpmevent and mhpmeventh Content-Language: en-US To: Anton Johansson , qemu-devel@nongnu.org Cc: philmd@linaro.org, richard.henderson@linaro.org, alistair.francis@wdc.com, palmer@dabbelt.com References: <20251001073306.28573-1-anjo@rev.ng> <20251001073306.28573-6-anjo@rev.ng> From: Pierrick Bouvier In-Reply-To: <20251001073306.28573-6-anjo@rev.ng> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=pierrick.bouvier@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 10/1/25 12:32 AM, Anton Johansson wrote: > According to version 20250508 of the privileged specification, > mhpmeventn is 64 bits in size and mhpmeventnh is only ever used > when XLEN == 32 and accesses the top 32 bits of the 64-bit > mhpmeventn registers. Combine the two arrays of target_ulong > mhpmeventh[] and mhpmevent[] to a single array of uint64_t. > > This also allows for some minor code simplification where branches > handling either mhpmeventh[] or mhpmevent[] could be combined. > > Signed-off-by: Anton Johansson > --- > target/riscv/cpu.h | 10 +++---- > target/riscv/csr.c | 67 +++++++++++++++--------------------------- > target/riscv/machine.c | 3 +- > target/riscv/pmu.c | 53 ++++++++------------------------- > 4 files changed, 42 insertions(+), 91 deletions(-) > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 3235108112..64b9964028 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -427,11 +427,11 @@ struct CPUArchState { > /* PMU counter state */ > PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS]; > > - /* PMU event selector configured values. First three are unused */ > - target_ulong mhpmevent_val[RV_MAX_MHPMEVENTS]; > - > - /* PMU event selector configured values for RV32 */ > - target_ulong mhpmeventh_val[RV_MAX_MHPMEVENTS]; > + /* > + * PMU event selector configured values. First three are unused. > + * For RV32 top 32 bits are accessed via the mhpmeventh CSR. > + */ > + uint64_t mhpmevent_val[RV_MAX_MHPMEVENTS]; > > PMUFixedCtrState pmu_fixed_ctrs[2]; > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index 859f89aedd..2d8916ee40 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -1166,8 +1166,9 @@ static RISCVException read_mhpmevent(CPURISCVState *env, int csrno, > target_ulong *val) > { > int evt_index = csrno - CSR_MCOUNTINHIBIT; > + bool rv32 = riscv_cpu_mxl(env) == MXL_RV32; > > - *val = env->mhpmevent_val[evt_index]; > + *val = extract64(env->mhpmevent_val[evt_index], 0, rv32 ? 32 : 64); > > return RISCV_EXCP_NONE; > } > @@ -1176,13 +1177,11 @@ static RISCVException write_mhpmevent(CPURISCVState *env, int csrno, > target_ulong val, uintptr_t ra) > { > int evt_index = csrno - CSR_MCOUNTINHIBIT; > - uint64_t mhpmevt_val = val; > + uint64_t mhpmevt_val; > uint64_t inh_avail_mask; > > if (riscv_cpu_mxl(env) == MXL_RV32) { > - env->mhpmevent_val[evt_index] = val; > - mhpmevt_val = mhpmevt_val | > - ((uint64_t)env->mhpmeventh_val[evt_index] << 32); > + mhpmevt_val = deposit64(env->mhpmevent_val[evt_index], 0, 32, val); Maybe I missed something, but should it be: deposit64(env->mhpmevent_val[evt_index], 32, 32, val) instead? Reading the rest of the patch, I'm a bit confused about which bits are supposed to be used in 32/64 mode.