* [PATCH 01/29] accel/tcg: Add restore_state_to_opc to TCGCPUOps
2022-10-24 13:24 [PATCH 00/29] tcg: Fix x86 TARGET_TB_PCREL (#1269) Richard Henderson
@ 2022-10-24 13:24 ` Richard Henderson
2022-10-24 15:05 ` Claudio Fontana
2022-10-24 13:24 ` [PATCH] tests/tcg/nios2: Tweak 10m50-ghrd.ld Richard Henderson
` (28 subsequent siblings)
29 siblings, 1 reply; 64+ messages in thread
From: Richard Henderson @ 2022-10-24 13:24 UTC (permalink / raw)
To: qemu-devel
Add a tcg_ops hook to replace the restore_state_to_opc
function call. Because these generic hooks cannot depend
on target-specific types, temporarily, copy the current
target_ulong data[] into uint64_t d64[].
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/exec-all.h | 2 +-
include/hw/core/tcg-cpu-ops.h | 11 +++++++++++
accel/tcg/translate-all.c | 24 ++++++++++++++++++++++--
3 files changed, 34 insertions(+), 3 deletions(-)
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index e5f8b224a5..a772e8cbdc 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -40,7 +40,7 @@ typedef ram_addr_t tb_page_addr_t;
#endif
void restore_state_to_opc(CPUArchState *env, TranslationBlock *tb,
- target_ulong *data);
+ target_ulong *data) __attribute__((weak));
/**
* cpu_restore_state:
diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
index 78c6c6635d..20e3c0ffbb 100644
--- a/include/hw/core/tcg-cpu-ops.h
+++ b/include/hw/core/tcg-cpu-ops.h
@@ -31,6 +31,17 @@ struct TCGCPUOps {
* function to restore all the state, and register it here.
*/
void (*synchronize_from_tb)(CPUState *cpu, const TranslationBlock *tb);
+ /**
+ * @restore_state_to_opc: Synchronize state from INDEX_op_start_insn
+ *
+ * This is called when we unwind state in the middle of a TB,
+ * usually before raising an exception. Set all part of the CPU
+ * state which are tracked insn-by-insn in the target-specific
+ * arguments to start_insn, passed as @data.
+ */
+ void (*restore_state_to_opc)(CPUState *cpu, const TranslationBlock *tb,
+ const uint64_t *data);
+
/** @cpu_exec_enter: Callback for cpu_exec preparation */
void (*cpu_exec_enter)(CPUState *cpu);
/** @cpu_exec_exit: Callback for cpu_exec cleanup */
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index 4ed75a13e1..19cd23e9a0 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -329,7 +329,6 @@ static int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb,
{
target_ulong data[TARGET_INSN_START_WORDS];
uintptr_t host_pc = (uintptr_t)tb->tc.ptr;
- CPUArchState *env = cpu->env_ptr;
const uint8_t *p = tb->tc.ptr + tb->tc.size;
int i, j, num_insns = tb->icount;
#ifdef CONFIG_PROFILER
@@ -368,7 +367,20 @@ static int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb,
and shift if to the number of actually executed instructions */
cpu_neg(cpu)->icount_decr.u16.low += num_insns - i;
}
- restore_state_to_opc(env, tb, data);
+
+ {
+ const struct TCGCPUOps *ops = cpu->cc->tcg_ops;
+ __typeof(ops->restore_state_to_opc) restore = ops->restore_state_to_opc;
+ if (restore) {
+ uint64_t d64[TARGET_INSN_START_WORDS];
+ for (i = 0; i < TARGET_INSN_START_WORDS; ++i) {
+ d64[i] = data[i];
+ }
+ restore(cpu, tb, d64);
+ } else {
+ restore_state_to_opc(cpu->env_ptr, tb, data);
+ }
+ }
#ifdef CONFIG_PROFILER
qatomic_set(&prof->restore_time,
@@ -380,6 +392,14 @@ static int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb,
bool cpu_restore_state(CPUState *cpu, uintptr_t host_pc, bool will_exit)
{
+ /*
+ * The pc update associated with restore without exit will
+ * break the relative pc adjustments performed by TARGET_TB_PCREL.
+ */
+ if (TARGET_TB_PCREL) {
+ assert(will_exit);
+ }
+
/*
* The host_pc has to be in the rx region of the code buffer.
* If it is not we will not be able to resolve it here.
--
2.34.1
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH 01/29] accel/tcg: Add restore_state_to_opc to TCGCPUOps
2022-10-24 13:24 ` [PATCH 01/29] accel/tcg: Add restore_state_to_opc to TCGCPUOps Richard Henderson
@ 2022-10-24 15:05 ` Claudio Fontana
2022-10-24 15:15 ` Richard Henderson
0 siblings, 1 reply; 64+ messages in thread
From: Claudio Fontana @ 2022-10-24 15:05 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
On 10/24/22 15:24, Richard Henderson wrote:
> Add a tcg_ops hook to replace the restore_state_to_opc
> function call. Because these generic hooks cannot depend
> on target-specific types, temporarily, copy the current
> target_ulong data[] into uint64_t d64[].
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> include/exec/exec-all.h | 2 +-
> include/hw/core/tcg-cpu-ops.h | 11 +++++++++++
> accel/tcg/translate-all.c | 24 ++++++++++++++++++++++--
> 3 files changed, 34 insertions(+), 3 deletions(-)
>
> diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
> index e5f8b224a5..a772e8cbdc 100644
> --- a/include/exec/exec-all.h
> +++ b/include/exec/exec-all.h
> @@ -40,7 +40,7 @@ typedef ram_addr_t tb_page_addr_t;
> #endif
>
> void restore_state_to_opc(CPUArchState *env, TranslationBlock *tb,
> - target_ulong *data);
> + target_ulong *data) __attribute__((weak));
Hi Richard, doesn't matter much since this is removed later on, but I wonder why the need for attribute weak here?
I don't see you overloading this function in later patches..
Thanks,
Claudio
>
> /**
> * cpu_restore_state:
> diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
> index 78c6c6635d..20e3c0ffbb 100644
> --- a/include/hw/core/tcg-cpu-ops.h
> +++ b/include/hw/core/tcg-cpu-ops.h
> @@ -31,6 +31,17 @@ struct TCGCPUOps {
> * function to restore all the state, and register it here.
> */
> void (*synchronize_from_tb)(CPUState *cpu, const TranslationBlock *tb);
> + /**
> + * @restore_state_to_opc: Synchronize state from INDEX_op_start_insn
> + *
> + * This is called when we unwind state in the middle of a TB,
> + * usually before raising an exception. Set all part of the CPU
> + * state which are tracked insn-by-insn in the target-specific
> + * arguments to start_insn, passed as @data.
> + */
> + void (*restore_state_to_opc)(CPUState *cpu, const TranslationBlock *tb,
> + const uint64_t *data);
> +
> /** @cpu_exec_enter: Callback for cpu_exec preparation */
> void (*cpu_exec_enter)(CPUState *cpu);
> /** @cpu_exec_exit: Callback for cpu_exec cleanup */
> diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
> index 4ed75a13e1..19cd23e9a0 100644
> --- a/accel/tcg/translate-all.c
> +++ b/accel/tcg/translate-all.c
> @@ -329,7 +329,6 @@ static int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb,
> {
> target_ulong data[TARGET_INSN_START_WORDS];
> uintptr_t host_pc = (uintptr_t)tb->tc.ptr;
> - CPUArchState *env = cpu->env_ptr;
> const uint8_t *p = tb->tc.ptr + tb->tc.size;
> int i, j, num_insns = tb->icount;
> #ifdef CONFIG_PROFILER
> @@ -368,7 +367,20 @@ static int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb,
> and shift if to the number of actually executed instructions */
> cpu_neg(cpu)->icount_decr.u16.low += num_insns - i;
> }
> - restore_state_to_opc(env, tb, data);
> +
> + {
> + const struct TCGCPUOps *ops = cpu->cc->tcg_ops;
> + __typeof(ops->restore_state_to_opc) restore = ops->restore_state_to_opc;
> + if (restore) {
> + uint64_t d64[TARGET_INSN_START_WORDS];
> + for (i = 0; i < TARGET_INSN_START_WORDS; ++i) {
> + d64[i] = data[i];
> + }
> + restore(cpu, tb, d64);
> + } else {
> + restore_state_to_opc(cpu->env_ptr, tb, data);
> + }
> + }
>
> #ifdef CONFIG_PROFILER
> qatomic_set(&prof->restore_time,
> @@ -380,6 +392,14 @@ static int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb,
>
> bool cpu_restore_state(CPUState *cpu, uintptr_t host_pc, bool will_exit)
> {
> + /*
> + * The pc update associated with restore without exit will
> + * break the relative pc adjustments performed by TARGET_TB_PCREL.
> + */
> + if (TARGET_TB_PCREL) {
> + assert(will_exit);
> + }
> +
> /*
> * The host_pc has to be in the rx region of the code buffer.
> * If it is not we will not be able to resolve it here.
^ permalink raw reply [flat|nested] 64+ messages in thread* Re: [PATCH 01/29] accel/tcg: Add restore_state_to_opc to TCGCPUOps
2022-10-24 15:05 ` Claudio Fontana
@ 2022-10-24 15:15 ` Richard Henderson
2022-10-25 8:41 ` Claudio Fontana
0 siblings, 1 reply; 64+ messages in thread
From: Richard Henderson @ 2022-10-24 15:15 UTC (permalink / raw)
To: Claudio Fontana, qemu-devel
On 10/25/22 01:05, Claudio Fontana wrote:
> On 10/24/22 15:24, Richard Henderson wrote:
>> Add a tcg_ops hook to replace the restore_state_to_opc
>> function call. Because these generic hooks cannot depend
>> on target-specific types, temporarily, copy the current
>> target_ulong data[] into uint64_t d64[].
>>
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>> include/exec/exec-all.h | 2 +-
>> include/hw/core/tcg-cpu-ops.h | 11 +++++++++++
>> accel/tcg/translate-all.c | 24 ++++++++++++++++++++++--
>> 3 files changed, 34 insertions(+), 3 deletions(-)
>>
>> diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
>> index e5f8b224a5..a772e8cbdc 100644
>> --- a/include/exec/exec-all.h
>> +++ b/include/exec/exec-all.h
>> @@ -40,7 +40,7 @@ typedef ram_addr_t tb_page_addr_t;
>> #endif
>>
>> void restore_state_to_opc(CPUArchState *env, TranslationBlock *tb,
>> - target_ulong *data);
>> + target_ulong *data) __attribute__((weak));
>
> Hi Richard, doesn't matter much since this is removed later on, but I wonder why the need for attribute weak here?
> I don't see you overloading this function in later patches..
So that it can be undefined. Otherwise I can't remove the existing symbol from each target.
r~
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH 01/29] accel/tcg: Add restore_state_to_opc to TCGCPUOps
2022-10-24 15:15 ` Richard Henderson
@ 2022-10-25 8:41 ` Claudio Fontana
0 siblings, 0 replies; 64+ messages in thread
From: Claudio Fontana @ 2022-10-25 8:41 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
On 10/24/22 17:15, Richard Henderson wrote:
> On 10/25/22 01:05, Claudio Fontana wrote:
>> On 10/24/22 15:24, Richard Henderson wrote:
>>> Add a tcg_ops hook to replace the restore_state_to_opc
>>> function call. Because these generic hooks cannot depend
>>> on target-specific types, temporarily, copy the current
>>> target_ulong data[] into uint64_t d64[].
>>>
>>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>>> ---
>>> include/exec/exec-all.h | 2 +-
>>> include/hw/core/tcg-cpu-ops.h | 11 +++++++++++
>>> accel/tcg/translate-all.c | 24 ++++++++++++++++++++++--
>>> 3 files changed, 34 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
>>> index e5f8b224a5..a772e8cbdc 100644
>>> --- a/include/exec/exec-all.h
>>> +++ b/include/exec/exec-all.h
>>> @@ -40,7 +40,7 @@ typedef ram_addr_t tb_page_addr_t;
>>> #endif
>>>
>>> void restore_state_to_opc(CPUArchState *env, TranslationBlock *tb,
>>> - target_ulong *data);
>>> + target_ulong *data) __attribute__((weak));
>>
>> Hi Richard, doesn't matter much since this is removed later on, but I wonder why the need for attribute weak here?
>> I don't see you overloading this function in later patches..
>
> So that it can be undefined. Otherwise I can't remove the existing symbol from each target.
>
>
> r~
>
>
Right - there is still the call to restore_state_to_opc in the else branch in the general code.
I wonder if checking for NULL would make sense in theory, I think that with both GCC and Clang the external declaration with attribute weak would make the function address evaluate to NULL,
so that could be a possible thing to exploit, but no matter.
Reviewed-by: Claudio Fontana <cfontana@suse.de>
^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH] tests/tcg/nios2: Tweak 10m50-ghrd.ld
2022-10-24 13:24 [PATCH 00/29] tcg: Fix x86 TARGET_TB_PCREL (#1269) Richard Henderson
2022-10-24 13:24 ` [PATCH 01/29] accel/tcg: Add restore_state_to_opc to TCGCPUOps Richard Henderson
@ 2022-10-24 13:24 ` Richard Henderson
2022-10-25 9:12 ` Claudio Fontana
2022-10-24 13:24 ` [PATCH 02/29] target/alpha: Convert to tcg_ops restore_state_to_opc Richard Henderson
` (27 subsequent siblings)
29 siblings, 1 reply; 64+ messages in thread
From: Richard Henderson @ 2022-10-24 13:24 UTC (permalink / raw)
To: qemu-devel
More closely follow the default linker script for nios2.
This magically fixes a problem resolving .got relocs from
the toolchain's libgcc.a.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1258
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tests/tcg/nios2/10m50-ghrd.ld | 14 +++++++++-----
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/tests/tcg/nios2/10m50-ghrd.ld b/tests/tcg/nios2/10m50-ghrd.ld
index 7db0d59ad7..71cdda450c 100644
--- a/tests/tcg/nios2/10m50-ghrd.ld
+++ b/tests/tcg/nios2/10m50-ghrd.ld
@@ -44,11 +44,15 @@ SECTIONS
.data : ALIGN(4) {
*(.shdata)
*(.data .data.* .gnu.linkonce.d.*)
- . = ALIGN(4);
- _gp = ABSOLUTE(. + 0x8000);
- *(.got.plt) *(.got)
- *(.lit8)
- *(.lit4)
+ } >ram :RAM
+
+ HIDDEN (_gp = ALIGN(16) + 0x7ff0);
+ PROVIDE_HIDDEN (gp = _gp);
+ .got : ALIGN(4) {
+ *(.got.plt) *(.igot.plt) *(.got) *(.igot)
+ } >ram :RAM
+
+ .sdata : ALIGN(4) {
*(.sdata .sdata.* .gnu.linkonce.s.*)
} >ram :RAM
--
2.34.1
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH] tests/tcg/nios2: Tweak 10m50-ghrd.ld
2022-10-24 13:24 ` [PATCH] tests/tcg/nios2: Tweak 10m50-ghrd.ld Richard Henderson
@ 2022-10-25 9:12 ` Claudio Fontana
0 siblings, 0 replies; 64+ messages in thread
From: Claudio Fontana @ 2022-10-25 9:12 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
This is unrelated to the "tcg: Fix x86 TARGET_TB_PCREL (#1269)" series right?
For some reason it appears to me as part of it, as a reply to the cover letter.
Ignoring this one as I don't understand it at all.
Ciao,
C
On 10/24/22 15:24, Richard Henderson wrote:
> More closely follow the default linker script for nios2.
> This magically fixes a problem resolving .got relocs from
> the toolchain's libgcc.a.
>
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1258
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tests/tcg/nios2/10m50-ghrd.ld | 14 +++++++++-----
> 1 file changed, 9 insertions(+), 5 deletions(-)
>
> diff --git a/tests/tcg/nios2/10m50-ghrd.ld b/tests/tcg/nios2/10m50-ghrd.ld
> index 7db0d59ad7..71cdda450c 100644
> --- a/tests/tcg/nios2/10m50-ghrd.ld
> +++ b/tests/tcg/nios2/10m50-ghrd.ld
> @@ -44,11 +44,15 @@ SECTIONS
> .data : ALIGN(4) {
> *(.shdata)
> *(.data .data.* .gnu.linkonce.d.*)
> - . = ALIGN(4);
> - _gp = ABSOLUTE(. + 0x8000);
> - *(.got.plt) *(.got)
> - *(.lit8)
> - *(.lit4)
> + } >ram :RAM
> +
> + HIDDEN (_gp = ALIGN(16) + 0x7ff0);
> + PROVIDE_HIDDEN (gp = _gp);
> + .got : ALIGN(4) {
> + *(.got.plt) *(.igot.plt) *(.got) *(.igot)
> + } >ram :RAM
> +
> + .sdata : ALIGN(4) {
> *(.sdata .sdata.* .gnu.linkonce.s.*)
> } >ram :RAM
>
^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH 02/29] target/alpha: Convert to tcg_ops restore_state_to_opc
2022-10-24 13:24 [PATCH 00/29] tcg: Fix x86 TARGET_TB_PCREL (#1269) Richard Henderson
2022-10-24 13:24 ` [PATCH 01/29] accel/tcg: Add restore_state_to_opc to TCGCPUOps Richard Henderson
2022-10-24 13:24 ` [PATCH] tests/tcg/nios2: Tweak 10m50-ghrd.ld Richard Henderson
@ 2022-10-24 13:24 ` Richard Henderson
2022-10-24 15:08 ` Philippe Mathieu-Daudé
2022-10-24 13:24 ` [PATCH 03/29] target/arm: " Richard Henderson
` (26 subsequent siblings)
29 siblings, 1 reply; 64+ messages in thread
From: Richard Henderson @ 2022-10-24 13:24 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/alpha/cpu.c | 9 +++++++++
target/alpha/translate.c | 6 ------
2 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index 979a629d59..270ae787b1 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -40,6 +40,14 @@ static vaddr alpha_cpu_get_pc(CPUState *cs)
return cpu->env.pc;
}
+static void alpha_restore_state_to_opc(CPUState *cs,
+ const TranslationBlock *tb,
+ const uint64_t *data)
+{
+ AlphaCPU *cpu = ALPHA_CPU(cs);
+
+ cpu->env.pc = data[0];
+}
static bool alpha_cpu_has_work(CPUState *cs)
{
@@ -226,6 +234,7 @@ static const struct SysemuCPUOps alpha_sysemu_ops = {
static const struct TCGCPUOps alpha_tcg_ops = {
.initialize = alpha_translate_init,
+ .restore_state_to_opc = alpha_restore_state_to_opc,
#ifdef CONFIG_USER_ONLY
.record_sigsegv = alpha_cpu_record_sigsegv,
diff --git a/target/alpha/translate.c b/target/alpha/translate.c
index 6766350f56..f9bcdeb717 100644
--- a/target/alpha/translate.c
+++ b/target/alpha/translate.c
@@ -3049,9 +3049,3 @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns,
DisasContext dc;
translator_loop(cpu, tb, max_insns, pc, host_pc, &alpha_tr_ops, &dc.base);
}
-
-void restore_state_to_opc(CPUAlphaState *env, TranslationBlock *tb,
- target_ulong *data)
-{
- env->pc = data[0];
-}
--
2.34.1
^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 03/29] target/arm: Convert to tcg_ops restore_state_to_opc
2022-10-24 13:24 [PATCH 00/29] tcg: Fix x86 TARGET_TB_PCREL (#1269) Richard Henderson
` (2 preceding siblings ...)
2022-10-24 13:24 ` [PATCH 02/29] target/alpha: Convert to tcg_ops restore_state_to_opc Richard Henderson
@ 2022-10-24 13:24 ` Richard Henderson
2022-10-24 14:27 ` Philippe Mathieu-Daudé
2022-10-24 13:24 ` [PATCH 04/29] target/avr: " Richard Henderson
` (25 subsequent siblings)
29 siblings, 1 reply; 64+ messages in thread
From: Richard Henderson @ 2022-10-24 13:24 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu.c | 26 ++++++++++++++++++++++++++
target/arm/translate.c | 22 ----------------------
2 files changed, 26 insertions(+), 22 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 0bc5e9b125..0a7bfbf999 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -90,6 +90,31 @@ void arm_cpu_synchronize_from_tb(CPUState *cs,
}
}
}
+
+static void arm_restore_state_to_opc(CPUState *cs,
+ const TranslationBlock *tb,
+ const uint64_t *data)
+{
+ CPUARMState *env = cs->env_ptr;
+
+ if (is_a64(env)) {
+ if (TARGET_TB_PCREL) {
+ env->pc = (env->pc & TARGET_PAGE_MASK) | data[0];
+ } else {
+ env->pc = data[0];
+ }
+ env->condexec_bits = 0;
+ env->exception.syndrome = data[2] << ARM_INSN_START_WORD2_SHIFT;
+ } else {
+ if (TARGET_TB_PCREL) {
+ env->regs[15] = (env->regs[15] & TARGET_PAGE_MASK) | data[0];
+ } else {
+ env->regs[15] = data[0];
+ }
+ env->condexec_bits = data[1];
+ env->exception.syndrome = data[2] << ARM_INSN_START_WORD2_SHIFT;
+ }
+}
#endif /* CONFIG_TCG */
static bool arm_cpu_has_work(CPUState *cs)
@@ -2152,6 +2177,7 @@ static const struct TCGCPUOps arm_tcg_ops = {
.initialize = arm_translate_init,
.synchronize_from_tb = arm_cpu_synchronize_from_tb,
.debug_excp_handler = arm_debug_excp_handler,
+ .restore_state_to_opc = arm_restore_state_to_opc,
#ifdef CONFIG_USER_ONLY
.record_sigsegv = arm_cpu_record_sigsegv,
diff --git a/target/arm/translate.c b/target/arm/translate.c
index d1b868430e..74a903072f 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -9939,25 +9939,3 @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns,
translator_loop(cpu, tb, max_insns, pc, host_pc, ops, &dc.base);
}
-
-void restore_state_to_opc(CPUARMState *env, TranslationBlock *tb,
- target_ulong *data)
-{
- if (is_a64(env)) {
- if (TARGET_TB_PCREL) {
- env->pc = (env->pc & TARGET_PAGE_MASK) | data[0];
- } else {
- env->pc = data[0];
- }
- env->condexec_bits = 0;
- env->exception.syndrome = data[2] << ARM_INSN_START_WORD2_SHIFT;
- } else {
- if (TARGET_TB_PCREL) {
- env->regs[15] = (env->regs[15] & TARGET_PAGE_MASK) | data[0];
- } else {
- env->regs[15] = data[0];
- }
- env->condexec_bits = data[1];
- env->exception.syndrome = data[2] << ARM_INSN_START_WORD2_SHIFT;
- }
-}
--
2.34.1
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH 03/29] target/arm: Convert to tcg_ops restore_state_to_opc
2022-10-24 13:24 ` [PATCH 03/29] target/arm: " Richard Henderson
@ 2022-10-24 14:27 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 64+ messages in thread
From: Philippe Mathieu-Daudé @ 2022-10-24 14:27 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
On 24/10/22 15:24, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/cpu.c | 26 ++++++++++++++++++++++++++
> target/arm/translate.c | 22 ----------------------
> 2 files changed, 26 insertions(+), 22 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH 04/29] target/avr: Convert to tcg_ops restore_state_to_opc
2022-10-24 13:24 [PATCH 00/29] tcg: Fix x86 TARGET_TB_PCREL (#1269) Richard Henderson
` (3 preceding siblings ...)
2022-10-24 13:24 ` [PATCH 03/29] target/arm: " Richard Henderson
@ 2022-10-24 13:24 ` Richard Henderson
2022-10-24 14:01 ` Philippe Mathieu-Daudé
2022-10-24 13:24 ` [PATCH 05/29] target/cris: " Richard Henderson
` (24 subsequent siblings)
29 siblings, 1 reply; 64+ messages in thread
From: Richard Henderson @ 2022-10-24 13:24 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/avr/cpu.c | 11 +++++++++++
target/avr/translate.c | 6 ------
2 files changed, 11 insertions(+), 6 deletions(-)
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index 0d2861179d..c7295b488d 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -57,6 +57,16 @@ static void avr_cpu_synchronize_from_tb(CPUState *cs,
env->pc_w = tb_pc(tb) / 2; /* internally PC points to words */
}
+static void avr_restore_state_to_opc(CPUState *cs,
+ const TranslationBlock *tb,
+ const uint64_t *data)
+{
+ AVRCPU *cpu = AVR_CPU(cs);
+ CPUAVRState *env = &cpu->env;
+
+ env->pc_w = data[0];
+}
+
static void avr_cpu_reset(DeviceState *ds)
{
CPUState *cs = CPU(ds);
@@ -202,6 +212,7 @@ static const struct SysemuCPUOps avr_sysemu_ops = {
static const struct TCGCPUOps avr_tcg_ops = {
.initialize = avr_cpu_tcg_init,
.synchronize_from_tb = avr_cpu_synchronize_from_tb,
+ .restore_state_to_opc = avr_restore_state_to_opc,
.cpu_exec_interrupt = avr_cpu_exec_interrupt,
.tlb_fill = avr_cpu_tlb_fill,
.do_interrupt = avr_cpu_do_interrupt,
diff --git a/target/avr/translate.c b/target/avr/translate.c
index e65b6008c0..2bed56f135 100644
--- a/target/avr/translate.c
+++ b/target/avr/translate.c
@@ -3055,9 +3055,3 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns,
DisasContext dc = { };
translator_loop(cs, tb, max_insns, pc, host_pc, &avr_tr_ops, &dc.base);
}
-
-void restore_state_to_opc(CPUAVRState *env, TranslationBlock *tb,
- target_ulong *data)
-{
- env->pc_w = data[0];
-}
--
2.34.1
^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 05/29] target/cris: Convert to tcg_ops restore_state_to_opc
2022-10-24 13:24 [PATCH 00/29] tcg: Fix x86 TARGET_TB_PCREL (#1269) Richard Henderson
` (4 preceding siblings ...)
2022-10-24 13:24 ` [PATCH 04/29] target/avr: " Richard Henderson
@ 2022-10-24 13:24 ` Richard Henderson
2022-10-24 14:58 ` Philippe Mathieu-Daudé
2022-10-24 13:24 ` [PATCH 06/29] target/hexagon: " Richard Henderson
` (23 subsequent siblings)
29 siblings, 1 reply; 64+ messages in thread
From: Richard Henderson @ 2022-10-24 13:24 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/cris/cpu.c | 11 +++++++++++
target/cris/translate.c | 6 ------
2 files changed, 11 insertions(+), 6 deletions(-)
diff --git a/target/cris/cpu.c b/target/cris/cpu.c
index 22f5c70f39..fb05dc6f9a 100644
--- a/target/cris/cpu.c
+++ b/target/cris/cpu.c
@@ -42,6 +42,15 @@ static vaddr cris_cpu_get_pc(CPUState *cs)
return cpu->env.pc;
}
+static void cris_restore_state_to_opc(CPUState *cs,
+ const TranslationBlock *tb,
+ const uint64_t *data)
+{
+ CRISCPU *cpu = CRIS_CPU(cs);
+
+ cpu->env.pc = data[0];
+}
+
static bool cris_cpu_has_work(CPUState *cs)
{
return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
@@ -212,6 +221,7 @@ static const struct SysemuCPUOps cris_sysemu_ops = {
static const struct TCGCPUOps crisv10_tcg_ops = {
.initialize = cris_initialize_crisv10_tcg,
+ .restore_state_to_opc = cris_restore_state_to_opc,
#ifndef CONFIG_USER_ONLY
.tlb_fill = cris_cpu_tlb_fill,
@@ -222,6 +232,7 @@ static const struct TCGCPUOps crisv10_tcg_ops = {
static const struct TCGCPUOps crisv32_tcg_ops = {
.initialize = cris_initialize_tcg,
+ .restore_state_to_opc = cris_restore_state_to_opc,
#ifndef CONFIG_USER_ONLY
.tlb_fill = cris_cpu_tlb_fill,
diff --git a/target/cris/translate.c b/target/cris/translate.c
index 73385b0b3c..fbc3fd5865 100644
--- a/target/cris/translate.c
+++ b/target/cris/translate.c
@@ -3392,9 +3392,3 @@ void cris_initialize_tcg(void)
pregnames_v32[i]);
}
}
-
-void restore_state_to_opc(CPUCRISState *env, TranslationBlock *tb,
- target_ulong *data)
-{
- env->pc = data[0];
-}
--
2.34.1
^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 06/29] target/hexagon: Convert to tcg_ops restore_state_to_opc
2022-10-24 13:24 [PATCH 00/29] tcg: Fix x86 TARGET_TB_PCREL (#1269) Richard Henderson
` (5 preceding siblings ...)
2022-10-24 13:24 ` [PATCH 05/29] target/cris: " Richard Henderson
@ 2022-10-24 13:24 ` Richard Henderson
2022-10-24 14:27 ` Philippe Mathieu-Daudé
2022-10-24 13:24 ` [PATCH 07/29] target/hppa: " Richard Henderson
` (22 subsequent siblings)
29 siblings, 1 reply; 64+ messages in thread
From: Richard Henderson @ 2022-10-24 13:24 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hexagon/cpu.c | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index fa6d722555..03221fbdc2 100644
--- a/target/hexagon/cpu.c
+++ b/target/hexagon/cpu.c
@@ -271,9 +271,13 @@ static bool hexagon_cpu_has_work(CPUState *cs)
return true;
}
-void restore_state_to_opc(CPUHexagonState *env, TranslationBlock *tb,
- target_ulong *data)
+static void hexagon_restore_state_to_opc(CPUState *cs,
+ const TranslationBlock *tb,
+ const uint64_t *data)
{
+ HexagonCPU *cpu = HEXAGON_CPU(cs);
+ CPUHexagonState *env = &cpu->env;
+
env->gpr[HEX_REG_PC] = data[0];
}
@@ -327,6 +331,7 @@ static void hexagon_cpu_init(Object *obj)
static const struct TCGCPUOps hexagon_tcg_ops = {
.initialize = hexagon_translate_init,
.synchronize_from_tb = hexagon_cpu_synchronize_from_tb,
+ .restore_state_to_opc = hexagon_restore_state_to_opc,
};
static void hexagon_cpu_class_init(ObjectClass *c, void *data)
--
2.34.1
^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 07/29] target/hppa: Convert to tcg_ops restore_state_to_opc
2022-10-24 13:24 [PATCH 00/29] tcg: Fix x86 TARGET_TB_PCREL (#1269) Richard Henderson
` (6 preceding siblings ...)
2022-10-24 13:24 ` [PATCH 06/29] target/hexagon: " Richard Henderson
@ 2022-10-24 13:24 ` Richard Henderson
2022-10-24 14:02 ` Philippe Mathieu-Daudé
2022-10-24 13:24 ` [PATCH 08/29] target/i386: " Richard Henderson
` (21 subsequent siblings)
29 siblings, 1 reply; 64+ messages in thread
From: Richard Henderson @ 2022-10-24 13:24 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/cpu.c | 19 +++++++++++++++++++
target/hppa/translate.c | 13 -------------
2 files changed, 19 insertions(+), 13 deletions(-)
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index e677ca09d4..55c190280e 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -68,6 +68,24 @@ static void hppa_cpu_synchronize_from_tb(CPUState *cs,
cpu->env.psw_n = (tb->flags & PSW_N) != 0;
}
+static void hppa_restore_state_to_opc(CPUState *cs,
+ const TranslationBlock *tb,
+ const uint64_t *data)
+{
+ HPPACPU *cpu = HPPA_CPU(cs);
+
+ cpu->env.iaoq_f = data[0];
+ if (data[1] != (target_ureg)-1) {
+ cpu->env.iaoq_b = data[1];
+ }
+ /*
+ * Since we were executing the instruction at IAOQ_F, and took some
+ * sort of action that provoked the cpu_restore_state, we can infer
+ * that the instruction was not nullified.
+ */
+ cpu->env.psw_n = 0;
+}
+
static bool hppa_cpu_has_work(CPUState *cs)
{
return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
@@ -153,6 +171,7 @@ static const struct SysemuCPUOps hppa_sysemu_ops = {
static const struct TCGCPUOps hppa_tcg_ops = {
.initialize = hppa_translate_init,
.synchronize_from_tb = hppa_cpu_synchronize_from_tb,
+ .restore_state_to_opc = hppa_restore_state_to_opc,
#ifndef CONFIG_USER_ONLY
.tlb_fill = hppa_cpu_tlb_fill,
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 8b861957e0..1af77473da 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -4346,16 +4346,3 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns,
DisasContext ctx;
translator_loop(cs, tb, max_insns, pc, host_pc, &hppa_tr_ops, &ctx.base);
}
-
-void restore_state_to_opc(CPUHPPAState *env, TranslationBlock *tb,
- target_ulong *data)
-{
- env->iaoq_f = data[0];
- if (data[1] != (target_ureg)-1) {
- env->iaoq_b = data[1];
- }
- /* Since we were executing the instruction at IAOQ_F, and took some
- sort of action that provoked the cpu_restore_state, we can infer
- that the instruction was not nullified. */
- env->psw_n = 0;
-}
--
2.34.1
^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 08/29] target/i386: Convert to tcg_ops restore_state_to_opc
2022-10-24 13:24 [PATCH 00/29] tcg: Fix x86 TARGET_TB_PCREL (#1269) Richard Henderson
` (7 preceding siblings ...)
2022-10-24 13:24 ` [PATCH 07/29] target/hppa: " Richard Henderson
@ 2022-10-24 13:24 ` Richard Henderson
2022-10-24 14:59 ` Philippe Mathieu-Daudé
2022-10-24 13:24 ` [PATCH 09/29] target/loongarch: " Richard Henderson
` (20 subsequent siblings)
29 siblings, 1 reply; 64+ messages in thread
From: Richard Henderson @ 2022-10-24 13:24 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/i386/tcg/tcg-cpu.c | 19 +++++++++++++++++++
target/i386/tcg/translate.c | 15 ---------------
2 files changed, 19 insertions(+), 15 deletions(-)
diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c
index 828244abe2..79ac5908f7 100644
--- a/target/i386/tcg/tcg-cpu.c
+++ b/target/i386/tcg/tcg-cpu.c
@@ -56,6 +56,24 @@ static void x86_cpu_synchronize_from_tb(CPUState *cs,
}
}
+static void x86_restore_state_to_opc(CPUState *cs,
+ const TranslationBlock *tb,
+ const uint64_t *data)
+{
+ X86CPU *cpu = X86_CPU(cs);
+ CPUX86State *env = &cpu->env;
+ int cc_op = data[1];
+
+ if (TARGET_TB_PCREL) {
+ env->eip = (env->eip & TARGET_PAGE_MASK) | data[0];
+ } else {
+ env->eip = data[0] - tb->cs_base;
+ }
+ if (cc_op != CC_OP_DYNAMIC) {
+ env->cc_op = cc_op;
+ }
+}
+
#ifndef CONFIG_USER_ONLY
static bool x86_debug_check_breakpoint(CPUState *cs)
{
@@ -72,6 +90,7 @@ static bool x86_debug_check_breakpoint(CPUState *cs)
static const struct TCGCPUOps x86_tcg_ops = {
.initialize = tcg_x86_init,
.synchronize_from_tb = x86_cpu_synchronize_from_tb,
+ .restore_state_to_opc = x86_restore_state_to_opc,
.cpu_exec_enter = x86_cpu_exec_enter,
.cpu_exec_exit = x86_cpu_exec_exit,
#ifdef CONFIG_USER_ONLY
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index e19d5c1c64..c8597e2008 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -7022,18 +7022,3 @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns,
translator_loop(cpu, tb, max_insns, pc, host_pc, &i386_tr_ops, &dc.base);
}
-
-void restore_state_to_opc(CPUX86State *env, TranslationBlock *tb,
- target_ulong *data)
-{
- int cc_op = data[1];
-
- if (TARGET_TB_PCREL) {
- env->eip = (env->eip & TARGET_PAGE_MASK) | data[0];
- } else {
- env->eip = data[0] - tb->cs_base;
- }
- if (cc_op != CC_OP_DYNAMIC) {
- env->cc_op = cc_op;
- }
-}
--
2.34.1
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH 08/29] target/i386: Convert to tcg_ops restore_state_to_opc
2022-10-24 13:24 ` [PATCH 08/29] target/i386: " Richard Henderson
@ 2022-10-24 14:59 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 64+ messages in thread
From: Philippe Mathieu-Daudé @ 2022-10-24 14:59 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
On 24/10/22 15:24, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/i386/tcg/tcg-cpu.c | 19 +++++++++++++++++++
> target/i386/tcg/translate.c | 15 ---------------
> 2 files changed, 19 insertions(+), 15 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH 09/29] target/loongarch: Convert to tcg_ops restore_state_to_opc
2022-10-24 13:24 [PATCH 00/29] tcg: Fix x86 TARGET_TB_PCREL (#1269) Richard Henderson
` (8 preceding siblings ...)
2022-10-24 13:24 ` [PATCH 08/29] target/i386: " Richard Henderson
@ 2022-10-24 13:24 ` Richard Henderson
2022-10-24 14:59 ` Philippe Mathieu-Daudé
2022-10-24 13:24 ` [PATCH 10/29] target/m68k: " Richard Henderson
` (19 subsequent siblings)
29 siblings, 1 reply; 64+ messages in thread
From: Richard Henderson @ 2022-10-24 13:24 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/loongarch/cpu.c | 11 +++++++++++
target/loongarch/translate.c | 6 ------
2 files changed, 11 insertions(+), 6 deletions(-)
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index 1722ed2a4d..49393d95d8 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -319,6 +319,16 @@ static void loongarch_cpu_synchronize_from_tb(CPUState *cs,
env->pc = tb_pc(tb);
}
+
+static void loongarch_restore_state_to_opc(CPUState *cs,
+ const TranslationBlock *tb,
+ const uint64_t *data)
+{
+ LoongArchCPU *cpu = LOONGARCH_CPU(cs);
+ CPULoongArchState *env = &cpu->env;
+
+ env->pc = data[0];
+}
#endif /* CONFIG_TCG */
static bool loongarch_cpu_has_work(CPUState *cs)
@@ -651,6 +661,7 @@ void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags)
static struct TCGCPUOps loongarch_tcg_ops = {
.initialize = loongarch_translate_init,
.synchronize_from_tb = loongarch_cpu_synchronize_from_tb,
+ .restore_state_to_opc = loongarch_restore_state_to_opc,
#ifndef CONFIG_USER_ONLY
.tlb_fill = loongarch_cpu_tlb_fill,
diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c
index 95b37ea180..6091772349 100644
--- a/target/loongarch/translate.c
+++ b/target/loongarch/translate.c
@@ -272,9 +272,3 @@ void loongarch_translate_init(void)
cpu_llval = tcg_global_mem_new(cpu_env,
offsetof(CPULoongArchState, llval), "llval");
}
-
-void restore_state_to_opc(CPULoongArchState *env, TranslationBlock *tb,
- target_ulong *data)
-{
- env->pc = data[0];
-}
--
2.34.1
^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 10/29] target/m68k: Convert to tcg_ops restore_state_to_opc
2022-10-24 13:24 [PATCH 00/29] tcg: Fix x86 TARGET_TB_PCREL (#1269) Richard Henderson
` (9 preceding siblings ...)
2022-10-24 13:24 ` [PATCH 09/29] target/loongarch: " Richard Henderson
@ 2022-10-24 13:24 ` Richard Henderson
2022-10-24 17:55 ` Philippe Mathieu-Daudé
2022-10-24 13:24 ` [PATCH 11/29] target/microblaze: " Richard Henderson
` (18 subsequent siblings)
29 siblings, 1 reply; 64+ messages in thread
From: Richard Henderson @ 2022-10-24 13:24 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/m68k/cpu.c | 14 ++++++++++++++
target/m68k/translate.c | 10 ----------
2 files changed, 14 insertions(+), 10 deletions(-)
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index 1e902e1ef0..b67ddea2ae 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -38,6 +38,19 @@ static vaddr m68k_cpu_get_pc(CPUState *cs)
return cpu->env.pc;
}
+static void m68k_restore_state_to_opc(CPUState *cs,
+ const TranslationBlock *tb,
+ const uint64_t *data)
+{
+ M68kCPU *cpu = M68K_CPU(cs);
+ int cc_op = data[1];
+
+ cpu->env.pc = data[0];
+ if (cc_op != CC_OP_DYNAMIC) {
+ cpu->env.cc_op = cc_op;
+ }
+}
+
static bool m68k_cpu_has_work(CPUState *cs)
{
return cs->interrupt_request & CPU_INTERRUPT_HARD;
@@ -524,6 +537,7 @@ static const struct SysemuCPUOps m68k_sysemu_ops = {
static const struct TCGCPUOps m68k_tcg_ops = {
.initialize = m68k_tcg_init,
+ .restore_state_to_opc = m68k_restore_state_to_opc,
#ifndef CONFIG_USER_ONLY
.tlb_fill = m68k_cpu_tlb_fill,
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index 9df17aa4b2..5cbde4be34 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -6479,13 +6479,3 @@ void m68k_cpu_dump_state(CPUState *cs, FILE *f, int flags)
env->mmu.mmusr, env->mmu.ar);
#endif
}
-
-void restore_state_to_opc(CPUM68KState *env, TranslationBlock *tb,
- target_ulong *data)
-{
- int cc_op = data[1];
- env->pc = data[0];
- if (cc_op != CC_OP_DYNAMIC) {
- env->cc_op = cc_op;
- }
-}
--
2.34.1
^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 11/29] target/microblaze: Convert to tcg_ops restore_state_to_opc
2022-10-24 13:24 [PATCH 00/29] tcg: Fix x86 TARGET_TB_PCREL (#1269) Richard Henderson
` (10 preceding siblings ...)
2022-10-24 13:24 ` [PATCH 10/29] target/m68k: " Richard Henderson
@ 2022-10-24 13:24 ` Richard Henderson
2022-10-24 17:56 ` Philippe Mathieu-Daudé
2022-10-24 13:24 ` [PATCH 12/29] target/mips: " Richard Henderson
` (17 subsequent siblings)
29 siblings, 1 reply; 64+ messages in thread
From: Richard Henderson @ 2022-10-24 13:24 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/microblaze/cpu.c | 11 +++++++++++
target/microblaze/translate.c | 7 -------
2 files changed, 11 insertions(+), 7 deletions(-)
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index c10b8ac029..89e493f3ff 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -100,6 +100,16 @@ static void mb_cpu_synchronize_from_tb(CPUState *cs,
cpu->env.iflags = tb->flags & IFLAGS_TB_MASK;
}
+static void mb_restore_state_to_opc(CPUState *cs,
+ const TranslationBlock *tb,
+ const uint64_t *data)
+{
+ MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
+
+ cpu->env.pc = data[0];
+ cpu->env.iflags = data[1];
+}
+
static bool mb_cpu_has_work(CPUState *cs)
{
return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
@@ -373,6 +383,7 @@ static const struct SysemuCPUOps mb_sysemu_ops = {
static const struct TCGCPUOps mb_tcg_ops = {
.initialize = mb_tcg_init,
.synchronize_from_tb = mb_cpu_synchronize_from_tb,
+ .restore_state_to_opc = mb_restore_state_to_opc,
#ifndef CONFIG_USER_ONLY
.tlb_fill = mb_cpu_tlb_fill,
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index c5546f93aa..974f21eb31 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -1946,10 +1946,3 @@ void mb_tcg_init(void)
cpu_res_addr =
tcg_global_mem_new(cpu_env, offsetof(CPUMBState, res_addr), "res_addr");
}
-
-void restore_state_to_opc(CPUMBState *env, TranslationBlock *tb,
- target_ulong *data)
-{
- env->pc = data[0];
- env->iflags = data[1];
-}
--
2.34.1
^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 12/29] target/mips: Convert to tcg_ops restore_state_to_opc
2022-10-24 13:24 [PATCH 00/29] tcg: Fix x86 TARGET_TB_PCREL (#1269) Richard Henderson
` (11 preceding siblings ...)
2022-10-24 13:24 ` [PATCH 11/29] target/microblaze: " Richard Henderson
@ 2022-10-24 13:24 ` Richard Henderson
2022-10-24 14:02 ` Philippe Mathieu-Daudé
2022-10-24 13:24 ` [PATCH 13/29] target/nios2: " Richard Henderson
` (16 subsequent siblings)
29 siblings, 1 reply; 64+ messages in thread
From: Richard Henderson @ 2022-10-24 13:24 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/mips/tcg/tcg-internal.h | 3 +++
target/mips/cpu.c | 1 +
target/mips/tcg/translate.c | 8 ++++++--
3 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h
index 1d27fa2ff9..aef032c48d 100644
--- a/target/mips/tcg/tcg-internal.h
+++ b/target/mips/tcg/tcg-internal.h
@@ -21,6 +21,9 @@ void mips_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb);
G_NORETURN void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
MMUAccessType access_type, int mmu_idx,
uintptr_t retaddr);
+void mips_restore_state_to_opc(CPUState *cs,
+ const TranslationBlock *tb,
+ const uint64_t *data);
const char *mips_exception_name(int32_t exception);
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index da58eb8892..e997c1b9cb 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -538,6 +538,7 @@ static const struct SysemuCPUOps mips_sysemu_ops = {
static const struct TCGCPUOps mips_tcg_ops = {
.initialize = mips_tcg_init,
.synchronize_from_tb = mips_cpu_synchronize_from_tb,
+ .restore_state_to_opc = mips_restore_state_to_opc,
#if !defined(CONFIG_USER_ONLY)
.tlb_fill = mips_cpu_tlb_fill,
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index c3f92ea652..2f2d707a12 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -16229,9 +16229,13 @@ void mips_tcg_init(void)
}
}
-void restore_state_to_opc(CPUMIPSState *env, TranslationBlock *tb,
- target_ulong *data)
+void mips_restore_state_to_opc(CPUState *cs,
+ const TranslationBlock *tb,
+ const uint64_t *data)
{
+ MIPSCPU *cpu = MIPS_CPU(cs);
+ CPUMIPSState *env = &cpu->env;
+
env->active_tc.PC = data[0];
env->hflags &= ~MIPS_HFLAG_BMASK;
env->hflags |= data[1];
--
2.34.1
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH 12/29] target/mips: Convert to tcg_ops restore_state_to_opc
2022-10-24 13:24 ` [PATCH 12/29] target/mips: " Richard Henderson
@ 2022-10-24 14:02 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 64+ messages in thread
From: Philippe Mathieu-Daudé @ 2022-10-24 14:02 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
On 24/10/22 15:24, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/mips/tcg/tcg-internal.h | 3 +++
> target/mips/cpu.c | 1 +
> target/mips/tcg/translate.c | 8 ++++++--
> 3 files changed, 10 insertions(+), 2 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH 13/29] target/nios2: Convert to tcg_ops restore_state_to_opc
2022-10-24 13:24 [PATCH 00/29] tcg: Fix x86 TARGET_TB_PCREL (#1269) Richard Henderson
` (12 preceding siblings ...)
2022-10-24 13:24 ` [PATCH 12/29] target/mips: " Richard Henderson
@ 2022-10-24 13:24 ` Richard Henderson
2022-10-24 14:03 ` Philippe Mathieu-Daudé
2022-10-24 13:24 ` [PATCH 14/29] target/openrisc: " Richard Henderson
` (15 subsequent siblings)
29 siblings, 1 reply; 64+ messages in thread
From: Richard Henderson @ 2022-10-24 13:24 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/nios2/cpu.c | 11 +++++++++++
target/nios2/translate.c | 6 ------
2 files changed, 11 insertions(+), 6 deletions(-)
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index 2b28429c08..9a5351bc81 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -42,6 +42,16 @@ static vaddr nios2_cpu_get_pc(CPUState *cs)
return env->pc;
}
+static void nios2_restore_state_to_opc(CPUState *cs,
+ const TranslationBlock *tb,
+ const uint64_t *data)
+{
+ Nios2CPU *cpu = NIOS2_CPU(cs);
+ CPUNios2State *env = &cpu->env;
+
+ env->pc = data[0];
+}
+
static bool nios2_cpu_has_work(CPUState *cs)
{
return cs->interrupt_request & CPU_INTERRUPT_HARD;
@@ -346,6 +356,7 @@ static const struct SysemuCPUOps nios2_sysemu_ops = {
static const struct TCGCPUOps nios2_tcg_ops = {
.initialize = nios2_tcg_init,
+ .restore_state_to_opc = nios2_restore_state_to_opc,
#ifndef CONFIG_USER_ONLY
.tlb_fill = nios2_cpu_tlb_fill,
diff --git a/target/nios2/translate.c b/target/nios2/translate.c
index 8dc0a32c6c..4db8b47744 100644
--- a/target/nios2/translate.c
+++ b/target/nios2/translate.c
@@ -1110,9 +1110,3 @@ void nios2_tcg_init(void)
cpu_pc = tcg_global_mem_new(cpu_env,
offsetof(CPUNios2State, pc), "pc");
}
-
-void restore_state_to_opc(CPUNios2State *env, TranslationBlock *tb,
- target_ulong *data)
-{
- env->pc = data[0];
-}
--
2.34.1
^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 14/29] target/openrisc: Convert to tcg_ops restore_state_to_opc
2022-10-24 13:24 [PATCH 00/29] tcg: Fix x86 TARGET_TB_PCREL (#1269) Richard Henderson
` (13 preceding siblings ...)
2022-10-24 13:24 ` [PATCH 13/29] target/nios2: " Richard Henderson
@ 2022-10-24 13:24 ` Richard Henderson
2022-10-24 15:00 ` Philippe Mathieu-Daudé
2022-10-24 13:24 ` [PATCH 15/29] target/ppc: " Richard Henderson
` (14 subsequent siblings)
29 siblings, 1 reply; 64+ messages in thread
From: Richard Henderson @ 2022-10-24 13:24 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/openrisc/cpu.c | 13 +++++++++++++
target/openrisc/translate.c | 10 ----------
2 files changed, 13 insertions(+), 10 deletions(-)
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index f6fd437785..de0176cd20 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -46,6 +46,18 @@ static void openrisc_cpu_synchronize_from_tb(CPUState *cs,
cpu->env.pc = tb_pc(tb);
}
+static void openrisc_restore_state_to_opc(CPUState *cs,
+ const TranslationBlock *tb,
+ const uint64_t *data)
+{
+ OpenRISCCPU *cpu = OPENRISC_CPU(cs);
+
+ cpu->env.pc = data[0];
+ cpu->env.dflag = data[1] & 1;
+ if (data[1] & 2) {
+ cpu->env.ppc = cpu->env.pc - 4;
+ }
+}
static bool openrisc_cpu_has_work(CPUState *cs)
{
@@ -203,6 +215,7 @@ static const struct SysemuCPUOps openrisc_sysemu_ops = {
static const struct TCGCPUOps openrisc_tcg_ops = {
.initialize = openrisc_translate_init,
.synchronize_from_tb = openrisc_cpu_synchronize_from_tb,
+ .restore_state_to_opc = openrisc_restore_state_to_opc,
#ifndef CONFIG_USER_ONLY
.tlb_fill = openrisc_cpu_tlb_fill,
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index 8154f9d744..2f3d7c5fd1 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -1726,13 +1726,3 @@ void openrisc_cpu_dump_state(CPUState *cs, FILE *f, int flags)
(i % 4) == 3 ? '\n' : ' ');
}
}
-
-void restore_state_to_opc(CPUOpenRISCState *env, TranslationBlock *tb,
- target_ulong *data)
-{
- env->pc = data[0];
- env->dflag = data[1] & 1;
- if (data[1] & 2) {
- env->ppc = env->pc - 4;
- }
-}
--
2.34.1
^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 15/29] target/ppc: Convert to tcg_ops restore_state_to_opc
2022-10-24 13:24 [PATCH 00/29] tcg: Fix x86 TARGET_TB_PCREL (#1269) Richard Henderson
` (14 preceding siblings ...)
2022-10-24 13:24 ` [PATCH 14/29] target/openrisc: " Richard Henderson
@ 2022-10-24 13:24 ` Richard Henderson
2022-10-24 17:56 ` Philippe Mathieu-Daudé
2022-10-24 13:24 ` [PATCH 16/29] target/riscv: " Richard Henderson
` (13 subsequent siblings)
29 siblings, 1 reply; 64+ messages in thread
From: Richard Henderson @ 2022-10-24 13:24 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/ppc/cpu_init.c | 10 ++++++++++
target/ppc/translate.c | 6 ------
2 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 763a8431be..335351c226 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -7221,6 +7221,15 @@ static vaddr ppc_cpu_get_pc(CPUState *cs)
return cpu->env.nip;
}
+static void ppc_restore_state_to_opc(CPUState *cs,
+ const TranslationBlock *tb,
+ const uint64_t *data)
+{
+ PowerPCCPU *cpu = POWERPC_CPU(cs);
+
+ cpu->env.nip = data[0];
+}
+
static bool ppc_cpu_has_work(CPUState *cs)
{
PowerPCCPU *cpu = POWERPC_CPU(cs);
@@ -7446,6 +7455,7 @@ static const struct SysemuCPUOps ppc_sysemu_ops = {
static const struct TCGCPUOps ppc_tcg_ops = {
.initialize = ppc_translate_init,
+ .restore_state_to_opc = ppc_restore_state_to_opc,
#ifdef CONFIG_USER_ONLY
.record_sigsegv = ppc_cpu_record_sigsegv,
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index e810842925..7228857e23 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -7739,9 +7739,3 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns,
translator_loop(cs, tb, max_insns, pc, host_pc, &ppc_tr_ops, &ctx.base);
}
-
-void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb,
- target_ulong *data)
-{
- env->nip = data[0];
-}
--
2.34.1
^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 16/29] target/riscv: Convert to tcg_ops restore_state_to_opc
2022-10-24 13:24 [PATCH 00/29] tcg: Fix x86 TARGET_TB_PCREL (#1269) Richard Henderson
` (15 preceding siblings ...)
2022-10-24 13:24 ` [PATCH 15/29] target/ppc: " Richard Henderson
@ 2022-10-24 13:24 ` Richard Henderson
2022-10-24 14:03 ` Philippe Mathieu-Daudé
2022-10-24 13:24 ` [PATCH 17/29] target/rx: " Richard Henderson
` (12 subsequent siblings)
29 siblings, 1 reply; 64+ messages in thread
From: Richard Henderson @ 2022-10-24 13:24 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/cpu.c | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index e6d9c706bb..d14e95c9dc 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -503,10 +503,14 @@ static bool riscv_cpu_has_work(CPUState *cs)
#endif
}
-void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb,
- target_ulong *data)
+static void riscv_restore_state_to_opc(CPUState *cs,
+ const TranslationBlock *tb,
+ const uint64_t *data)
{
+ RISCVCPU *cpu = RISCV_CPU(cs);
+ CPURISCVState *env = &cpu->env;
RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
+
if (xl == MXL_RV32) {
env->pc = (int32_t)data[0];
} else {
@@ -1138,6 +1142,7 @@ static const struct SysemuCPUOps riscv_sysemu_ops = {
static const struct TCGCPUOps riscv_tcg_ops = {
.initialize = riscv_translate_init,
.synchronize_from_tb = riscv_cpu_synchronize_from_tb,
+ .restore_state_to_opc = riscv_restore_state_to_opc,
#ifndef CONFIG_USER_ONLY
.tlb_fill = riscv_cpu_tlb_fill,
--
2.34.1
^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 17/29] target/rx: Convert to tcg_ops restore_state_to_opc
2022-10-24 13:24 [PATCH 00/29] tcg: Fix x86 TARGET_TB_PCREL (#1269) Richard Henderson
` (16 preceding siblings ...)
2022-10-24 13:24 ` [PATCH 16/29] target/riscv: " Richard Henderson
@ 2022-10-24 13:24 ` Richard Henderson
2022-10-24 14:03 ` Philippe Mathieu-Daudé
2022-10-24 13:24 ` [PATCH 18/29] target/s390x: " Richard Henderson
` (11 subsequent siblings)
29 siblings, 1 reply; 64+ messages in thread
From: Richard Henderson @ 2022-10-24 13:24 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/rx/cpu.c | 10 ++++++++++
target/rx/translate.c | 6 ------
2 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index 2f28099723..9003c6e9fe 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -47,6 +47,15 @@ static void rx_cpu_synchronize_from_tb(CPUState *cs,
cpu->env.pc = tb_pc(tb);
}
+static void rx_restore_state_to_opc(CPUState *cs,
+ const TranslationBlock *tb,
+ const uint64_t *data)
+{
+ RXCPU *cpu = RX_CPU(cs);
+
+ cpu->env.pc = data[0];
+}
+
static bool rx_cpu_has_work(CPUState *cs)
{
return cs->interrupt_request &
@@ -192,6 +201,7 @@ static const struct SysemuCPUOps rx_sysemu_ops = {
static const struct TCGCPUOps rx_tcg_ops = {
.initialize = rx_translate_init,
.synchronize_from_tb = rx_cpu_synchronize_from_tb,
+ .restore_state_to_opc = rx_restore_state_to_opc,
.tlb_fill = rx_cpu_tlb_fill,
#ifndef CONFIG_USER_ONLY
diff --git a/target/rx/translate.c b/target/rx/translate.c
index ea5653bc95..87a3f54adb 100644
--- a/target/rx/translate.c
+++ b/target/rx/translate.c
@@ -2371,12 +2371,6 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns,
translator_loop(cs, tb, max_insns, pc, host_pc, &rx_tr_ops, &dc.base);
}
-void restore_state_to_opc(CPURXState *env, TranslationBlock *tb,
- target_ulong *data)
-{
- env->pc = data[0];
-}
-
#define ALLOC_REGISTER(sym, name) \
cpu_##sym = tcg_global_mem_new_i32(cpu_env, \
offsetof(CPURXState, sym), name)
--
2.34.1
^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 18/29] target/s390x: Convert to tcg_ops restore_state_to_opc
2022-10-24 13:24 [PATCH 00/29] tcg: Fix x86 TARGET_TB_PCREL (#1269) Richard Henderson
` (17 preceding siblings ...)
2022-10-24 13:24 ` [PATCH 17/29] target/rx: " Richard Henderson
@ 2022-10-24 13:24 ` Richard Henderson
2022-10-24 14:05 ` Philippe Mathieu-Daudé
2022-10-24 13:24 ` [PATCH 19/29] target/sh4: " Richard Henderson
` (10 subsequent siblings)
29 siblings, 1 reply; 64+ messages in thread
From: Richard Henderson @ 2022-10-24 13:24 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/s390x/s390x-internal.h | 4 +++-
target/s390x/cpu.c | 1 +
target/s390x/tcg/translate.c | 7 +++++--
3 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/target/s390x/s390x-internal.h b/target/s390x/s390x-internal.h
index b5ae0ae364..5d4361d35b 100644
--- a/target/s390x/s390x-internal.h
+++ b/target/s390x/s390x-internal.h
@@ -398,7 +398,9 @@ void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3,
/* translate.c */
void s390x_translate_init(void);
-
+void s390x_restore_state_to_opc(CPUState *cs,
+ const TranslationBlock *tb,
+ const uint64_t *data);
/* sigp.c */
int handle_sigp(CPUS390XState *env, uint8_t order, uint64_t r1, uint64_t r3);
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index df00040e95..96562c516d 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -272,6 +272,7 @@ static void s390_cpu_reset_full(DeviceState *dev)
static const struct TCGCPUOps s390_tcg_ops = {
.initialize = s390x_translate_init,
+ .restore_state_to_opc = s390x_restore_state_to_opc,
#ifdef CONFIG_USER_ONLY
.record_sigsegv = s390_cpu_record_sigsegv,
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
index 1d2dddab1c..5798928473 100644
--- a/target/s390x/tcg/translate.c
+++ b/target/s390x/tcg/translate.c
@@ -6691,9 +6691,12 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns,
translator_loop(cs, tb, max_insns, pc, host_pc, &s390x_tr_ops, &dc.base);
}
-void restore_state_to_opc(CPUS390XState *env, TranslationBlock *tb,
- target_ulong *data)
+void s390x_restore_state_to_opc(CPUState *cs,
+ const TranslationBlock *tb,
+ const uint64_t *data)
{
+ S390CPU *cpu = S390_CPU(cs);
+ CPUS390XState *env = &cpu->env;
int cc_op = data[1];
env->psw.addr = data[0];
--
2.34.1
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH 18/29] target/s390x: Convert to tcg_ops restore_state_to_opc
2022-10-24 13:24 ` [PATCH 18/29] target/s390x: " Richard Henderson
@ 2022-10-24 14:05 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 64+ messages in thread
From: Philippe Mathieu-Daudé @ 2022-10-24 14:05 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
On 24/10/22 15:24, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/s390x/s390x-internal.h | 4 +++-
> target/s390x/cpu.c | 1 +
> target/s390x/tcg/translate.c | 7 +++++--
> 3 files changed, 9 insertions(+), 3 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH 19/29] target/sh4: Convert to tcg_ops restore_state_to_opc
2022-10-24 13:24 [PATCH 00/29] tcg: Fix x86 TARGET_TB_PCREL (#1269) Richard Henderson
` (18 preceding siblings ...)
2022-10-24 13:24 ` [PATCH 18/29] target/s390x: " Richard Henderson
@ 2022-10-24 13:24 ` Richard Henderson
2022-10-24 14:04 ` Philippe Mathieu-Daudé
2022-10-24 13:24 ` [PATCH 20/29] target/sparc: " Richard Henderson
` (9 subsequent siblings)
29 siblings, 1 reply; 64+ messages in thread
From: Richard Henderson @ 2022-10-24 13:24 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sh4/cpu.c | 16 ++++++++++++++++
target/sh4/translate.c | 10 ----------
2 files changed, 16 insertions(+), 10 deletions(-)
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index 56c50530da..453268392b 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -50,6 +50,21 @@ static void superh_cpu_synchronize_from_tb(CPUState *cs,
cpu->env.flags = tb->flags;
}
+static void superh_restore_state_to_opc(CPUState *cs,
+ const TranslationBlock *tb,
+ const uint64_t *data)
+{
+ SuperHCPU *cpu = SUPERH_CPU(cs);
+
+ cpu->env.pc = data[0];
+ cpu->env.flags = data[1];
+ /*
+ * Theoretically delayed_pc should also be restored. In practice the
+ * branch instruction is re-executed after exception, so the delayed
+ * branch target will be recomputed.
+ */
+}
+
#ifndef CONFIG_USER_ONLY
static bool superh_io_recompile_replay_branch(CPUState *cs,
const TranslationBlock *tb)
@@ -243,6 +258,7 @@ static const struct SysemuCPUOps sh4_sysemu_ops = {
static const struct TCGCPUOps superh_tcg_ops = {
.initialize = sh4_translate_init,
.synchronize_from_tb = superh_cpu_synchronize_from_tb,
+ .restore_state_to_opc = superh_restore_state_to_opc,
#ifndef CONFIG_USER_ONLY
.tlb_fill = superh_cpu_tlb_fill,
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index 26231b2a5a..7db3468b01 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -2381,13 +2381,3 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns,
translator_loop(cs, tb, max_insns, pc, host_pc, &sh4_tr_ops, &ctx.base);
}
-
-void restore_state_to_opc(CPUSH4State *env, TranslationBlock *tb,
- target_ulong *data)
-{
- env->pc = data[0];
- env->flags = data[1];
- /* Theoretically delayed_pc should also be restored. In practice the
- branch instruction is re-executed after exception, so the delayed
- branch target will be recomputed. */
-}
--
2.34.1
^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 20/29] target/sparc: Convert to tcg_ops restore_state_to_opc
2022-10-24 13:24 [PATCH 00/29] tcg: Fix x86 TARGET_TB_PCREL (#1269) Richard Henderson
` (19 preceding siblings ...)
2022-10-24 13:24 ` [PATCH 19/29] target/sh4: " Richard Henderson
@ 2022-10-24 13:24 ` Richard Henderson
2022-10-24 14:07 ` Philippe Mathieu-Daudé
2022-10-24 13:24 ` [PATCH 21/29] target/tricore: " Richard Henderson
` (8 subsequent siblings)
29 siblings, 1 reply; 64+ messages in thread
From: Richard Henderson @ 2022-10-24 13:24 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sparc/cpu.h | 3 +++
target/sparc/cpu.c | 1 +
target/sparc/translate.c | 7 +++++--
3 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index f80ea2e8cf..e478c5eb16 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -600,6 +600,9 @@ int sparc_cpu_memory_rw_debug(CPUState *cpu, vaddr addr,
/* translate.c */
void sparc_tcg_init(void);
+void sparc_restore_state_to_opc(CPUState *cs,
+ const TranslationBlock *tb,
+ const uint64_t *data);
/* cpu-exec.c */
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index 1f9ef7afd8..4c3d08a875 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -872,6 +872,7 @@ static const struct SysemuCPUOps sparc_sysemu_ops = {
static const struct TCGCPUOps sparc_tcg_ops = {
.initialize = sparc_tcg_init,
.synchronize_from_tb = sparc_cpu_synchronize_from_tb,
+ .restore_state_to_opc = sparc_restore_state_to_opc,
#ifndef CONFIG_USER_ONLY
.tlb_fill = sparc_cpu_tlb_fill,
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 2cbbe2396a..34858eb95f 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -6011,9 +6011,12 @@ void sparc_tcg_init(void)
}
}
-void restore_state_to_opc(CPUSPARCState *env, TranslationBlock *tb,
- target_ulong *data)
+void sparc_restore_state_to_opc(CPUState *cs,
+ const TranslationBlock *tb,
+ const uint64_t *data)
{
+ SPARCCPU *cpu = SPARC_CPU(cs);
+ CPUSPARCState *env = &cpu->env;
target_ulong pc = data[0];
target_ulong npc = data[1];
--
2.34.1
^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 21/29] target/tricore: Convert to tcg_ops restore_state_to_opc
2022-10-24 13:24 [PATCH 00/29] tcg: Fix x86 TARGET_TB_PCREL (#1269) Richard Henderson
` (20 preceding siblings ...)
2022-10-24 13:24 ` [PATCH 20/29] target/sparc: " Richard Henderson
@ 2022-10-24 13:24 ` Richard Henderson
2022-10-24 14:04 ` Philippe Mathieu-Daudé
2022-10-24 13:24 ` [PATCH 22/29] target/xtensa: " Richard Henderson
` (7 subsequent siblings)
29 siblings, 1 reply; 64+ messages in thread
From: Richard Henderson @ 2022-10-24 13:24 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/tricore/cpu.c | 11 +++++++++++
target/tricore/translate.c | 6 ------
2 files changed, 11 insertions(+), 6 deletions(-)
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index ab7a1e3a6d..2c54a2825f 100644
--- a/target/tricore/cpu.c
+++ b/target/tricore/cpu.c
@@ -58,6 +58,16 @@ static void tricore_cpu_synchronize_from_tb(CPUState *cs,
env->PC = tb_pc(tb);
}
+static void tricore_restore_state_to_opc(CPUState *cs,
+ const TranslationBlock *tb,
+ const uint64_t *data)
+{
+ TriCoreCPU *cpu = TRICORE_CPU(cs);
+ CPUTriCoreState *env = &cpu->env;
+
+ env->PC = data[0];
+}
+
static void tricore_cpu_reset(DeviceState *dev)
{
CPUState *s = CPU(dev);
@@ -161,6 +171,7 @@ static const struct SysemuCPUOps tricore_sysemu_ops = {
static const struct TCGCPUOps tricore_tcg_ops = {
.initialize = tricore_tcg_init,
.synchronize_from_tb = tricore_cpu_synchronize_from_tb,
+ .restore_state_to_opc = tricore_restore_state_to_opc,
.tlb_fill = tricore_cpu_tlb_fill,
};
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index a0558ead71..c5b7bfbf20 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -8886,12 +8886,6 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns,
&tricore_tr_ops, &ctx.base);
}
-void
-restore_state_to_opc(CPUTriCoreState *env, TranslationBlock *tb,
- target_ulong *data)
-{
- env->PC = data[0];
-}
/*
*
* Initialization
--
2.34.1
^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 22/29] target/xtensa: Convert to tcg_ops restore_state_to_opc
2022-10-24 13:24 [PATCH 00/29] tcg: Fix x86 TARGET_TB_PCREL (#1269) Richard Henderson
` (21 preceding siblings ...)
2022-10-24 13:24 ` [PATCH 21/29] target/tricore: " Richard Henderson
@ 2022-10-24 13:24 ` Richard Henderson
2022-10-24 17:56 ` Philippe Mathieu-Daudé
2022-10-24 13:24 ` [PATCH 23/29] accel/tcg: Remove restore_state_to_opc function Richard Henderson
` (6 subsequent siblings)
29 siblings, 1 reply; 64+ messages in thread
From: Richard Henderson @ 2022-10-24 13:24 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/xtensa/cpu.c | 10 ++++++++++
target/xtensa/translate.c | 6 ------
2 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index cbbe0e84a2..09923301c4 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -51,6 +51,15 @@ static vaddr xtensa_cpu_get_pc(CPUState *cs)
return cpu->env.pc;
}
+static void xtensa_restore_state_to_opc(CPUState *cs,
+ const TranslationBlock *tb,
+ const uint64_t *data)
+{
+ XtensaCPU *cpu = XTENSA_CPU(cs);
+
+ cpu->env.pc = data[0];
+}
+
static bool xtensa_cpu_has_work(CPUState *cs)
{
#ifndef CONFIG_USER_ONLY
@@ -215,6 +224,7 @@ static const struct SysemuCPUOps xtensa_sysemu_ops = {
static const struct TCGCPUOps xtensa_tcg_ops = {
.initialize = xtensa_translate_init,
.debug_excp_handler = xtensa_breakpoint_handler,
+ .restore_state_to_opc = xtensa_restore_state_to_opc,
#ifndef CONFIG_USER_ONLY
.tlb_fill = xtensa_cpu_tlb_fill,
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index bdd4690a5c..77bcd71030 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -1355,12 +1355,6 @@ void xtensa_cpu_dump_state(CPUState *cs, FILE *f, int flags)
}
}
-void restore_state_to_opc(CPUXtensaState *env, TranslationBlock *tb,
- target_ulong *data)
-{
- env->pc = data[0];
-}
-
static void translate_abs(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
--
2.34.1
^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 23/29] accel/tcg: Remove restore_state_to_opc function
2022-10-24 13:24 [PATCH 00/29] tcg: Fix x86 TARGET_TB_PCREL (#1269) Richard Henderson
` (22 preceding siblings ...)
2022-10-24 13:24 ` [PATCH 22/29] target/xtensa: " Richard Henderson
@ 2022-10-24 13:24 ` Richard Henderson
2022-10-25 8:56 ` Claudio Fontana
2022-10-24 13:24 ` [PATCH 24/29] accel/tcg: Introduce cpu_unwind_state_data Richard Henderson
` (5 subsequent siblings)
29 siblings, 1 reply; 64+ messages in thread
From: Richard Henderson @ 2022-10-24 13:24 UTC (permalink / raw)
To: qemu-devel
All targets have been updated. Use the tcg_ops target hook
exclusively, which allows the compat code to be removed.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/exec-all.h | 3 ---
accel/tcg/translate-all.c | 16 ++--------------
2 files changed, 2 insertions(+), 17 deletions(-)
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index a772e8cbdc..300832bd0b 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -39,9 +39,6 @@ typedef ram_addr_t tb_page_addr_t;
#define TB_PAGE_ADDR_FMT RAM_ADDR_FMT
#endif
-void restore_state_to_opc(CPUArchState *env, TranslationBlock *tb,
- target_ulong *data) __attribute__((weak));
-
/**
* cpu_restore_state:
* @cpu: the vCPU state is to be restore to
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index 19cd23e9a0..e4386b3198 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -327,7 +327,7 @@ static int encode_search(TranslationBlock *tb, uint8_t *block)
static int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb,
uintptr_t searched_pc, bool reset_icount)
{
- target_ulong data[TARGET_INSN_START_WORDS];
+ uint64_t data[TARGET_INSN_START_WORDS];
uintptr_t host_pc = (uintptr_t)tb->tc.ptr;
const uint8_t *p = tb->tc.ptr + tb->tc.size;
int i, j, num_insns = tb->icount;
@@ -368,19 +368,7 @@ static int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb,
cpu_neg(cpu)->icount_decr.u16.low += num_insns - i;
}
- {
- const struct TCGCPUOps *ops = cpu->cc->tcg_ops;
- __typeof(ops->restore_state_to_opc) restore = ops->restore_state_to_opc;
- if (restore) {
- uint64_t d64[TARGET_INSN_START_WORDS];
- for (i = 0; i < TARGET_INSN_START_WORDS; ++i) {
- d64[i] = data[i];
- }
- restore(cpu, tb, d64);
- } else {
- restore_state_to_opc(cpu->env_ptr, tb, data);
- }
- }
+ cpu->cc->tcg_ops->restore_state_to_opc(cpu, tb, data);
#ifdef CONFIG_PROFILER
qatomic_set(&prof->restore_time,
--
2.34.1
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH 23/29] accel/tcg: Remove restore_state_to_opc function
2022-10-24 13:24 ` [PATCH 23/29] accel/tcg: Remove restore_state_to_opc function Richard Henderson
@ 2022-10-25 8:56 ` Claudio Fontana
0 siblings, 0 replies; 64+ messages in thread
From: Claudio Fontana @ 2022-10-25 8:56 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Reviewed-by: Claudio Fontana <cfontana@suse.de>
On 10/24/22 15:24, Richard Henderson wrote:
> All targets have been updated. Use the tcg_ops target hook
> exclusively, which allows the compat code to be removed.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> include/exec/exec-all.h | 3 ---
> accel/tcg/translate-all.c | 16 ++--------------
> 2 files changed, 2 insertions(+), 17 deletions(-)
>
> diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
> index a772e8cbdc..300832bd0b 100644
> --- a/include/exec/exec-all.h
> +++ b/include/exec/exec-all.h
> @@ -39,9 +39,6 @@ typedef ram_addr_t tb_page_addr_t;
> #define TB_PAGE_ADDR_FMT RAM_ADDR_FMT
> #endif
>
> -void restore_state_to_opc(CPUArchState *env, TranslationBlock *tb,
> - target_ulong *data) __attribute__((weak));
> -
> /**
> * cpu_restore_state:
> * @cpu: the vCPU state is to be restore to
> diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
> index 19cd23e9a0..e4386b3198 100644
> --- a/accel/tcg/translate-all.c
> +++ b/accel/tcg/translate-all.c
> @@ -327,7 +327,7 @@ static int encode_search(TranslationBlock *tb, uint8_t *block)
> static int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb,
> uintptr_t searched_pc, bool reset_icount)
> {
> - target_ulong data[TARGET_INSN_START_WORDS];
> + uint64_t data[TARGET_INSN_START_WORDS];
> uintptr_t host_pc = (uintptr_t)tb->tc.ptr;
> const uint8_t *p = tb->tc.ptr + tb->tc.size;
> int i, j, num_insns = tb->icount;
> @@ -368,19 +368,7 @@ static int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb,
> cpu_neg(cpu)->icount_decr.u16.low += num_insns - i;
> }
>
> - {
> - const struct TCGCPUOps *ops = cpu->cc->tcg_ops;
> - __typeof(ops->restore_state_to_opc) restore = ops->restore_state_to_opc;
> - if (restore) {
> - uint64_t d64[TARGET_INSN_START_WORDS];
> - for (i = 0; i < TARGET_INSN_START_WORDS; ++i) {
> - d64[i] = data[i];
> - }
> - restore(cpu, tb, d64);
> - } else {
> - restore_state_to_opc(cpu->env_ptr, tb, data);
> - }
> - }
> + cpu->cc->tcg_ops->restore_state_to_opc(cpu, tb, data);
>
> #ifdef CONFIG_PROFILER
> qatomic_set(&prof->restore_time,
^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH 24/29] accel/tcg: Introduce cpu_unwind_state_data
2022-10-24 13:24 [PATCH 00/29] tcg: Fix x86 TARGET_TB_PCREL (#1269) Richard Henderson
` (23 preceding siblings ...)
2022-10-24 13:24 ` [PATCH 23/29] accel/tcg: Remove restore_state_to_opc function Richard Henderson
@ 2022-10-24 13:24 ` Richard Henderson
2022-10-25 9:23 ` Claudio Fontana
2022-10-24 13:24 ` [PATCH 25/29] target/i386: Use cpu_unwind_state_data for tpr access Richard Henderson
` (4 subsequent siblings)
29 siblings, 1 reply; 64+ messages in thread
From: Richard Henderson @ 2022-10-24 13:24 UTC (permalink / raw)
To: qemu-devel
Add a way to examine the unwind data without actually
restoring the data back into env.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/exec-all.h | 13 ++++++++
accel/tcg/translate-all.c | 68 ++++++++++++++++++++++++++-------------
2 files changed, 58 insertions(+), 23 deletions(-)
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index 300832bd0b..d49cf113dd 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -39,6 +39,19 @@ typedef ram_addr_t tb_page_addr_t;
#define TB_PAGE_ADDR_FMT RAM_ADDR_FMT
#endif
+/**
+ * cpu_unwind_state_data:
+ * @cpu: the vCPU state is to be restore to
+ * @host_pc: the host PC the fault occurred at
+ * @data: output data
+ *
+ * Attempt to load the the unwind state for a host pc occurring in
+ * translated code. If the searched_pc is not in translated code,
+ * the function returns false; otherwise @data is loaded.
+ * This is the same unwind info as given to restore_state_to_opc.
+ */
+bool cpu_unwind_state_data(CPUState *cpu, uintptr_t host_pc, uint64_t *data);
+
/**
* cpu_restore_state:
* @cpu: the vCPU state is to be restore to
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index e4386b3198..c772e3769c 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -320,29 +320,20 @@ static int encode_search(TranslationBlock *tb, uint8_t *block)
return p - block;
}
-/* The cpu state corresponding to 'searched_pc' is restored.
- * When reset_icount is true, current TB will be interrupted and
- * icount should be recalculated.
- */
-static int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb,
- uintptr_t searched_pc, bool reset_icount)
+static int cpu_unwind_data_from_tb(TranslationBlock *tb, uintptr_t host_pc,
+ uint64_t *data)
{
- uint64_t data[TARGET_INSN_START_WORDS];
- uintptr_t host_pc = (uintptr_t)tb->tc.ptr;
+ uintptr_t iter_pc = (uintptr_t)tb->tc.ptr;
const uint8_t *p = tb->tc.ptr + tb->tc.size;
int i, j, num_insns = tb->icount;
-#ifdef CONFIG_PROFILER
- TCGProfile *prof = &tcg_ctx->prof;
- int64_t ti = profile_getclock();
-#endif
- searched_pc -= GETPC_ADJ;
+ host_pc -= GETPC_ADJ;
- if (searched_pc < host_pc) {
+ if (host_pc < iter_pc) {
return -1;
}
- memset(data, 0, sizeof(data));
+ memset(data, 0, sizeof(uint64_t) * TARGET_INSN_START_WORDS);
if (!TARGET_TB_PCREL) {
data[0] = tb_pc(tb);
}
@@ -353,19 +344,40 @@ static int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb,
for (j = 0; j < TARGET_INSN_START_WORDS; ++j) {
data[j] += decode_sleb128(&p);
}
- host_pc += decode_sleb128(&p);
- if (host_pc > searched_pc) {
- goto found;
+ iter_pc += decode_sleb128(&p);
+ if (iter_pc > host_pc) {
+ return num_insns - i;
}
}
return -1;
+}
+
+/*
+ * The cpu state corresponding to 'host_pc' is restored.
+ * When reset_icount is true, current TB will be interrupted and
+ * icount should be recalculated.
+ */
+static void cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb,
+ uintptr_t host_pc, bool reset_icount)
+{
+ uint64_t data[TARGET_INSN_START_WORDS];
+#ifdef CONFIG_PROFILER
+ TCGProfile *prof = &tcg_ctx->prof;
+ int64_t ti = profile_getclock();
+#endif
+ int insns_left = cpu_unwind_data_from_tb(tb, host_pc, data);
+
+ if (insns_left < 0) {
+ return;
+ }
- found:
if (reset_icount && (tb_cflags(tb) & CF_USE_ICOUNT)) {
assert(icount_enabled());
- /* Reset the cycle counter to the start of the block
- and shift if to the number of actually executed instructions */
- cpu_neg(cpu)->icount_decr.u16.low += num_insns - i;
+ /*
+ * Reset the cycle counter to the start of the block and
+ * shift if to the number of actually executed instructions.
+ */
+ cpu_neg(cpu)->icount_decr.u16.low += insns_left;
}
cpu->cc->tcg_ops->restore_state_to_opc(cpu, tb, data);
@@ -375,7 +387,6 @@ static int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb,
prof->restore_time + profile_getclock() - ti);
qatomic_set(&prof->restore_count, prof->restore_count + 1);
#endif
- return 0;
}
bool cpu_restore_state(CPUState *cpu, uintptr_t host_pc, bool will_exit)
@@ -408,6 +419,17 @@ bool cpu_restore_state(CPUState *cpu, uintptr_t host_pc, bool will_exit)
return false;
}
+bool cpu_unwind_state_data(CPUState *cpu, uintptr_t host_pc, uint64_t *data)
+{
+ if (in_code_gen_buffer((const void *)(host_pc - tcg_splitwx_diff))) {
+ TranslationBlock *tb = tcg_tb_lookup(host_pc);
+ if (tb) {
+ return cpu_unwind_data_from_tb(tb, host_pc, data) >= 0;
+ }
+ }
+ return false;
+}
+
void page_init(void)
{
page_size_init();
--
2.34.1
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH 24/29] accel/tcg: Introduce cpu_unwind_state_data
2022-10-24 13:24 ` [PATCH 24/29] accel/tcg: Introduce cpu_unwind_state_data Richard Henderson
@ 2022-10-25 9:23 ` Claudio Fontana
2022-10-25 9:32 ` Claudio Fontana
2022-10-25 23:08 ` Richard Henderson
0 siblings, 2 replies; 64+ messages in thread
From: Claudio Fontana @ 2022-10-25 9:23 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
On 10/24/22 15:24, Richard Henderson wrote:
> Add a way to examine the unwind data without actually
> restoring the data back into env.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> include/exec/exec-all.h | 13 ++++++++
> accel/tcg/translate-all.c | 68 ++++++++++++++++++++++++++-------------
> 2 files changed, 58 insertions(+), 23 deletions(-)
>
> diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
> index 300832bd0b..d49cf113dd 100644
> --- a/include/exec/exec-all.h
> +++ b/include/exec/exec-all.h
> @@ -39,6 +39,19 @@ typedef ram_addr_t tb_page_addr_t;
> #define TB_PAGE_ADDR_FMT RAM_ADDR_FMT
> #endif
>
> +/**
> + * cpu_unwind_state_data:
> + * @cpu: the vCPU state is to be restore to
> + * @host_pc: the host PC the fault occurred at
> + * @data: output data
> + *
> + * Attempt to load the the unwind state for a host pc occurring in
> + * translated code. If the searched_pc is not in translated code,
> + * the function returns false; otherwise @data is loaded.
> + * This is the same unwind info as given to restore_state_to_opc.
> + */
> +bool cpu_unwind_state_data(CPUState *cpu, uintptr_t host_pc, uint64_t *data);
> +
> /**
> * cpu_restore_state:
> * @cpu: the vCPU state is to be restore to
> diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
> index e4386b3198..c772e3769c 100644
> --- a/accel/tcg/translate-all.c
> +++ b/accel/tcg/translate-all.c
> @@ -320,29 +320,20 @@ static int encode_search(TranslationBlock *tb, uint8_t *block)
> return p - block;
> }
>
> -/* The cpu state corresponding to 'searched_pc' is restored.
> - * When reset_icount is true, current TB will be interrupted and
> - * icount should be recalculated.
> - */
> -static int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb,
> - uintptr_t searched_pc, bool reset_icount)
> +static int cpu_unwind_data_from_tb(TranslationBlock *tb, uintptr_t host_pc,
> + uint64_t *data)
> {
> - uint64_t data[TARGET_INSN_START_WORDS];
> - uintptr_t host_pc = (uintptr_t)tb->tc.ptr;
> + uintptr_t iter_pc = (uintptr_t)tb->tc.ptr;
> const uint8_t *p = tb->tc.ptr + tb->tc.size;
> int i, j, num_insns = tb->icount;
> -#ifdef CONFIG_PROFILER
> - TCGProfile *prof = &tcg_ctx->prof;
> - int64_t ti = profile_getclock();
> -#endif
>
> - searched_pc -= GETPC_ADJ;
> + host_pc -= GETPC_ADJ;
>
> - if (searched_pc < host_pc) {
> + if (host_pc < iter_pc) {
> return -1;
> }
>
> - memset(data, 0, sizeof(data));
> + memset(data, 0, sizeof(uint64_t) * TARGET_INSN_START_WORDS);
> if (!TARGET_TB_PCREL) {
> data[0] = tb_pc(tb);
> }
It's not visible in this hunk, but what follows is:
/* Reconstruct the stored insn data while looking for the point at
which the end of the insn exceeds the searched_pc. */
Should this comment be adapted, minimally with s,searched_pc,host_pc, ?
> @@ -353,19 +344,40 @@ static int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb,
> for (j = 0; j < TARGET_INSN_START_WORDS; ++j) {
> data[j] += decode_sleb128(&p);
> }
> - host_pc += decode_sleb128(&p);
> - if (host_pc > searched_pc) {
> - goto found;
> + iter_pc += decode_sleb128(&p);
> + if (iter_pc > host_pc) {
> + return num_insns - i;
> }
> }
> return -1;
> +}
> +
> +/*
> + * The cpu state corresponding to 'host_pc' is restored.
> + * When reset_icount is true, current TB will be interrupted and
> + * icount should be recalculated.
> + */
> +static void cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb,
> + uintptr_t host_pc, bool reset_icount)
> +{
> + uint64_t data[TARGET_INSN_START_WORDS];
> +#ifdef CONFIG_PROFILER
> + TCGProfile *prof = &tcg_ctx->prof;
> + int64_t ti = profile_getclock();
> +#endif
> + int insns_left = cpu_unwind_data_from_tb(tb, host_pc, data);
> +
> + if (insns_left < 0) {
> + return;
> + }
Is the -1 return value some error condition to do anything about, log, tcg assert, or ...,
under some DEBUG_* condition, or ignored as done here?
Thanks,
Claudio
>
> - found:
> if (reset_icount && (tb_cflags(tb) & CF_USE_ICOUNT)) {
> assert(icount_enabled());
> - /* Reset the cycle counter to the start of the block
> - and shift if to the number of actually executed instructions */
> - cpu_neg(cpu)->icount_decr.u16.low += num_insns - i;
> + /*
> + * Reset the cycle counter to the start of the block and
> + * shift if to the number of actually executed instructions.
> + */
> + cpu_neg(cpu)->icount_decr.u16.low += insns_left;
> }
>
> cpu->cc->tcg_ops->restore_state_to_opc(cpu, tb, data);
> @@ -375,7 +387,6 @@ static int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb,
> prof->restore_time + profile_getclock() - ti);
> qatomic_set(&prof->restore_count, prof->restore_count + 1);
> #endif
> - return 0;
> }
>
> bool cpu_restore_state(CPUState *cpu, uintptr_t host_pc, bool will_exit)
> @@ -408,6 +419,17 @@ bool cpu_restore_state(CPUState *cpu, uintptr_t host_pc, bool will_exit)
> return false;
> }
>
> +bool cpu_unwind_state_data(CPUState *cpu, uintptr_t host_pc, uint64_t *data)
> +{
> + if (in_code_gen_buffer((const void *)(host_pc - tcg_splitwx_diff))) {
> + TranslationBlock *tb = tcg_tb_lookup(host_pc);
> + if (tb) {
> + return cpu_unwind_data_from_tb(tb, host_pc, data) >= 0;
> + }
> + }
> + return false;
> +}
> +
> void page_init(void)
> {
> page_size_init();
^ permalink raw reply [flat|nested] 64+ messages in thread* Re: [PATCH 24/29] accel/tcg: Introduce cpu_unwind_state_data
2022-10-25 9:23 ` Claudio Fontana
@ 2022-10-25 9:32 ` Claudio Fontana
2022-10-25 23:08 ` Richard Henderson
1 sibling, 0 replies; 64+ messages in thread
From: Claudio Fontana @ 2022-10-25 9:32 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
On 10/25/22 11:23, Claudio Fontana wrote:
> On 10/24/22 15:24, Richard Henderson wrote:
>> Add a way to examine the unwind data without actually
>> restoring the data back into env.
>>
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>> include/exec/exec-all.h | 13 ++++++++
>> accel/tcg/translate-all.c | 68 ++++++++++++++++++++++++++-------------
>> 2 files changed, 58 insertions(+), 23 deletions(-)
>>
>> diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
>> index 300832bd0b..d49cf113dd 100644
>> --- a/include/exec/exec-all.h
>> +++ b/include/exec/exec-all.h
>> @@ -39,6 +39,19 @@ typedef ram_addr_t tb_page_addr_t;
>> #define TB_PAGE_ADDR_FMT RAM_ADDR_FMT
>> #endif
>>
>> +/**
>> + * cpu_unwind_state_data:
>> + * @cpu: the vCPU state is to be restore to
"the vCPU state to be restored to" ?
>> + * @host_pc: the host PC the fault occurred at
>> + * @data: output data
>> + *
>> + * Attempt to load the the unwind state for a host pc occurring in
>> + * translated code. If the searched_pc is not in translated code,
>> + * the function returns false; otherwise @data is loaded.
>> + * This is the same unwind info as given to restore_state_to_opc.
>> + */
>> +bool cpu_unwind_state_data(CPUState *cpu, uintptr_t host_pc, uint64_t *data);
>> +
>> /**
>> * cpu_restore_state:
>> * @cpu: the vCPU state is to be restore to
>> diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
>> index e4386b3198..c772e3769c 100644
>> --- a/accel/tcg/translate-all.c
>> +++ b/accel/tcg/translate-all.c
>> @@ -320,29 +320,20 @@ static int encode_search(TranslationBlock *tb, uint8_t *block)
>> return p - block;
>> }
>>
>> -/* The cpu state corresponding to 'searched_pc' is restored.
>> - * When reset_icount is true, current TB will be interrupted and
>> - * icount should be recalculated.
>> - */
>> -static int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb,
>> - uintptr_t searched_pc, bool reset_icount)
>> +static int cpu_unwind_data_from_tb(TranslationBlock *tb, uintptr_t host_pc,
>> + uint64_t *data)
>> {
>> - uint64_t data[TARGET_INSN_START_WORDS];
>> - uintptr_t host_pc = (uintptr_t)tb->tc.ptr;
>> + uintptr_t iter_pc = (uintptr_t)tb->tc.ptr;
>> const uint8_t *p = tb->tc.ptr + tb->tc.size;
>> int i, j, num_insns = tb->icount;
>> -#ifdef CONFIG_PROFILER
>> - TCGProfile *prof = &tcg_ctx->prof;
>> - int64_t ti = profile_getclock();
>> -#endif
>>
>> - searched_pc -= GETPC_ADJ;
>> + host_pc -= GETPC_ADJ;
>>
>> - if (searched_pc < host_pc) {
>> + if (host_pc < iter_pc) {
>> return -1;
>> }
>>
>> - memset(data, 0, sizeof(data));
>> + memset(data, 0, sizeof(uint64_t) * TARGET_INSN_START_WORDS);
>> if (!TARGET_TB_PCREL) {
>> data[0] = tb_pc(tb);
>> }
>
> It's not visible in this hunk, but what follows is:
>
> /* Reconstruct the stored insn data while looking for the point at
> which the end of the insn exceeds the searched_pc. */
>
> Should this comment be adapted, minimally with s,searched_pc,host_pc, ?
>
>
>> @@ -353,19 +344,40 @@ static int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb,
>> for (j = 0; j < TARGET_INSN_START_WORDS; ++j) {
>> data[j] += decode_sleb128(&p);
>> }
>> - host_pc += decode_sleb128(&p);
>> - if (host_pc > searched_pc) {
>> - goto found;
>> + iter_pc += decode_sleb128(&p);
>> + if (iter_pc > host_pc) {
>> + return num_insns - i;
>> }
>> }
>> return -1;
>> +}
>> +
>> +/*
>> + * The cpu state corresponding to 'host_pc' is restored.
>> + * When reset_icount is true, current TB will be interrupted and
>> + * icount should be recalculated.
>> + */
>> +static void cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb,
>> + uintptr_t host_pc, bool reset_icount)
>> +{
>> + uint64_t data[TARGET_INSN_START_WORDS];
>> +#ifdef CONFIG_PROFILER
>> + TCGProfile *prof = &tcg_ctx->prof;
>> + int64_t ti = profile_getclock();
>> +#endif
>> + int insns_left = cpu_unwind_data_from_tb(tb, host_pc, data);
>> +
>> + if (insns_left < 0) {
>> + return;
>> + }
>
> Is the -1 return value some error condition to do anything about, log, tcg assert, or ...,
> under some DEBUG_* condition, or ignored as done here?
>
> Thanks,
>
> Claudio
>
>>
>> - found:
>> if (reset_icount && (tb_cflags(tb) & CF_USE_ICOUNT)) {
>> assert(icount_enabled());
>> - /* Reset the cycle counter to the start of the block
>> - and shift if to the number of actually executed instructions */
>> - cpu_neg(cpu)->icount_decr.u16.low += num_insns - i;
>> + /*
>> + * Reset the cycle counter to the start of the block and
>> + * shift if to the number of actually executed instructions.
>> + */
>> + cpu_neg(cpu)->icount_decr.u16.low += insns_left;
>> }
>>
>> cpu->cc->tcg_ops->restore_state_to_opc(cpu, tb, data);
>> @@ -375,7 +387,6 @@ static int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb,
>> prof->restore_time + profile_getclock() - ti);
>> qatomic_set(&prof->restore_count, prof->restore_count + 1);
>> #endif
>> - return 0;
>> }
>>
>> bool cpu_restore_state(CPUState *cpu, uintptr_t host_pc, bool will_exit)
>> @@ -408,6 +419,17 @@ bool cpu_restore_state(CPUState *cpu, uintptr_t host_pc, bool will_exit)
>> return false;
>> }
>>
>> +bool cpu_unwind_state_data(CPUState *cpu, uintptr_t host_pc, uint64_t *data)
>> +{
>> + if (in_code_gen_buffer((const void *)(host_pc - tcg_splitwx_diff))) {
>> + TranslationBlock *tb = tcg_tb_lookup(host_pc);
>> + if (tb) {
>> + return cpu_unwind_data_from_tb(tb, host_pc, data) >= 0;
>> + }
>> + }
>> + return false;
>> +}
>> +
>> void page_init(void)
>> {
>> page_size_init();
>
^ permalink raw reply [flat|nested] 64+ messages in thread* Re: [PATCH 24/29] accel/tcg: Introduce cpu_unwind_state_data
2022-10-25 9:23 ` Claudio Fontana
2022-10-25 9:32 ` Claudio Fontana
@ 2022-10-25 23:08 ` Richard Henderson
1 sibling, 0 replies; 64+ messages in thread
From: Richard Henderson @ 2022-10-25 23:08 UTC (permalink / raw)
To: Claudio Fontana, qemu-devel
On 10/25/22 19:23, Claudio Fontana wrote:
>> +/*
>> + * The cpu state corresponding to 'host_pc' is restored.
>> + * When reset_icount is true, current TB will be interrupted and
>> + * icount should be recalculated.
>> + */
>> +static void cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb,
>> + uintptr_t host_pc, bool reset_icount)
>> +{
>> + uint64_t data[TARGET_INSN_START_WORDS];
>> +#ifdef CONFIG_PROFILER
>> + TCGProfile *prof = &tcg_ctx->prof;
>> + int64_t ti = profile_getclock();
>> +#endif
>> + int insns_left = cpu_unwind_data_from_tb(tb, host_pc, data);
>> +
>> + if (insns_left < 0) {
>> + return;
>> + }
>
> Is the -1 return value some error condition to do anything about, log, tcg assert, or ...,
> under some DEBUG_* condition, or ignored as done here?
Interesting question.
By presenting this tb, have we asserted that host_pc is within (otherwise, why select this
tb). But if we didn't find host_pc within the unwind data... that suggests that the tcg
backend code generation may be wrong, generating an exception at an unexpected point.
But for the purposes of this patch, it is no change in behaviour. Previously we returned
from the function without goto found.
r~
^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH 25/29] target/i386: Use cpu_unwind_state_data for tpr access
2022-10-24 13:24 [PATCH 00/29] tcg: Fix x86 TARGET_TB_PCREL (#1269) Richard Henderson
` (24 preceding siblings ...)
2022-10-24 13:24 ` [PATCH 24/29] accel/tcg: Introduce cpu_unwind_state_data Richard Henderson
@ 2022-10-24 13:24 ` Richard Henderson
2022-10-24 13:24 ` [PATCH 26/29] target/openrisc: Always exit after mtspr npc Richard Henderson
` (3 subsequent siblings)
29 siblings, 0 replies; 64+ messages in thread
From: Richard Henderson @ 2022-10-24 13:24 UTC (permalink / raw)
To: qemu-devel
Avoid cpu_restore_state, and modifying env->eip out from
underneath the translator with TARGET_TB_PCREL. There is
some slight duplication from x86_restore_state_to_opc,
but it's just a few lines.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1269
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/i386/helper.c | 21 +++++++++++++++++++--
1 file changed, 19 insertions(+), 2 deletions(-)
diff --git a/target/i386/helper.c b/target/i386/helper.c
index b62a1e48e2..2cd1756f1a 100644
--- a/target/i386/helper.c
+++ b/target/i386/helper.c
@@ -509,6 +509,23 @@ void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank,
}
}
+static target_ulong get_memio_eip(CPUX86State *env)
+{
+ uint64_t data[TARGET_INSN_START_WORDS];
+ CPUState *cs = env_cpu(env);
+
+ if (!cpu_unwind_state_data(cs, cs->mem_io_pc, data)) {
+ return env->eip;
+ }
+
+ /* Per x86_restore_state_to_opc. */
+ if (TARGET_TB_PCREL) {
+ return (env->eip & TARGET_PAGE_MASK) | data[0];
+ } else {
+ return data[0] - env->segs[R_CS].base;
+ }
+}
+
void cpu_report_tpr_access(CPUX86State *env, TPRAccess access)
{
X86CPU *cpu = env_archcpu(env);
@@ -519,9 +536,9 @@ void cpu_report_tpr_access(CPUX86State *env, TPRAccess access)
cpu_interrupt(cs, CPU_INTERRUPT_TPR);
} else if (tcg_enabled()) {
- cpu_restore_state(cs, cs->mem_io_pc, false);
+ target_ulong eip = get_memio_eip(env);
- apic_handle_tpr_access_report(cpu->apic_state, env->eip, access);
+ apic_handle_tpr_access_report(cpu->apic_state, eip, access);
}
}
#endif /* !CONFIG_USER_ONLY */
--
2.34.1
^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 26/29] target/openrisc: Always exit after mtspr npc
2022-10-24 13:24 [PATCH 00/29] tcg: Fix x86 TARGET_TB_PCREL (#1269) Richard Henderson
` (25 preceding siblings ...)
2022-10-24 13:24 ` [PATCH 25/29] target/i386: Use cpu_unwind_state_data for tpr access Richard Henderson
@ 2022-10-24 13:24 ` Richard Henderson
2022-10-25 15:39 ` Philippe Mathieu-Daudé
2022-10-24 13:24 ` [PATCH 27/29] target/openrisc: Use cpu_unwind_state_data for mfspr Richard Henderson
` (2 subsequent siblings)
29 siblings, 1 reply; 64+ messages in thread
From: Richard Henderson @ 2022-10-24 13:24 UTC (permalink / raw)
To: qemu-devel
We have called cpu_restore_state asserting will_exit.
Do not go back on that promise. This affects icount.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/openrisc/sys_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c
index 09b3c97d7c..a3508e421d 100644
--- a/target/openrisc/sys_helper.c
+++ b/target/openrisc/sys_helper.c
@@ -51,8 +51,8 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb)
if (env->pc != rb) {
env->pc = rb;
env->dflag = 0;
- cpu_loop_exit(cs);
}
+ cpu_loop_exit(cs);
break;
case TO_SPR(0, 17): /* SR */
--
2.34.1
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH 26/29] target/openrisc: Always exit after mtspr npc
2022-10-24 13:24 ` [PATCH 26/29] target/openrisc: Always exit after mtspr npc Richard Henderson
@ 2022-10-25 15:39 ` Philippe Mathieu-Daudé
2022-10-25 15:49 ` Richard Henderson
0 siblings, 1 reply; 64+ messages in thread
From: Philippe Mathieu-Daudé @ 2022-10-25 15:39 UTC (permalink / raw)
To: Richard Henderson, Stafford Horne; +Cc: qemu-devel
On 24/10/22 15:24, Richard Henderson wrote:
> We have called cpu_restore_state asserting will_exit.
> Do not go back on that promise. This affects icount.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/openrisc/sys_helper.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c
> index 09b3c97d7c..a3508e421d 100644
> --- a/target/openrisc/sys_helper.c
> +++ b/target/openrisc/sys_helper.c
> @@ -51,8 +51,8 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb)
Extending the diff context from commit 24c328521b ("Tidy ppc/npc
implementation"):
cpu_restore_state(cs, GETPC(), true);
/* ??? Mirror or1ksim in not trashing delayed branch state
when "jumping" to the current instruction. */
> if (env->pc != rb) {
> env->pc = rb;
> env->dflag = 0;
> - cpu_loop_exit(cs);
> }
> + cpu_loop_exit(cs);
Is the comment still relevant?
> break;
>
> case TO_SPR(0, 17): /* SR */
^ permalink raw reply [flat|nested] 64+ messages in thread* Re: [PATCH 26/29] target/openrisc: Always exit after mtspr npc
2022-10-25 15:39 ` Philippe Mathieu-Daudé
@ 2022-10-25 15:49 ` Richard Henderson
0 siblings, 0 replies; 64+ messages in thread
From: Richard Henderson @ 2022-10-25 15:49 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, Stafford Horne; +Cc: qemu-devel
On 10/26/22 01:39, Philippe Mathieu-Daudé wrote:
> On 24/10/22 15:24, Richard Henderson wrote:
>> We have called cpu_restore_state asserting will_exit.
>> Do not go back on that promise. This affects icount.
>>
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>> target/openrisc/sys_helper.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c
>> index 09b3c97d7c..a3508e421d 100644
>> --- a/target/openrisc/sys_helper.c
>> +++ b/target/openrisc/sys_helper.c
>> @@ -51,8 +51,8 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr,
>> target_ulong rb)
>
> Extending the diff context from commit 24c328521b ("Tidy ppc/npc implementation"):
>
> cpu_restore_state(cs, GETPC(), true);
> /* ??? Mirror or1ksim in not trashing delayed branch state
> when "jumping" to the current instruction. */
>
>> if (env->pc != rb) {
>> env->pc = rb;
>> env->dflag = 0;
>> - cpu_loop_exit(cs);
>> }
>> + cpu_loop_exit(cs);
>
> Is the comment still relevant?
Yes, in that when pc == rb we don't clear dflag.
The only change here is exiting to the main loop before starting the next insn.
r~
^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH 27/29] target/openrisc: Use cpu_unwind_state_data for mfspr
2022-10-24 13:24 [PATCH 00/29] tcg: Fix x86 TARGET_TB_PCREL (#1269) Richard Henderson
` (26 preceding siblings ...)
2022-10-24 13:24 ` [PATCH 26/29] target/openrisc: Always exit after mtspr npc Richard Henderson
@ 2022-10-24 13:24 ` Richard Henderson
2022-10-24 13:24 ` [PATCH 28/29] accel/tcg: Remove will_exit argument from cpu_restore_state Richard Henderson
2022-10-24 13:24 ` [PATCH 29/29] accel/tcg: Remove reset_icount argument from cpu_restore_state_from_tb Richard Henderson
29 siblings, 0 replies; 64+ messages in thread
From: Richard Henderson @ 2022-10-24 13:24 UTC (permalink / raw)
To: qemu-devel
Since we do not plan to exit, use cpu_unwind_state_data
and extract exactly the data requested.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/openrisc/sys_helper.c | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c
index a3508e421d..dde2fa1623 100644
--- a/target/openrisc/sys_helper.c
+++ b/target/openrisc/sys_helper.c
@@ -199,6 +199,7 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd,
target_ulong spr)
{
#ifndef CONFIG_USER_ONLY
+ uint64_t data[TARGET_INSN_START_WORDS];
MachineState *ms = MACHINE(qdev_get_machine());
OpenRISCCPU *cpu = env_archcpu(env);
CPUState *cs = env_cpu(env);
@@ -232,14 +233,20 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd,
return env->evbar;
case TO_SPR(0, 16): /* NPC (equals PC) */
- cpu_restore_state(cs, GETPC(), false);
+ if (cpu_unwind_state_data(cs, GETPC(), data)) {
+ return data[0];
+ }
return env->pc;
case TO_SPR(0, 17): /* SR */
return cpu_get_sr(env);
case TO_SPR(0, 18): /* PPC */
- cpu_restore_state(cs, GETPC(), false);
+ if (cpu_unwind_state_data(cs, GETPC(), data)) {
+ if (data[1] & 2) {
+ return data[0] - 4;
+ }
+ }
return env->ppc;
case TO_SPR(0, 32): /* EPCR */
--
2.34.1
^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 28/29] accel/tcg: Remove will_exit argument from cpu_restore_state
2022-10-24 13:24 [PATCH 00/29] tcg: Fix x86 TARGET_TB_PCREL (#1269) Richard Henderson
` (27 preceding siblings ...)
2022-10-24 13:24 ` [PATCH 27/29] target/openrisc: Use cpu_unwind_state_data for mfspr Richard Henderson
@ 2022-10-24 13:24 ` Richard Henderson
2022-10-25 13:00 ` Claudio Fontana
2022-10-24 13:24 ` [PATCH 29/29] accel/tcg: Remove reset_icount argument from cpu_restore_state_from_tb Richard Henderson
29 siblings, 1 reply; 64+ messages in thread
From: Richard Henderson @ 2022-10-24 13:24 UTC (permalink / raw)
To: qemu-devel
The value passed is always true, and if the target's
synchronize_from_tb hook is non-trivial, not exiting
may be erroneous.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/exec-all.h | 9 ++++-----
accel/tcg/cpu-exec-common.c | 2 +-
accel/tcg/translate-all.c | 12 ++----------
target/alpha/helper.c | 2 +-
target/alpha/mem_helper.c | 2 +-
target/arm/op_helper.c | 2 +-
target/arm/tlb_helper.c | 8 ++++----
target/cris/helper.c | 2 +-
target/i386/tcg/sysemu/svm_helper.c | 2 +-
target/m68k/op_helper.c | 4 ++--
target/microblaze/helper.c | 2 +-
target/nios2/op_helper.c | 2 +-
target/openrisc/sys_helper.c | 4 ++--
target/ppc/excp_helper.c | 2 +-
target/s390x/tcg/excp_helper.c | 2 +-
target/tricore/op_helper.c | 2 +-
target/xtensa/helper.c | 6 +++---
17 files changed, 28 insertions(+), 37 deletions(-)
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index d49cf113dd..4078f4ceec 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -56,16 +56,15 @@ bool cpu_unwind_state_data(CPUState *cpu, uintptr_t host_pc, uint64_t *data);
* cpu_restore_state:
* @cpu: the vCPU state is to be restore to
* @searched_pc: the host PC the fault occurred at
- * @will_exit: true if the TB executed will be interrupted after some
- cpu adjustments. Required for maintaining the correct
- icount valus
* @return: true if state was restored, false otherwise
*
* Attempt to restore the state for a fault occurring in translated
* code. If the searched_pc is not in translated code no state is
- * restored and the function returns false.
+ * restored and the function returns false. After calling this function,
+ * we must return to the main loop -- required for maintaining the
+ * correct icount values.
*/
-bool cpu_restore_state(CPUState *cpu, uintptr_t searched_pc, bool will_exit);
+bool cpu_restore_state(CPUState *cpu, uintptr_t searched_pc);
G_NORETURN void cpu_loop_exit_noexc(CPUState *cpu);
G_NORETURN void cpu_loop_exit(CPUState *cpu);
diff --git a/accel/tcg/cpu-exec-common.c b/accel/tcg/cpu-exec-common.c
index be6fe45aa5..c7bc8c6efa 100644
--- a/accel/tcg/cpu-exec-common.c
+++ b/accel/tcg/cpu-exec-common.c
@@ -71,7 +71,7 @@ void cpu_loop_exit(CPUState *cpu)
void cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc)
{
if (pc) {
- cpu_restore_state(cpu, pc, true);
+ cpu_restore_state(cpu, pc);
}
cpu_loop_exit(cpu);
}
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index c772e3769c..dd439b5e3c 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -389,16 +389,8 @@ static void cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb,
#endif
}
-bool cpu_restore_state(CPUState *cpu, uintptr_t host_pc, bool will_exit)
+bool cpu_restore_state(CPUState *cpu, uintptr_t host_pc)
{
- /*
- * The pc update associated with restore without exit will
- * break the relative pc adjustments performed by TARGET_TB_PCREL.
- */
- if (TARGET_TB_PCREL) {
- assert(will_exit);
- }
-
/*
* The host_pc has to be in the rx region of the code buffer.
* If it is not we will not be able to resolve it here.
@@ -412,7 +404,7 @@ bool cpu_restore_state(CPUState *cpu, uintptr_t host_pc, bool will_exit)
if (in_code_gen_buffer((const void *)(host_pc - tcg_splitwx_diff))) {
TranslationBlock *tb = tcg_tb_lookup(host_pc);
if (tb) {
- cpu_restore_state_from_tb(cpu, tb, host_pc, will_exit);
+ cpu_restore_state_from_tb(cpu, tb, host_pc, true);
return true;
}
}
diff --git a/target/alpha/helper.c b/target/alpha/helper.c
index a5a389b5a3..970c869771 100644
--- a/target/alpha/helper.c
+++ b/target/alpha/helper.c
@@ -532,7 +532,7 @@ G_NORETURN void dynamic_excp(CPUAlphaState *env, uintptr_t retaddr,
cs->exception_index = excp;
env->error_code = error;
if (retaddr) {
- cpu_restore_state(cs, retaddr, true);
+ cpu_restore_state(cs, retaddr);
/* Floating-point exceptions (our only users) point to the next PC. */
env->pc += 4;
}
diff --git a/target/alpha/mem_helper.c b/target/alpha/mem_helper.c
index 47283a0612..a39b52c5dd 100644
--- a/target/alpha/mem_helper.c
+++ b/target/alpha/mem_helper.c
@@ -28,7 +28,7 @@ static void do_unaligned_access(CPUAlphaState *env, vaddr addr, uintptr_t retadd
uint64_t pc;
uint32_t insn;
- cpu_restore_state(env_cpu(env), retaddr, true);
+ cpu_restore_state(env_cpu(env), retaddr);
pc = env->pc;
insn = cpu_ldl_code(env, pc);
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
index c5bde1cfcc..70672bcd9f 100644
--- a/target/arm/op_helper.c
+++ b/target/arm/op_helper.c
@@ -78,7 +78,7 @@ void raise_exception_ra(CPUARMState *env, uint32_t excp, uint32_t syndrome,
* we must restore CPU state here before setting the syndrome
* the caller passed us, and cannot use cpu_loop_exit_restore().
*/
- cpu_restore_state(cs, ra, true);
+ cpu_restore_state(cs, ra);
raise_exception(env, excp, syndrome, target_el);
}
diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c
index 69b0dc69df..0f4f4fc809 100644
--- a/target/arm/tlb_helper.c
+++ b/target/arm/tlb_helper.c
@@ -156,7 +156,7 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
ARMMMUFaultInfo fi = {};
/* now we have a real cpu fault */
- cpu_restore_state(cs, retaddr, true);
+ cpu_restore_state(cs, retaddr);
fi.type = ARMFault_Alignment;
arm_deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi);
@@ -196,7 +196,7 @@ void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
ARMMMUFaultInfo fi = {};
/* now we have a real cpu fault */
- cpu_restore_state(cs, retaddr, true);
+ cpu_restore_state(cs, retaddr);
fi.ea = arm_extabort_type(response);
fi.type = ARMFault_SyncExternal;
@@ -252,7 +252,7 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
return false;
} else {
/* now we have a real cpu fault */
- cpu_restore_state(cs, retaddr, true);
+ cpu_restore_state(cs, retaddr);
arm_deliver_fault(cpu, address, access_type, mmu_idx, fi);
}
}
@@ -271,7 +271,7 @@ void arm_cpu_record_sigsegv(CPUState *cs, vaddr addr,
* We report both ESR and FAR to signal handlers.
* For now, it's easiest to deliver the fault normally.
*/
- cpu_restore_state(cs, ra, true);
+ cpu_restore_state(cs, ra);
arm_deliver_fault(cpu, addr, access_type, MMU_USER_IDX, &fi);
}
diff --git a/target/cris/helper.c b/target/cris/helper.c
index 91e4aeb178..81a72699b5 100644
--- a/target/cris/helper.c
+++ b/target/cris/helper.c
@@ -87,7 +87,7 @@ bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
cs->exception_index = EXCP_BUSFAULT;
env->fault_vector = res.bf_vec;
if (retaddr) {
- if (cpu_restore_state(cs, retaddr, true)) {
+ if (cpu_restore_state(cs, retaddr)) {
/* Evaluate flags after retranslation. */
helper_top_evaluate_flags(env);
}
diff --git a/target/i386/tcg/sysemu/svm_helper.c b/target/i386/tcg/sysemu/svm_helper.c
index 8e88567399..2d27731b60 100644
--- a/target/i386/tcg/sysemu/svm_helper.c
+++ b/target/i386/tcg/sysemu/svm_helper.c
@@ -704,7 +704,7 @@ void cpu_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1,
{
CPUState *cs = env_cpu(env);
- cpu_restore_state(cs, retaddr, true);
+ cpu_restore_state(cs, retaddr);
qemu_log_mask(CPU_LOG_TB_IN_ASM, "vmexit(%08x, %016" PRIx64 ", %016"
PRIx64 ", " TARGET_FMT_lx ")!\n",
diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c
index 5da176d642..1ce850bbc5 100644
--- a/target/m68k/op_helper.c
+++ b/target/m68k/op_helper.c
@@ -460,7 +460,7 @@ void m68k_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
M68kCPU *cpu = M68K_CPU(cs);
CPUM68KState *env = &cpu->env;
- cpu_restore_state(cs, retaddr, true);
+ cpu_restore_state(cs, retaddr);
if (m68k_feature(env, M68K_FEATURE_M68040)) {
env->mmu.mmusr = 0;
@@ -558,7 +558,7 @@ raise_exception_format2(CPUM68KState *env, int tt, int ilen, uintptr_t raddr)
cs->exception_index = tt;
/* Recover PC and CC_OP for the beginning of the insn. */
- cpu_restore_state(cs, raddr, true);
+ cpu_restore_state(cs, raddr);
/* Flags are current in env->cc_*, or are undefined. */
env->cc_op = CC_OP_FLAGS;
diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c
index a607fe68e5..98bdb82de8 100644
--- a/target/microblaze/helper.c
+++ b/target/microblaze/helper.c
@@ -277,7 +277,7 @@ void mb_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
uint32_t esr, iflags;
/* Recover the pc and iflags from the corresponding insn_start. */
- cpu_restore_state(cs, retaddr, true);
+ cpu_restore_state(cs, retaddr);
iflags = cpu->env.iflags;
qemu_log_mask(CPU_LOG_INT,
diff --git a/target/nios2/op_helper.c b/target/nios2/op_helper.c
index 2e30d0a908..0aaf33ffc2 100644
--- a/target/nios2/op_helper.c
+++ b/target/nios2/op_helper.c
@@ -40,7 +40,7 @@ void nios2_cpu_loop_exit_advance(CPUNios2State *env, uintptr_t retaddr)
* Do this here, rather than in restore_state_to_opc(),
* lest we affect QEMU internal exceptions, like EXCP_DEBUG.
*/
- cpu_restore_state(cs, retaddr, true);
+ cpu_restore_state(cs, retaddr);
env->pc += 4;
cpu_loop_exit(cs);
}
diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c
index dde2fa1623..ec145960e3 100644
--- a/target/openrisc/sys_helper.c
+++ b/target/openrisc/sys_helper.c
@@ -45,7 +45,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb)
break;
case TO_SPR(0, 16): /* NPC */
- cpu_restore_state(cs, GETPC(), true);
+ cpu_restore_state(cs, GETPC());
/* ??? Mirror or1ksim in not trashing delayed branch state
when "jumping" to the current instruction. */
if (env->pc != rb) {
@@ -131,7 +131,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb)
case TO_SPR(8, 0): /* PMR */
env->pmr = rb;
if (env->pmr & PMR_DME || env->pmr & PMR_SME) {
- cpu_restore_state(cs, GETPC(), true);
+ cpu_restore_state(cs, GETPC());
env->pc += 4;
cs->halted = 1;
raise_exception(cpu, EXCP_HALTED);
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 43f2480e94..3ded309265 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -2414,7 +2414,7 @@ void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
uint32_t insn;
/* Restore state and reload the insn we executed, for filling in DSISR. */
- cpu_restore_state(cs, retaddr, true);
+ cpu_restore_state(cs, retaddr);
insn = cpu_ldl_code(env, env->nip);
switch (env->mmu_model) {
diff --git a/target/s390x/tcg/excp_helper.c b/target/s390x/tcg/excp_helper.c
index 29ccf70df1..2cd6d062b9 100644
--- a/target/s390x/tcg/excp_helper.c
+++ b/target/s390x/tcg/excp_helper.c
@@ -39,7 +39,7 @@ G_NORETURN void tcg_s390_program_interrupt(CPUS390XState *env,
{
CPUState *cs = env_cpu(env);
- cpu_restore_state(cs, ra, true);
+ cpu_restore_state(cs, ra);
qemu_log_mask(CPU_LOG_INT, "program interrupt at %#" PRIx64 "\n",
env->psw.addr);
trigger_pgm_exception(env, code);
diff --git a/target/tricore/op_helper.c b/target/tricore/op_helper.c
index a79c838a92..532ae6b74c 100644
--- a/target/tricore/op_helper.c
+++ b/target/tricore/op_helper.c
@@ -31,7 +31,7 @@ void raise_exception_sync_internal(CPUTriCoreState *env, uint32_t class, int tin
{
CPUState *cs = env_cpu(env);
/* in case we come from a helper-call we need to restore the PC */
- cpu_restore_state(cs, pc, true);
+ cpu_restore_state(cs, pc);
/* Tin is loaded into d[15] */
env->gpr_d[15] = tin;
diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c
index e0a9caab4b..2aa9777a8e 100644
--- a/target/xtensa/helper.c
+++ b/target/xtensa/helper.c
@@ -253,7 +253,7 @@ void xtensa_cpu_do_unaligned_access(CPUState *cs,
assert(xtensa_option_enabled(env->config,
XTENSA_OPTION_UNALIGNED_EXCEPTION));
- cpu_restore_state(CPU(cpu), retaddr, true);
+ cpu_restore_state(CPU(cpu), retaddr);
HELPER(exception_cause_vaddr)(env,
env->pc, LOAD_STORE_ALIGNMENT_CAUSE,
addr);
@@ -284,7 +284,7 @@ bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
} else if (probe) {
return false;
} else {
- cpu_restore_state(cs, retaddr, true);
+ cpu_restore_state(cs, retaddr);
HELPER(exception_cause_vaddr)(env, env->pc, ret, address);
}
}
@@ -297,7 +297,7 @@ void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
XtensaCPU *cpu = XTENSA_CPU(cs);
CPUXtensaState *env = &cpu->env;
- cpu_restore_state(cs, retaddr, true);
+ cpu_restore_state(cs, retaddr);
HELPER(exception_cause_vaddr)(env, env->pc,
access_type == MMU_INST_FETCH ?
INSTR_PIF_ADDR_ERROR_CAUSE :
--
2.34.1
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH 28/29] accel/tcg: Remove will_exit argument from cpu_restore_state
2022-10-24 13:24 ` [PATCH 28/29] accel/tcg: Remove will_exit argument from cpu_restore_state Richard Henderson
@ 2022-10-25 13:00 ` Claudio Fontana
0 siblings, 0 replies; 64+ messages in thread
From: Claudio Fontana @ 2022-10-25 13:00 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
On 10/24/22 15:24, Richard Henderson wrote:
> The value passed is always true, and if the target's
> synchronize_from_tb hook is non-trivial, not exiting
> may be erroneous.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Claudio Fontana <cfontana@suse.de>
> ---
> include/exec/exec-all.h | 9 ++++-----
> accel/tcg/cpu-exec-common.c | 2 +-
> accel/tcg/translate-all.c | 12 ++----------
> target/alpha/helper.c | 2 +-
> target/alpha/mem_helper.c | 2 +-
> target/arm/op_helper.c | 2 +-
> target/arm/tlb_helper.c | 8 ++++----
> target/cris/helper.c | 2 +-
> target/i386/tcg/sysemu/svm_helper.c | 2 +-
> target/m68k/op_helper.c | 4 ++--
> target/microblaze/helper.c | 2 +-
> target/nios2/op_helper.c | 2 +-
> target/openrisc/sys_helper.c | 4 ++--
> target/ppc/excp_helper.c | 2 +-
> target/s390x/tcg/excp_helper.c | 2 +-
> target/tricore/op_helper.c | 2 +-
> target/xtensa/helper.c | 6 +++---
> 17 files changed, 28 insertions(+), 37 deletions(-)
>
> diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
> index d49cf113dd..4078f4ceec 100644
> --- a/include/exec/exec-all.h
> +++ b/include/exec/exec-all.h
> @@ -56,16 +56,15 @@ bool cpu_unwind_state_data(CPUState *cpu, uintptr_t host_pc, uint64_t *data);
> * cpu_restore_state:
> * @cpu: the vCPU state is to be restore to
> * @searched_pc: the host PC the fault occurred at
> - * @will_exit: true if the TB executed will be interrupted after some
> - cpu adjustments. Required for maintaining the correct
> - icount valus
> * @return: true if state was restored, false otherwise
> *
> * Attempt to restore the state for a fault occurring in translated
> * code. If the searched_pc is not in translated code no state is
> - * restored and the function returns false.
> + * restored and the function returns false. After calling this function,
> + * we must return to the main loop -- required for maintaining the
> + * correct icount values.
> */
> -bool cpu_restore_state(CPUState *cpu, uintptr_t searched_pc, bool will_exit);
> +bool cpu_restore_state(CPUState *cpu, uintptr_t searched_pc);
>
> G_NORETURN void cpu_loop_exit_noexc(CPUState *cpu);
> G_NORETURN void cpu_loop_exit(CPUState *cpu);
> diff --git a/accel/tcg/cpu-exec-common.c b/accel/tcg/cpu-exec-common.c
> index be6fe45aa5..c7bc8c6efa 100644
> --- a/accel/tcg/cpu-exec-common.c
> +++ b/accel/tcg/cpu-exec-common.c
> @@ -71,7 +71,7 @@ void cpu_loop_exit(CPUState *cpu)
> void cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc)
> {
> if (pc) {
> - cpu_restore_state(cpu, pc, true);
> + cpu_restore_state(cpu, pc);
> }
> cpu_loop_exit(cpu);
> }
> diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
> index c772e3769c..dd439b5e3c 100644
> --- a/accel/tcg/translate-all.c
> +++ b/accel/tcg/translate-all.c
> @@ -389,16 +389,8 @@ static void cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb,
> #endif
> }
>
> -bool cpu_restore_state(CPUState *cpu, uintptr_t host_pc, bool will_exit)
> +bool cpu_restore_state(CPUState *cpu, uintptr_t host_pc)
> {
> - /*
> - * The pc update associated with restore without exit will
> - * break the relative pc adjustments performed by TARGET_TB_PCREL.
> - */
> - if (TARGET_TB_PCREL) {
> - assert(will_exit);
> - }
> -
> /*
> * The host_pc has to be in the rx region of the code buffer.
> * If it is not we will not be able to resolve it here.
> @@ -412,7 +404,7 @@ bool cpu_restore_state(CPUState *cpu, uintptr_t host_pc, bool will_exit)
> if (in_code_gen_buffer((const void *)(host_pc - tcg_splitwx_diff))) {
> TranslationBlock *tb = tcg_tb_lookup(host_pc);
> if (tb) {
> - cpu_restore_state_from_tb(cpu, tb, host_pc, will_exit);
> + cpu_restore_state_from_tb(cpu, tb, host_pc, true);
> return true;
> }
> }
> diff --git a/target/alpha/helper.c b/target/alpha/helper.c
> index a5a389b5a3..970c869771 100644
> --- a/target/alpha/helper.c
> +++ b/target/alpha/helper.c
> @@ -532,7 +532,7 @@ G_NORETURN void dynamic_excp(CPUAlphaState *env, uintptr_t retaddr,
> cs->exception_index = excp;
> env->error_code = error;
> if (retaddr) {
> - cpu_restore_state(cs, retaddr, true);
> + cpu_restore_state(cs, retaddr);
> /* Floating-point exceptions (our only users) point to the next PC. */
> env->pc += 4;
> }
> diff --git a/target/alpha/mem_helper.c b/target/alpha/mem_helper.c
> index 47283a0612..a39b52c5dd 100644
> --- a/target/alpha/mem_helper.c
> +++ b/target/alpha/mem_helper.c
> @@ -28,7 +28,7 @@ static void do_unaligned_access(CPUAlphaState *env, vaddr addr, uintptr_t retadd
> uint64_t pc;
> uint32_t insn;
>
> - cpu_restore_state(env_cpu(env), retaddr, true);
> + cpu_restore_state(env_cpu(env), retaddr);
>
> pc = env->pc;
> insn = cpu_ldl_code(env, pc);
> diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
> index c5bde1cfcc..70672bcd9f 100644
> --- a/target/arm/op_helper.c
> +++ b/target/arm/op_helper.c
> @@ -78,7 +78,7 @@ void raise_exception_ra(CPUARMState *env, uint32_t excp, uint32_t syndrome,
> * we must restore CPU state here before setting the syndrome
> * the caller passed us, and cannot use cpu_loop_exit_restore().
> */
> - cpu_restore_state(cs, ra, true);
> + cpu_restore_state(cs, ra);
> raise_exception(env, excp, syndrome, target_el);
> }
>
> diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c
> index 69b0dc69df..0f4f4fc809 100644
> --- a/target/arm/tlb_helper.c
> +++ b/target/arm/tlb_helper.c
> @@ -156,7 +156,7 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
> ARMMMUFaultInfo fi = {};
>
> /* now we have a real cpu fault */
> - cpu_restore_state(cs, retaddr, true);
> + cpu_restore_state(cs, retaddr);
>
> fi.type = ARMFault_Alignment;
> arm_deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi);
> @@ -196,7 +196,7 @@ void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
> ARMMMUFaultInfo fi = {};
>
> /* now we have a real cpu fault */
> - cpu_restore_state(cs, retaddr, true);
> + cpu_restore_state(cs, retaddr);
>
> fi.ea = arm_extabort_type(response);
> fi.type = ARMFault_SyncExternal;
> @@ -252,7 +252,7 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
> return false;
> } else {
> /* now we have a real cpu fault */
> - cpu_restore_state(cs, retaddr, true);
> + cpu_restore_state(cs, retaddr);
> arm_deliver_fault(cpu, address, access_type, mmu_idx, fi);
> }
> }
> @@ -271,7 +271,7 @@ void arm_cpu_record_sigsegv(CPUState *cs, vaddr addr,
> * We report both ESR and FAR to signal handlers.
> * For now, it's easiest to deliver the fault normally.
> */
> - cpu_restore_state(cs, ra, true);
> + cpu_restore_state(cs, ra);
> arm_deliver_fault(cpu, addr, access_type, MMU_USER_IDX, &fi);
> }
>
> diff --git a/target/cris/helper.c b/target/cris/helper.c
> index 91e4aeb178..81a72699b5 100644
> --- a/target/cris/helper.c
> +++ b/target/cris/helper.c
> @@ -87,7 +87,7 @@ bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
> cs->exception_index = EXCP_BUSFAULT;
> env->fault_vector = res.bf_vec;
> if (retaddr) {
> - if (cpu_restore_state(cs, retaddr, true)) {
> + if (cpu_restore_state(cs, retaddr)) {
> /* Evaluate flags after retranslation. */
> helper_top_evaluate_flags(env);
> }
> diff --git a/target/i386/tcg/sysemu/svm_helper.c b/target/i386/tcg/sysemu/svm_helper.c
> index 8e88567399..2d27731b60 100644
> --- a/target/i386/tcg/sysemu/svm_helper.c
> +++ b/target/i386/tcg/sysemu/svm_helper.c
> @@ -704,7 +704,7 @@ void cpu_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1,
> {
> CPUState *cs = env_cpu(env);
>
> - cpu_restore_state(cs, retaddr, true);
> + cpu_restore_state(cs, retaddr);
>
> qemu_log_mask(CPU_LOG_TB_IN_ASM, "vmexit(%08x, %016" PRIx64 ", %016"
> PRIx64 ", " TARGET_FMT_lx ")!\n",
> diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c
> index 5da176d642..1ce850bbc5 100644
> --- a/target/m68k/op_helper.c
> +++ b/target/m68k/op_helper.c
> @@ -460,7 +460,7 @@ void m68k_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
> M68kCPU *cpu = M68K_CPU(cs);
> CPUM68KState *env = &cpu->env;
>
> - cpu_restore_state(cs, retaddr, true);
> + cpu_restore_state(cs, retaddr);
>
> if (m68k_feature(env, M68K_FEATURE_M68040)) {
> env->mmu.mmusr = 0;
> @@ -558,7 +558,7 @@ raise_exception_format2(CPUM68KState *env, int tt, int ilen, uintptr_t raddr)
> cs->exception_index = tt;
>
> /* Recover PC and CC_OP for the beginning of the insn. */
> - cpu_restore_state(cs, raddr, true);
> + cpu_restore_state(cs, raddr);
>
> /* Flags are current in env->cc_*, or are undefined. */
> env->cc_op = CC_OP_FLAGS;
> diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c
> index a607fe68e5..98bdb82de8 100644
> --- a/target/microblaze/helper.c
> +++ b/target/microblaze/helper.c
> @@ -277,7 +277,7 @@ void mb_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
> uint32_t esr, iflags;
>
> /* Recover the pc and iflags from the corresponding insn_start. */
> - cpu_restore_state(cs, retaddr, true);
> + cpu_restore_state(cs, retaddr);
> iflags = cpu->env.iflags;
>
> qemu_log_mask(CPU_LOG_INT,
> diff --git a/target/nios2/op_helper.c b/target/nios2/op_helper.c
> index 2e30d0a908..0aaf33ffc2 100644
> --- a/target/nios2/op_helper.c
> +++ b/target/nios2/op_helper.c
> @@ -40,7 +40,7 @@ void nios2_cpu_loop_exit_advance(CPUNios2State *env, uintptr_t retaddr)
> * Do this here, rather than in restore_state_to_opc(),
> * lest we affect QEMU internal exceptions, like EXCP_DEBUG.
> */
> - cpu_restore_state(cs, retaddr, true);
> + cpu_restore_state(cs, retaddr);
> env->pc += 4;
> cpu_loop_exit(cs);
> }
> diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c
> index dde2fa1623..ec145960e3 100644
> --- a/target/openrisc/sys_helper.c
> +++ b/target/openrisc/sys_helper.c
> @@ -45,7 +45,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb)
> break;
>
> case TO_SPR(0, 16): /* NPC */
> - cpu_restore_state(cs, GETPC(), true);
> + cpu_restore_state(cs, GETPC());
> /* ??? Mirror or1ksim in not trashing delayed branch state
> when "jumping" to the current instruction. */
> if (env->pc != rb) {
> @@ -131,7 +131,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb)
> case TO_SPR(8, 0): /* PMR */
> env->pmr = rb;
> if (env->pmr & PMR_DME || env->pmr & PMR_SME) {
> - cpu_restore_state(cs, GETPC(), true);
> + cpu_restore_state(cs, GETPC());
> env->pc += 4;
> cs->halted = 1;
> raise_exception(cpu, EXCP_HALTED);
> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
> index 43f2480e94..3ded309265 100644
> --- a/target/ppc/excp_helper.c
> +++ b/target/ppc/excp_helper.c
> @@ -2414,7 +2414,7 @@ void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
> uint32_t insn;
>
> /* Restore state and reload the insn we executed, for filling in DSISR. */
> - cpu_restore_state(cs, retaddr, true);
> + cpu_restore_state(cs, retaddr);
> insn = cpu_ldl_code(env, env->nip);
>
> switch (env->mmu_model) {
> diff --git a/target/s390x/tcg/excp_helper.c b/target/s390x/tcg/excp_helper.c
> index 29ccf70df1..2cd6d062b9 100644
> --- a/target/s390x/tcg/excp_helper.c
> +++ b/target/s390x/tcg/excp_helper.c
> @@ -39,7 +39,7 @@ G_NORETURN void tcg_s390_program_interrupt(CPUS390XState *env,
> {
> CPUState *cs = env_cpu(env);
>
> - cpu_restore_state(cs, ra, true);
> + cpu_restore_state(cs, ra);
> qemu_log_mask(CPU_LOG_INT, "program interrupt at %#" PRIx64 "\n",
> env->psw.addr);
> trigger_pgm_exception(env, code);
> diff --git a/target/tricore/op_helper.c b/target/tricore/op_helper.c
> index a79c838a92..532ae6b74c 100644
> --- a/target/tricore/op_helper.c
> +++ b/target/tricore/op_helper.c
> @@ -31,7 +31,7 @@ void raise_exception_sync_internal(CPUTriCoreState *env, uint32_t class, int tin
> {
> CPUState *cs = env_cpu(env);
> /* in case we come from a helper-call we need to restore the PC */
> - cpu_restore_state(cs, pc, true);
> + cpu_restore_state(cs, pc);
>
> /* Tin is loaded into d[15] */
> env->gpr_d[15] = tin;
> diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c
> index e0a9caab4b..2aa9777a8e 100644
> --- a/target/xtensa/helper.c
> +++ b/target/xtensa/helper.c
> @@ -253,7 +253,7 @@ void xtensa_cpu_do_unaligned_access(CPUState *cs,
>
> assert(xtensa_option_enabled(env->config,
> XTENSA_OPTION_UNALIGNED_EXCEPTION));
> - cpu_restore_state(CPU(cpu), retaddr, true);
> + cpu_restore_state(CPU(cpu), retaddr);
> HELPER(exception_cause_vaddr)(env,
> env->pc, LOAD_STORE_ALIGNMENT_CAUSE,
> addr);
> @@ -284,7 +284,7 @@ bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
> } else if (probe) {
> return false;
> } else {
> - cpu_restore_state(cs, retaddr, true);
> + cpu_restore_state(cs, retaddr);
> HELPER(exception_cause_vaddr)(env, env->pc, ret, address);
> }
> }
> @@ -297,7 +297,7 @@ void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
> XtensaCPU *cpu = XTENSA_CPU(cs);
> CPUXtensaState *env = &cpu->env;
>
> - cpu_restore_state(cs, retaddr, true);
> + cpu_restore_state(cs, retaddr);
> HELPER(exception_cause_vaddr)(env, env->pc,
> access_type == MMU_INST_FETCH ?
> INSTR_PIF_ADDR_ERROR_CAUSE :
^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH 29/29] accel/tcg: Remove reset_icount argument from cpu_restore_state_from_tb
2022-10-24 13:24 [PATCH 00/29] tcg: Fix x86 TARGET_TB_PCREL (#1269) Richard Henderson
` (28 preceding siblings ...)
2022-10-24 13:24 ` [PATCH 28/29] accel/tcg: Remove will_exit argument from cpu_restore_state Richard Henderson
@ 2022-10-24 13:24 ` Richard Henderson
2022-10-25 13:09 ` Claudio Fontana
29 siblings, 1 reply; 64+ messages in thread
From: Richard Henderson @ 2022-10-24 13:24 UTC (permalink / raw)
To: qemu-devel
The value passed is always true.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/translate-all.c | 19 +++++++++----------
1 file changed, 9 insertions(+), 10 deletions(-)
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index dd439b5e3c..9e7dd41795 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -353,12 +353,11 @@ static int cpu_unwind_data_from_tb(TranslationBlock *tb, uintptr_t host_pc,
}
/*
- * The cpu state corresponding to 'host_pc' is restored.
- * When reset_icount is true, current TB will be interrupted and
- * icount should be recalculated.
+ * The cpu state corresponding to 'host_pc' is restored in
+ * preparation for exiting the TB.
*/
static void cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb,
- uintptr_t host_pc, bool reset_icount)
+ uintptr_t host_pc)
{
uint64_t data[TARGET_INSN_START_WORDS];
#ifdef CONFIG_PROFILER
@@ -371,7 +370,7 @@ static void cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb,
return;
}
- if (reset_icount && (tb_cflags(tb) & CF_USE_ICOUNT)) {
+ if (tb_cflags(tb) & CF_USE_ICOUNT) {
assert(icount_enabled());
/*
* Reset the cycle counter to the start of the block and
@@ -404,7 +403,7 @@ bool cpu_restore_state(CPUState *cpu, uintptr_t host_pc)
if (in_code_gen_buffer((const void *)(host_pc - tcg_splitwx_diff))) {
TranslationBlock *tb = tcg_tb_lookup(host_pc);
if (tb) {
- cpu_restore_state_from_tb(cpu, tb, host_pc, true);
+ cpu_restore_state_from_tb(cpu, tb, host_pc);
return true;
}
}
@@ -1715,7 +1714,7 @@ tb_invalidate_phys_page_range__locked(struct page_collection *pages,
* restore the CPU state.
*/
current_tb_modified = true;
- cpu_restore_state_from_tb(cpu, current_tb, retaddr, true);
+ cpu_restore_state_from_tb(cpu, current_tb, retaddr);
cpu_get_tb_cpu_state(env, ¤t_pc, ¤t_cs_base,
¤t_flags);
}
@@ -1874,7 +1873,7 @@ static bool tb_invalidate_phys_page(tb_page_addr_t addr, uintptr_t pc)
restore the CPU state */
current_tb_modified = 1;
- cpu_restore_state_from_tb(cpu, current_tb, pc, true);
+ cpu_restore_state_from_tb(cpu, current_tb, pc);
cpu_get_tb_cpu_state(env, ¤t_pc, ¤t_cs_base,
¤t_flags);
}
@@ -1904,7 +1903,7 @@ void tb_check_watchpoint(CPUState *cpu, uintptr_t retaddr)
tb = tcg_tb_lookup(retaddr);
if (tb) {
/* We can use retranslation to find the PC. */
- cpu_restore_state_from_tb(cpu, tb, retaddr, true);
+ cpu_restore_state_from_tb(cpu, tb, retaddr);
tb_phys_invalidate(tb, -1);
} else {
/* The exception probably happened in a helper. The CPU state should
@@ -1940,7 +1939,7 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr)
cpu_abort(cpu, "cpu_io_recompile: could not find TB for pc=%p",
(void *)retaddr);
}
- cpu_restore_state_from_tb(cpu, tb, retaddr, true);
+ cpu_restore_state_from_tb(cpu, tb, retaddr);
/*
* Some guests must re-execute the branch when re-executing a delay
--
2.34.1
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH 29/29] accel/tcg: Remove reset_icount argument from cpu_restore_state_from_tb
2022-10-24 13:24 ` [PATCH 29/29] accel/tcg: Remove reset_icount argument from cpu_restore_state_from_tb Richard Henderson
@ 2022-10-25 13:09 ` Claudio Fontana
0 siblings, 0 replies; 64+ messages in thread
From: Claudio Fontana @ 2022-10-25 13:09 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
On 10/24/22 15:24, Richard Henderson wrote:
> The value passed is always true.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Claudio Fontana <cfontana@suse.de>
> ---
> accel/tcg/translate-all.c | 19 +++++++++----------
> 1 file changed, 9 insertions(+), 10 deletions(-)
>
> diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
> index dd439b5e3c..9e7dd41795 100644
> --- a/accel/tcg/translate-all.c
> +++ b/accel/tcg/translate-all.c
> @@ -353,12 +353,11 @@ static int cpu_unwind_data_from_tb(TranslationBlock *tb, uintptr_t host_pc,
> }
>
> /*
> - * The cpu state corresponding to 'host_pc' is restored.
> - * When reset_icount is true, current TB will be interrupted and
> - * icount should be recalculated.
> + * The cpu state corresponding to 'host_pc' is restored in
> + * preparation for exiting the TB.
> */
> static void cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb,
> - uintptr_t host_pc, bool reset_icount)
> + uintptr_t host_pc)
> {
> uint64_t data[TARGET_INSN_START_WORDS];
> #ifdef CONFIG_PROFILER
> @@ -371,7 +370,7 @@ static void cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb,
> return;
> }
>
> - if (reset_icount && (tb_cflags(tb) & CF_USE_ICOUNT)) {
> + if (tb_cflags(tb) & CF_USE_ICOUNT) {
> assert(icount_enabled());
> /*
> * Reset the cycle counter to the start of the block and
> @@ -404,7 +403,7 @@ bool cpu_restore_state(CPUState *cpu, uintptr_t host_pc)
> if (in_code_gen_buffer((const void *)(host_pc - tcg_splitwx_diff))) {
> TranslationBlock *tb = tcg_tb_lookup(host_pc);
> if (tb) {
> - cpu_restore_state_from_tb(cpu, tb, host_pc, true);
> + cpu_restore_state_from_tb(cpu, tb, host_pc);
> return true;
> }
> }
> @@ -1715,7 +1714,7 @@ tb_invalidate_phys_page_range__locked(struct page_collection *pages,
> * restore the CPU state.
> */
> current_tb_modified = true;
> - cpu_restore_state_from_tb(cpu, current_tb, retaddr, true);
> + cpu_restore_state_from_tb(cpu, current_tb, retaddr);
> cpu_get_tb_cpu_state(env, ¤t_pc, ¤t_cs_base,
> ¤t_flags);
> }
> @@ -1874,7 +1873,7 @@ static bool tb_invalidate_phys_page(tb_page_addr_t addr, uintptr_t pc)
> restore the CPU state */
>
> current_tb_modified = 1;
> - cpu_restore_state_from_tb(cpu, current_tb, pc, true);
> + cpu_restore_state_from_tb(cpu, current_tb, pc);
> cpu_get_tb_cpu_state(env, ¤t_pc, ¤t_cs_base,
> ¤t_flags);
> }
> @@ -1904,7 +1903,7 @@ void tb_check_watchpoint(CPUState *cpu, uintptr_t retaddr)
> tb = tcg_tb_lookup(retaddr);
> if (tb) {
> /* We can use retranslation to find the PC. */
> - cpu_restore_state_from_tb(cpu, tb, retaddr, true);
> + cpu_restore_state_from_tb(cpu, tb, retaddr);
> tb_phys_invalidate(tb, -1);
> } else {
> /* The exception probably happened in a helper. The CPU state should
> @@ -1940,7 +1939,7 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr)
> cpu_abort(cpu, "cpu_io_recompile: could not find TB for pc=%p",
> (void *)retaddr);
> }
> - cpu_restore_state_from_tb(cpu, tb, retaddr, true);
> + cpu_restore_state_from_tb(cpu, tb, retaddr);
>
> /*
> * Some guests must re-execute the branch when re-executing a delay
^ permalink raw reply [flat|nested] 64+ messages in thread