* [PULL v2 01/78] vdpa: Use iovec for vhost_vdpa_net_cvq_add()
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
@ 2023-10-19 18:21 ` Michael S. Tsirkin
2023-10-19 18:21 ` [PULL v2 02/78] vdpa: Avoid using vhost_vdpa_net_load_*() outside vhost_vdpa_net_load() Michael S. Tsirkin
` (77 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:21 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Hawkins Jiawei, Eugenio Pérez, Jason Wang
From: Hawkins Jiawei <yin31149@gmail.com>
Next patches in this series will no longer perform an
immediate poll and check of the device's used buffers
for each CVQ state load command. Consequently, there
will be multiple pending buffers in the shadow VirtQueue,
making it a must for every control command to have its
own buffer.
To achieve this, this patch refactor vhost_vdpa_net_cvq_add()
to accept `struct iovec`, which eliminates the coupling of
control commands to `s->cvq_cmd_out_buffer` and `s->status`,
allowing them to use their own buffer.
Signed-off-by: Hawkins Jiawei <yin31149@gmail.com>
Acked-by: Eugenio Pérez <eperezma@redhat.com>
Message-Id: <8a328f146fb043f34edb75ba6d043d2d6de88f99.1697165821.git.yin31149@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
net/vhost-vdpa.c | 39 ++++++++++++++++++++++-----------------
1 file changed, 22 insertions(+), 17 deletions(-)
diff --git a/net/vhost-vdpa.c b/net/vhost-vdpa.c
index 939c984d5b..618758596a 100644
--- a/net/vhost-vdpa.c
+++ b/net/vhost-vdpa.c
@@ -618,22 +618,14 @@ static void vhost_vdpa_net_cvq_stop(NetClientState *nc)
vhost_vdpa_net_client_stop(nc);
}
-static ssize_t vhost_vdpa_net_cvq_add(VhostVDPAState *s, size_t out_len,
- size_t in_len)
+static ssize_t vhost_vdpa_net_cvq_add(VhostVDPAState *s,
+ const struct iovec *out_sg, size_t out_num,
+ const struct iovec *in_sg, size_t in_num)
{
- /* Buffers for the device */
- const struct iovec out = {
- .iov_base = s->cvq_cmd_out_buffer,
- .iov_len = out_len,
- };
- const struct iovec in = {
- .iov_base = s->status,
- .iov_len = sizeof(virtio_net_ctrl_ack),
- };
VhostShadowVirtqueue *svq = g_ptr_array_index(s->vhost_vdpa.shadow_vqs, 0);
int r;
- r = vhost_svq_add(svq, &out, 1, &in, 1, NULL);
+ r = vhost_svq_add(svq, out_sg, out_num, in_sg, in_num, NULL);
if (unlikely(r != 0)) {
if (unlikely(r == -ENOSPC)) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: No space on device queue\n",
@@ -659,6 +651,15 @@ static ssize_t vhost_vdpa_net_load_cmd(VhostVDPAState *s, uint8_t class,
.cmd = cmd,
};
size_t data_size = iov_size(data_sg, data_num);
+ /* Buffers for the device */
+ const struct iovec out = {
+ .iov_base = s->cvq_cmd_out_buffer,
+ .iov_len = sizeof(ctrl) + data_size,
+ };
+ const struct iovec in = {
+ .iov_base = s->status,
+ .iov_len = sizeof(*s->status),
+ };
assert(data_size < vhost_vdpa_net_cvq_cmd_page_len() - sizeof(ctrl));
@@ -669,8 +670,7 @@ static ssize_t vhost_vdpa_net_load_cmd(VhostVDPAState *s, uint8_t class,
iov_to_buf(data_sg, data_num, 0,
s->cvq_cmd_out_buffer + sizeof(ctrl), data_size);
- return vhost_vdpa_net_cvq_add(s, data_size + sizeof(ctrl),
- sizeof(virtio_net_ctrl_ack));
+ return vhost_vdpa_net_cvq_add(s, &out, 1, &in, 1);
}
static int vhost_vdpa_net_load_mac(VhostVDPAState *s, const VirtIONet *n)
@@ -1248,10 +1248,15 @@ static int vhost_vdpa_net_handle_ctrl_avail(VhostShadowVirtqueue *svq,
.iov_base = s->cvq_cmd_out_buffer,
};
/* in buffer used for device model */
- const struct iovec in = {
+ const struct iovec model_in = {
.iov_base = &status,
.iov_len = sizeof(status),
};
+ /* in buffer used for vdpa device */
+ const struct iovec vdpa_in = {
+ .iov_base = s->status,
+ .iov_len = sizeof(*s->status),
+ };
ssize_t dev_written = -EINVAL;
out.iov_len = iov_to_buf(elem->out_sg, elem->out_num, 0,
@@ -1285,7 +1290,7 @@ static int vhost_vdpa_net_handle_ctrl_avail(VhostShadowVirtqueue *svq,
goto out;
}
} else {
- dev_written = vhost_vdpa_net_cvq_add(s, out.iov_len, sizeof(status));
+ dev_written = vhost_vdpa_net_cvq_add(s, &out, 1, &vdpa_in, 1);
if (unlikely(dev_written < 0)) {
goto out;
}
@@ -1301,7 +1306,7 @@ static int vhost_vdpa_net_handle_ctrl_avail(VhostShadowVirtqueue *svq,
}
status = VIRTIO_NET_ERR;
- virtio_net_handle_ctrl_iov(svq->vdev, &in, 1, &out, 1);
+ virtio_net_handle_ctrl_iov(svq->vdev, &model_in, 1, &out, 1);
if (status != VIRTIO_NET_OK) {
error_report("Bad CVQ processing in model");
}
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 02/78] vdpa: Avoid using vhost_vdpa_net_load_*() outside vhost_vdpa_net_load()
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
2023-10-19 18:21 ` [PULL v2 01/78] vdpa: Use iovec for vhost_vdpa_net_cvq_add() Michael S. Tsirkin
@ 2023-10-19 18:21 ` Michael S. Tsirkin
2023-10-19 18:21 ` [PULL v2 03/78] vdpa: Check device ack in vhost_vdpa_net_load_rx_mode() Michael S. Tsirkin
` (76 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:21 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Hawkins Jiawei, Eugenio Pérez, Jason Wang
From: Hawkins Jiawei <yin31149@gmail.com>
Next patches in this series will refactor vhost_vdpa_net_load_cmd()
to iterate through the control commands shadow buffers, allowing QEMU
to send CVQ state load commands in parallel at device startup.
Considering that QEMU always forwards the CVQ command serialized
outside of vhost_vdpa_net_load(), it is more elegant to send the
CVQ commands directly without invoking vhost_vdpa_net_load_*() helpers.
Signed-off-by: Hawkins Jiawei <yin31149@gmail.com>
Acked-by: Eugenio Pérez <eperezma@redhat.com>
Message-Id: <254f0618efde7af7229ba4fdada667bb9d318991.1697165821.git.yin31149@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
net/vhost-vdpa.c | 14 +++++++++++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/net/vhost-vdpa.c b/net/vhost-vdpa.c
index 618758596a..86b8d31244 100644
--- a/net/vhost-vdpa.c
+++ b/net/vhost-vdpa.c
@@ -1114,12 +1114,14 @@ static NetClientInfo net_vhost_vdpa_cvq_info = {
*/
static int vhost_vdpa_net_excessive_mac_filter_cvq_add(VhostVDPAState *s,
VirtQueueElement *elem,
- struct iovec *out)
+ struct iovec *out,
+ const struct iovec *in)
{
struct virtio_net_ctrl_mac mac_data, *mac_ptr;
struct virtio_net_ctrl_hdr *hdr_ptr;
uint32_t cursor;
ssize_t r;
+ uint8_t on = 1;
/* parse the non-multicast MAC address entries from CVQ command */
cursor = sizeof(*hdr_ptr);
@@ -1167,7 +1169,13 @@ static int vhost_vdpa_net_excessive_mac_filter_cvq_add(VhostVDPAState *s,
* filter table to the vdpa device, it should send the
* VIRTIO_NET_CTRL_RX_PROMISC CVQ command to enable promiscuous mode
*/
- r = vhost_vdpa_net_load_rx_mode(s, VIRTIO_NET_CTRL_RX_PROMISC, 1);
+ hdr_ptr = out->iov_base;
+ out->iov_len = sizeof(*hdr_ptr) + sizeof(on);
+
+ hdr_ptr->class = VIRTIO_NET_CTRL_RX;
+ hdr_ptr->cmd = VIRTIO_NET_CTRL_RX_PROMISC;
+ iov_from_buf(out, 1, sizeof(*hdr_ptr), &on, sizeof(on));
+ r = vhost_vdpa_net_cvq_add(s, out, 1, in, 1);
if (unlikely(r < 0)) {
return r;
}
@@ -1285,7 +1293,7 @@ static int vhost_vdpa_net_handle_ctrl_avail(VhostShadowVirtqueue *svq,
* the CVQ command directly.
*/
dev_written = vhost_vdpa_net_excessive_mac_filter_cvq_add(s, elem,
- &out);
+ &out, &vdpa_in);
if (unlikely(dev_written < 0)) {
goto out;
}
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 03/78] vdpa: Check device ack in vhost_vdpa_net_load_rx_mode()
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
2023-10-19 18:21 ` [PULL v2 01/78] vdpa: Use iovec for vhost_vdpa_net_cvq_add() Michael S. Tsirkin
2023-10-19 18:21 ` [PULL v2 02/78] vdpa: Avoid using vhost_vdpa_net_load_*() outside vhost_vdpa_net_load() Michael S. Tsirkin
@ 2023-10-19 18:21 ` Michael S. Tsirkin
2023-10-19 18:21 ` [PULL v2 04/78] vdpa: Move vhost_svq_poll() to the caller of vhost_vdpa_net_cvq_add() Michael S. Tsirkin
` (75 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:21 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Hawkins Jiawei, Eugenio Pérez, Jason Wang
From: Hawkins Jiawei <yin31149@gmail.com>
Considering that vhost_vdpa_net_load_rx_mode() is only called
within vhost_vdpa_net_load_rx() now, this patch refactors
vhost_vdpa_net_load_rx_mode() to include a check for the
device's ack, simplifying the code and improving its maintainability.
Signed-off-by: Hawkins Jiawei <yin31149@gmail.com>
Acked-by: Eugenio Pérez <eperezma@redhat.com>
Message-Id: <68811d52f96ae12d68f0d67d996ac1642a623943.1697165821.git.yin31149@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
net/vhost-vdpa.c | 76 ++++++++++++++++++++----------------------------
1 file changed, 31 insertions(+), 45 deletions(-)
diff --git a/net/vhost-vdpa.c b/net/vhost-vdpa.c
index 86b8d31244..36a4e57c0d 100644
--- a/net/vhost-vdpa.c
+++ b/net/vhost-vdpa.c
@@ -827,14 +827,24 @@ static int vhost_vdpa_net_load_rx_mode(VhostVDPAState *s,
.iov_base = &on,
.iov_len = sizeof(on),
};
- return vhost_vdpa_net_load_cmd(s, VIRTIO_NET_CTRL_RX,
- cmd, &data, 1);
+ ssize_t dev_written;
+
+ dev_written = vhost_vdpa_net_load_cmd(s, VIRTIO_NET_CTRL_RX,
+ cmd, &data, 1);
+ if (unlikely(dev_written < 0)) {
+ return dev_written;
+ }
+ if (*s->status != VIRTIO_NET_OK) {
+ return -EIO;
+ }
+
+ return 0;
}
static int vhost_vdpa_net_load_rx(VhostVDPAState *s,
const VirtIONet *n)
{
- ssize_t dev_written;
+ ssize_t r;
if (!virtio_vdev_has_feature(&n->parent_obj, VIRTIO_NET_F_CTRL_RX)) {
return 0;
@@ -859,13 +869,9 @@ static int vhost_vdpa_net_load_rx(VhostVDPAState *s,
* configuration only at live migration.
*/
if (!n->mac_table.uni_overflow && !n->promisc) {
- dev_written = vhost_vdpa_net_load_rx_mode(s,
- VIRTIO_NET_CTRL_RX_PROMISC, 0);
- if (unlikely(dev_written < 0)) {
- return dev_written;
- }
- if (*s->status != VIRTIO_NET_OK) {
- return -EIO;
+ r = vhost_vdpa_net_load_rx_mode(s, VIRTIO_NET_CTRL_RX_PROMISC, 0);
+ if (unlikely(r < 0)) {
+ return r;
}
}
@@ -887,13 +893,9 @@ static int vhost_vdpa_net_load_rx(VhostVDPAState *s,
* configuration only at live migration.
*/
if (n->mac_table.multi_overflow || n->allmulti) {
- dev_written = vhost_vdpa_net_load_rx_mode(s,
- VIRTIO_NET_CTRL_RX_ALLMULTI, 1);
- if (unlikely(dev_written < 0)) {
- return dev_written;
- }
- if (*s->status != VIRTIO_NET_OK) {
- return -EIO;
+ r = vhost_vdpa_net_load_rx_mode(s, VIRTIO_NET_CTRL_RX_ALLMULTI, 1);
+ if (unlikely(r < 0)) {
+ return r;
}
}
@@ -912,13 +914,9 @@ static int vhost_vdpa_net_load_rx(VhostVDPAState *s,
* configuration only at live migration.
*/
if (n->alluni) {
- dev_written = vhost_vdpa_net_load_rx_mode(s,
- VIRTIO_NET_CTRL_RX_ALLUNI, 1);
- if (dev_written < 0) {
- return dev_written;
- }
- if (*s->status != VIRTIO_NET_OK) {
- return -EIO;
+ r = vhost_vdpa_net_load_rx_mode(s, VIRTIO_NET_CTRL_RX_ALLUNI, 1);
+ if (r < 0) {
+ return r;
}
}
@@ -933,13 +931,9 @@ static int vhost_vdpa_net_load_rx(VhostVDPAState *s,
* configuration only at live migration.
*/
if (n->nomulti) {
- dev_written = vhost_vdpa_net_load_rx_mode(s,
- VIRTIO_NET_CTRL_RX_NOMULTI, 1);
- if (dev_written < 0) {
- return dev_written;
- }
- if (*s->status != VIRTIO_NET_OK) {
- return -EIO;
+ r = vhost_vdpa_net_load_rx_mode(s, VIRTIO_NET_CTRL_RX_NOMULTI, 1);
+ if (r < 0) {
+ return r;
}
}
@@ -954,13 +948,9 @@ static int vhost_vdpa_net_load_rx(VhostVDPAState *s,
* configuration only at live migration.
*/
if (n->nouni) {
- dev_written = vhost_vdpa_net_load_rx_mode(s,
- VIRTIO_NET_CTRL_RX_NOUNI, 1);
- if (dev_written < 0) {
- return dev_written;
- }
- if (*s->status != VIRTIO_NET_OK) {
- return -EIO;
+ r = vhost_vdpa_net_load_rx_mode(s, VIRTIO_NET_CTRL_RX_NOUNI, 1);
+ if (r < 0) {
+ return r;
}
}
@@ -975,13 +965,9 @@ static int vhost_vdpa_net_load_rx(VhostVDPAState *s,
* configuration only at live migration.
*/
if (n->nobcast) {
- dev_written = vhost_vdpa_net_load_rx_mode(s,
- VIRTIO_NET_CTRL_RX_NOBCAST, 1);
- if (dev_written < 0) {
- return dev_written;
- }
- if (*s->status != VIRTIO_NET_OK) {
- return -EIO;
+ r = vhost_vdpa_net_load_rx_mode(s, VIRTIO_NET_CTRL_RX_NOBCAST, 1);
+ if (r < 0) {
+ return r;
}
}
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 04/78] vdpa: Move vhost_svq_poll() to the caller of vhost_vdpa_net_cvq_add()
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (2 preceding siblings ...)
2023-10-19 18:21 ` [PULL v2 03/78] vdpa: Check device ack in vhost_vdpa_net_load_rx_mode() Michael S. Tsirkin
@ 2023-10-19 18:21 ` Michael S. Tsirkin
2023-10-19 18:21 ` [PULL v2 05/78] vdpa: Introduce cursors to vhost_vdpa_net_loadx() Michael S. Tsirkin
` (74 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:21 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Hawkins Jiawei, Jason Wang
From: Hawkins Jiawei <yin31149@gmail.com>
This patch moves vhost_svq_poll() to the caller of
vhost_vdpa_net_cvq_add() and introduces a helper funtion.
By making this change, next patches in this series is
able to refactor vhost_vdpa_net_load_x() only to delay
the polling and checking process until either the SVQ
is full or control commands shadow buffers are full.
Signed-off-by: Hawkins Jiawei <yin31149@gmail.com>
Message-Id: <196cadb55175a75275660c6634a538289f027ae3.1697165821.git.yin31149@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
net/vhost-vdpa.c | 53 +++++++++++++++++++++++++++++++++++++++---------
1 file changed, 43 insertions(+), 10 deletions(-)
diff --git a/net/vhost-vdpa.c b/net/vhost-vdpa.c
index 36a4e57c0d..ea73e3c410 100644
--- a/net/vhost-vdpa.c
+++ b/net/vhost-vdpa.c
@@ -631,15 +631,21 @@ static ssize_t vhost_vdpa_net_cvq_add(VhostVDPAState *s,
qemu_log_mask(LOG_GUEST_ERROR, "%s: No space on device queue\n",
__func__);
}
- return r;
}
- /*
- * We can poll here since we've had BQL from the time we sent the
- * descriptor. Also, we need to take the answer before SVQ pulls by itself,
- * when BQL is released
- */
- return vhost_svq_poll(svq, 1);
+ return r;
+}
+
+/*
+ * Convenience wrapper to poll SVQ for multiple control commands.
+ *
+ * Caller should hold the BQL when invoking this function, and should take
+ * the answer before SVQ pulls by itself when BQL is released.
+ */
+static ssize_t vhost_vdpa_net_svq_poll(VhostVDPAState *s, size_t cmds_in_flight)
+{
+ VhostShadowVirtqueue *svq = g_ptr_array_index(s->vhost_vdpa.shadow_vqs, 0);
+ return vhost_svq_poll(svq, cmds_in_flight);
}
static ssize_t vhost_vdpa_net_load_cmd(VhostVDPAState *s, uint8_t class,
@@ -660,6 +666,7 @@ static ssize_t vhost_vdpa_net_load_cmd(VhostVDPAState *s, uint8_t class,
.iov_base = s->status,
.iov_len = sizeof(*s->status),
};
+ ssize_t r;
assert(data_size < vhost_vdpa_net_cvq_cmd_page_len() - sizeof(ctrl));
@@ -670,7 +677,16 @@ static ssize_t vhost_vdpa_net_load_cmd(VhostVDPAState *s, uint8_t class,
iov_to_buf(data_sg, data_num, 0,
s->cvq_cmd_out_buffer + sizeof(ctrl), data_size);
- return vhost_vdpa_net_cvq_add(s, &out, 1, &in, 1);
+ r = vhost_vdpa_net_cvq_add(s, &out, 1, &in, 1);
+ if (unlikely(r < 0)) {
+ return r;
+ }
+
+ /*
+ * We can poll here since we've had BQL from the time
+ * we sent the descriptor.
+ */
+ return vhost_vdpa_net_svq_poll(s, 1);
}
static int vhost_vdpa_net_load_mac(VhostVDPAState *s, const VirtIONet *n)
@@ -1165,6 +1181,15 @@ static int vhost_vdpa_net_excessive_mac_filter_cvq_add(VhostVDPAState *s,
if (unlikely(r < 0)) {
return r;
}
+
+ /*
+ * We can poll here since we've had BQL from the time
+ * we sent the descriptor.
+ */
+ r = vhost_vdpa_net_svq_poll(s, 1);
+ if (unlikely(r < sizeof(*s->status))) {
+ return r;
+ }
if (*s->status != VIRTIO_NET_OK) {
return sizeof(*s->status);
}
@@ -1284,10 +1309,18 @@ static int vhost_vdpa_net_handle_ctrl_avail(VhostShadowVirtqueue *svq,
goto out;
}
} else {
- dev_written = vhost_vdpa_net_cvq_add(s, &out, 1, &vdpa_in, 1);
- if (unlikely(dev_written < 0)) {
+ ssize_t r;
+ r = vhost_vdpa_net_cvq_add(s, &out, 1, &vdpa_in, 1);
+ if (unlikely(r < 0)) {
+ dev_written = r;
goto out;
}
+
+ /*
+ * We can poll here since we've had BQL from the time
+ * we sent the descriptor.
+ */
+ dev_written = vhost_vdpa_net_svq_poll(s, 1);
}
if (unlikely(dev_written < sizeof(status))) {
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 05/78] vdpa: Introduce cursors to vhost_vdpa_net_loadx()
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (3 preceding siblings ...)
2023-10-19 18:21 ` [PULL v2 04/78] vdpa: Move vhost_svq_poll() to the caller of vhost_vdpa_net_cvq_add() Michael S. Tsirkin
@ 2023-10-19 18:21 ` Michael S. Tsirkin
2023-10-19 18:21 ` [PULL v2 06/78] vhost: Expose vhost_svq_available_slots() Michael S. Tsirkin
` (73 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:21 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Hawkins Jiawei, Jason Wang
From: Hawkins Jiawei <yin31149@gmail.com>
This patch introduces two new arugments, `out_cursor`
and `in_cursor`, to vhost_vdpa_net_loadx(). Addtionally,
it includes a helper function
vhost_vdpa_net_load_cursor_reset() for resetting these
cursors.
Furthermore, this patch refactors vhost_vdpa_net_load_cmd()
so that vhost_vdpa_net_load_cmd() prepares buffers
for the device using the cursors arguments, instead
of directly accesses `s->cvq_cmd_out_buffer` and
`s->status` fields.
By making these change, next patches in this series
can refactor vhost_vdpa_net_load_cmd() directly to
iterate through the control commands shadow buffers,
allowing QEMU to send CVQ state load commands in parallel
at device startup.
Signed-off-by: Hawkins Jiawei <yin31149@gmail.com>
Message-Id: <1c6516e233a14cc222f0884e148e4e1adceda78d.1697165821.git.yin31149@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
net/vhost-vdpa.c | 111 ++++++++++++++++++++++++++++++++---------------
1 file changed, 75 insertions(+), 36 deletions(-)
diff --git a/net/vhost-vdpa.c b/net/vhost-vdpa.c
index ea73e3c410..ef4d242811 100644
--- a/net/vhost-vdpa.c
+++ b/net/vhost-vdpa.c
@@ -648,7 +648,22 @@ static ssize_t vhost_vdpa_net_svq_poll(VhostVDPAState *s, size_t cmds_in_flight)
return vhost_svq_poll(svq, cmds_in_flight);
}
-static ssize_t vhost_vdpa_net_load_cmd(VhostVDPAState *s, uint8_t class,
+static void vhost_vdpa_net_load_cursor_reset(VhostVDPAState *s,
+ struct iovec *out_cursor,
+ struct iovec *in_cursor)
+{
+ /* reset the cursor of the output buffer for the device */
+ out_cursor->iov_base = s->cvq_cmd_out_buffer;
+ out_cursor->iov_len = vhost_vdpa_net_cvq_cmd_page_len();
+
+ /* reset the cursor of the in buffer for the device */
+ in_cursor->iov_base = s->status;
+ in_cursor->iov_len = vhost_vdpa_net_cvq_cmd_page_len();
+}
+
+static ssize_t vhost_vdpa_net_load_cmd(VhostVDPAState *s,
+ struct iovec *out_cursor,
+ struct iovec *in_cursor, uint8_t class,
uint8_t cmd, const struct iovec *data_sg,
size_t data_num)
{
@@ -657,25 +672,21 @@ static ssize_t vhost_vdpa_net_load_cmd(VhostVDPAState *s, uint8_t class,
.cmd = cmd,
};
size_t data_size = iov_size(data_sg, data_num);
- /* Buffers for the device */
- const struct iovec out = {
- .iov_base = s->cvq_cmd_out_buffer,
- .iov_len = sizeof(ctrl) + data_size,
- };
- const struct iovec in = {
- .iov_base = s->status,
- .iov_len = sizeof(*s->status),
- };
+ struct iovec out, in;
ssize_t r;
assert(data_size < vhost_vdpa_net_cvq_cmd_page_len() - sizeof(ctrl));
/* pack the CVQ command header */
- memcpy(s->cvq_cmd_out_buffer, &ctrl, sizeof(ctrl));
-
+ iov_from_buf(out_cursor, 1, 0, &ctrl, sizeof(ctrl));
/* pack the CVQ command command-specific-data */
iov_to_buf(data_sg, data_num, 0,
- s->cvq_cmd_out_buffer + sizeof(ctrl), data_size);
+ out_cursor->iov_base + sizeof(ctrl), data_size);
+
+ /* extract the required buffer from the cursor for output */
+ iov_copy(&out, 1, out_cursor, 1, 0, sizeof(ctrl) + data_size);
+ /* extract the required buffer from the cursor for input */
+ iov_copy(&in, 1, in_cursor, 1, 0, sizeof(*s->status));
r = vhost_vdpa_net_cvq_add(s, &out, 1, &in, 1);
if (unlikely(r < 0)) {
@@ -689,14 +700,17 @@ static ssize_t vhost_vdpa_net_load_cmd(VhostVDPAState *s, uint8_t class,
return vhost_vdpa_net_svq_poll(s, 1);
}
-static int vhost_vdpa_net_load_mac(VhostVDPAState *s, const VirtIONet *n)
+static int vhost_vdpa_net_load_mac(VhostVDPAState *s, const VirtIONet *n,
+ struct iovec *out_cursor,
+ struct iovec *in_cursor)
{
if (virtio_vdev_has_feature(&n->parent_obj, VIRTIO_NET_F_CTRL_MAC_ADDR)) {
const struct iovec data = {
.iov_base = (void *)n->mac,
.iov_len = sizeof(n->mac),
};
- ssize_t dev_written = vhost_vdpa_net_load_cmd(s, VIRTIO_NET_CTRL_MAC,
+ ssize_t dev_written = vhost_vdpa_net_load_cmd(s, out_cursor, in_cursor,
+ VIRTIO_NET_CTRL_MAC,
VIRTIO_NET_CTRL_MAC_ADDR_SET,
&data, 1);
if (unlikely(dev_written < 0)) {
@@ -748,7 +762,7 @@ static int vhost_vdpa_net_load_mac(VhostVDPAState *s, const VirtIONet *n)
.iov_len = mul_macs_size,
},
};
- ssize_t dev_written = vhost_vdpa_net_load_cmd(s,
+ ssize_t dev_written = vhost_vdpa_net_load_cmd(s, out_cursor, in_cursor,
VIRTIO_NET_CTRL_MAC,
VIRTIO_NET_CTRL_MAC_TABLE_SET,
data, ARRAY_SIZE(data));
@@ -763,7 +777,9 @@ static int vhost_vdpa_net_load_mac(VhostVDPAState *s, const VirtIONet *n)
}
static int vhost_vdpa_net_load_mq(VhostVDPAState *s,
- const VirtIONet *n)
+ const VirtIONet *n,
+ struct iovec *out_cursor,
+ struct iovec *in_cursor)
{
struct virtio_net_ctrl_mq mq;
ssize_t dev_written;
@@ -777,7 +793,8 @@ static int vhost_vdpa_net_load_mq(VhostVDPAState *s,
.iov_base = &mq,
.iov_len = sizeof(mq),
};
- dev_written = vhost_vdpa_net_load_cmd(s, VIRTIO_NET_CTRL_MQ,
+ dev_written = vhost_vdpa_net_load_cmd(s, out_cursor, in_cursor,
+ VIRTIO_NET_CTRL_MQ,
VIRTIO_NET_CTRL_MQ_VQ_PAIRS_SET,
&data, 1);
if (unlikely(dev_written < 0)) {
@@ -791,7 +808,9 @@ static int vhost_vdpa_net_load_mq(VhostVDPAState *s,
}
static int vhost_vdpa_net_load_offloads(VhostVDPAState *s,
- const VirtIONet *n)
+ const VirtIONet *n,
+ struct iovec *out_cursor,
+ struct iovec *in_cursor)
{
uint64_t offloads;
ssize_t dev_written;
@@ -822,7 +841,8 @@ static int vhost_vdpa_net_load_offloads(VhostVDPAState *s,
.iov_base = &offloads,
.iov_len = sizeof(offloads),
};
- dev_written = vhost_vdpa_net_load_cmd(s, VIRTIO_NET_CTRL_GUEST_OFFLOADS,
+ dev_written = vhost_vdpa_net_load_cmd(s, out_cursor, in_cursor,
+ VIRTIO_NET_CTRL_GUEST_OFFLOADS,
VIRTIO_NET_CTRL_GUEST_OFFLOADS_SET,
&data, 1);
if (unlikely(dev_written < 0)) {
@@ -836,6 +856,8 @@ static int vhost_vdpa_net_load_offloads(VhostVDPAState *s,
}
static int vhost_vdpa_net_load_rx_mode(VhostVDPAState *s,
+ struct iovec *out_cursor,
+ struct iovec *in_cursor,
uint8_t cmd,
uint8_t on)
{
@@ -845,7 +867,8 @@ static int vhost_vdpa_net_load_rx_mode(VhostVDPAState *s,
};
ssize_t dev_written;
- dev_written = vhost_vdpa_net_load_cmd(s, VIRTIO_NET_CTRL_RX,
+ dev_written = vhost_vdpa_net_load_cmd(s, out_cursor, in_cursor,
+ VIRTIO_NET_CTRL_RX,
cmd, &data, 1);
if (unlikely(dev_written < 0)) {
return dev_written;
@@ -858,7 +881,9 @@ static int vhost_vdpa_net_load_rx_mode(VhostVDPAState *s,
}
static int vhost_vdpa_net_load_rx(VhostVDPAState *s,
- const VirtIONet *n)
+ const VirtIONet *n,
+ struct iovec *out_cursor,
+ struct iovec *in_cursor)
{
ssize_t r;
@@ -885,7 +910,8 @@ static int vhost_vdpa_net_load_rx(VhostVDPAState *s,
* configuration only at live migration.
*/
if (!n->mac_table.uni_overflow && !n->promisc) {
- r = vhost_vdpa_net_load_rx_mode(s, VIRTIO_NET_CTRL_RX_PROMISC, 0);
+ r = vhost_vdpa_net_load_rx_mode(s, out_cursor, in_cursor,
+ VIRTIO_NET_CTRL_RX_PROMISC, 0);
if (unlikely(r < 0)) {
return r;
}
@@ -909,7 +935,8 @@ static int vhost_vdpa_net_load_rx(VhostVDPAState *s,
* configuration only at live migration.
*/
if (n->mac_table.multi_overflow || n->allmulti) {
- r = vhost_vdpa_net_load_rx_mode(s, VIRTIO_NET_CTRL_RX_ALLMULTI, 1);
+ r = vhost_vdpa_net_load_rx_mode(s, out_cursor, in_cursor,
+ VIRTIO_NET_CTRL_RX_ALLMULTI, 1);
if (unlikely(r < 0)) {
return r;
}
@@ -930,7 +957,8 @@ static int vhost_vdpa_net_load_rx(VhostVDPAState *s,
* configuration only at live migration.
*/
if (n->alluni) {
- r = vhost_vdpa_net_load_rx_mode(s, VIRTIO_NET_CTRL_RX_ALLUNI, 1);
+ r = vhost_vdpa_net_load_rx_mode(s, out_cursor, in_cursor,
+ VIRTIO_NET_CTRL_RX_ALLUNI, 1);
if (r < 0) {
return r;
}
@@ -947,7 +975,8 @@ static int vhost_vdpa_net_load_rx(VhostVDPAState *s,
* configuration only at live migration.
*/
if (n->nomulti) {
- r = vhost_vdpa_net_load_rx_mode(s, VIRTIO_NET_CTRL_RX_NOMULTI, 1);
+ r = vhost_vdpa_net_load_rx_mode(s, out_cursor, in_cursor,
+ VIRTIO_NET_CTRL_RX_NOMULTI, 1);
if (r < 0) {
return r;
}
@@ -964,7 +993,8 @@ static int vhost_vdpa_net_load_rx(VhostVDPAState *s,
* configuration only at live migration.
*/
if (n->nouni) {
- r = vhost_vdpa_net_load_rx_mode(s, VIRTIO_NET_CTRL_RX_NOUNI, 1);
+ r = vhost_vdpa_net_load_rx_mode(s, out_cursor, in_cursor,
+ VIRTIO_NET_CTRL_RX_NOUNI, 1);
if (r < 0) {
return r;
}
@@ -981,7 +1011,8 @@ static int vhost_vdpa_net_load_rx(VhostVDPAState *s,
* configuration only at live migration.
*/
if (n->nobcast) {
- r = vhost_vdpa_net_load_rx_mode(s, VIRTIO_NET_CTRL_RX_NOBCAST, 1);
+ r = vhost_vdpa_net_load_rx_mode(s, out_cursor, in_cursor,
+ VIRTIO_NET_CTRL_RX_NOBCAST, 1);
if (r < 0) {
return r;
}
@@ -992,13 +1023,16 @@ static int vhost_vdpa_net_load_rx(VhostVDPAState *s,
static int vhost_vdpa_net_load_single_vlan(VhostVDPAState *s,
const VirtIONet *n,
+ struct iovec *out_cursor,
+ struct iovec *in_cursor,
uint16_t vid)
{
const struct iovec data = {
.iov_base = &vid,
.iov_len = sizeof(vid),
};
- ssize_t dev_written = vhost_vdpa_net_load_cmd(s, VIRTIO_NET_CTRL_VLAN,
+ ssize_t dev_written = vhost_vdpa_net_load_cmd(s, out_cursor, in_cursor,
+ VIRTIO_NET_CTRL_VLAN,
VIRTIO_NET_CTRL_VLAN_ADD,
&data, 1);
if (unlikely(dev_written < 0)) {
@@ -1012,7 +1046,9 @@ static int vhost_vdpa_net_load_single_vlan(VhostVDPAState *s,
}
static int vhost_vdpa_net_load_vlan(VhostVDPAState *s,
- const VirtIONet *n)
+ const VirtIONet *n,
+ struct iovec *out_cursor,
+ struct iovec *in_cursor)
{
int r;
@@ -1023,7 +1059,8 @@ static int vhost_vdpa_net_load_vlan(VhostVDPAState *s,
for (int i = 0; i < MAX_VLAN >> 5; i++) {
for (int j = 0; n->vlans[i] && j <= 0x1f; j++) {
if (n->vlans[i] & (1U << j)) {
- r = vhost_vdpa_net_load_single_vlan(s, n, (i << 5) + j);
+ r = vhost_vdpa_net_load_single_vlan(s, n, out_cursor,
+ in_cursor, (i << 5) + j);
if (unlikely(r != 0)) {
return r;
}
@@ -1040,6 +1077,7 @@ static int vhost_vdpa_net_cvq_load(NetClientState *nc)
struct vhost_vdpa *v = &s->vhost_vdpa;
const VirtIONet *n;
int r;
+ struct iovec out_cursor, in_cursor;
assert(nc->info->type == NET_CLIENT_DRIVER_VHOST_VDPA);
@@ -1047,23 +1085,24 @@ static int vhost_vdpa_net_cvq_load(NetClientState *nc)
if (v->shadow_vqs_enabled) {
n = VIRTIO_NET(v->dev->vdev);
- r = vhost_vdpa_net_load_mac(s, n);
+ vhost_vdpa_net_load_cursor_reset(s, &out_cursor, &in_cursor);
+ r = vhost_vdpa_net_load_mac(s, n, &out_cursor, &in_cursor);
if (unlikely(r < 0)) {
return r;
}
- r = vhost_vdpa_net_load_mq(s, n);
+ r = vhost_vdpa_net_load_mq(s, n, &out_cursor, &in_cursor);
if (unlikely(r)) {
return r;
}
- r = vhost_vdpa_net_load_offloads(s, n);
+ r = vhost_vdpa_net_load_offloads(s, n, &out_cursor, &in_cursor);
if (unlikely(r)) {
return r;
}
- r = vhost_vdpa_net_load_rx(s, n);
+ r = vhost_vdpa_net_load_rx(s, n, &out_cursor, &in_cursor);
if (unlikely(r)) {
return r;
}
- r = vhost_vdpa_net_load_vlan(s, n);
+ r = vhost_vdpa_net_load_vlan(s, n, &out_cursor, &in_cursor);
if (unlikely(r)) {
return r;
}
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 06/78] vhost: Expose vhost_svq_available_slots()
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (4 preceding siblings ...)
2023-10-19 18:21 ` [PULL v2 05/78] vdpa: Introduce cursors to vhost_vdpa_net_loadx() Michael S. Tsirkin
@ 2023-10-19 18:21 ` Michael S. Tsirkin
2023-10-19 18:21 ` [PULL v2 07/78] vdpa: Send cvq state load commands in parallel Michael S. Tsirkin
` (72 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:21 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Hawkins Jiawei, Eugenio Pérez
From: Hawkins Jiawei <yin31149@gmail.com>
Next patches in this series will delay the polling
and checking of buffers until either the SVQ is
full or control commands shadow buffers are full,
no longer perform an immediate poll and check of
the device's used buffers for each CVQ state load command.
To achieve this, this patch exposes
vhost_svq_available_slots(), allowing QEMU to know
whether the SVQ is full.
Signed-off-by: Hawkins Jiawei <yin31149@gmail.com>
Acked-by: Eugenio Pérez <eperezma@redhat.com>
Message-Id: <25938079f0bd8185fd664c64e205e629f7a966be.1697165821.git.yin31149@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/virtio/vhost-shadow-virtqueue.h | 1 +
hw/virtio/vhost-shadow-virtqueue.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/virtio/vhost-shadow-virtqueue.h b/hw/virtio/vhost-shadow-virtqueue.h
index 5bce67837b..19c842a15b 100644
--- a/hw/virtio/vhost-shadow-virtqueue.h
+++ b/hw/virtio/vhost-shadow-virtqueue.h
@@ -114,6 +114,7 @@ typedef struct VhostShadowVirtqueue {
bool vhost_svq_valid_features(uint64_t features, Error **errp);
+uint16_t vhost_svq_available_slots(const VhostShadowVirtqueue *svq);
void vhost_svq_push_elem(VhostShadowVirtqueue *svq,
const VirtQueueElement *elem, uint32_t len);
int vhost_svq_add(VhostShadowVirtqueue *svq, const struct iovec *out_sg,
diff --git a/hw/virtio/vhost-shadow-virtqueue.c b/hw/virtio/vhost-shadow-virtqueue.c
index e731b1d2ea..fc5f408f77 100644
--- a/hw/virtio/vhost-shadow-virtqueue.c
+++ b/hw/virtio/vhost-shadow-virtqueue.c
@@ -66,7 +66,7 @@ bool vhost_svq_valid_features(uint64_t features, Error **errp)
*
* @svq: The svq
*/
-static uint16_t vhost_svq_available_slots(const VhostShadowVirtqueue *svq)
+uint16_t vhost_svq_available_slots(const VhostShadowVirtqueue *svq)
{
return svq->num_free;
}
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 07/78] vdpa: Send cvq state load commands in parallel
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (5 preceding siblings ...)
2023-10-19 18:21 ` [PULL v2 06/78] vhost: Expose vhost_svq_available_slots() Michael S. Tsirkin
@ 2023-10-19 18:21 ` Michael S. Tsirkin
2023-10-19 18:21 ` [PULL v2 08/78] tests: test-smp-parse: Add the test for cores/threads per socket helpers Michael S. Tsirkin
` (71 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:21 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Hawkins Jiawei, Eugenio Pérez, Jason Wang
From: Hawkins Jiawei <yin31149@gmail.com>
This patch enables sending CVQ state load commands
in parallel at device startup by following steps:
* Refactor vhost_vdpa_net_load_cmd() to iterate through
the control commands shadow buffers. This allows different
CVQ state load commands to use their own unique buffers.
* Delay the polling and checking of buffers until either
the SVQ is full or control commands shadow buffers are full.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1578
Signed-off-by: Hawkins Jiawei <yin31149@gmail.com>
Acked-by: Eugenio Pérez <eperezma@redhat.com>
Message-Id: <9350f32278e39f7bce297b8f2d82dac27c6f8c9a.1697165821.git.yin31149@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
net/vhost-vdpa.c | 165 +++++++++++++++++++++++++++++------------------
1 file changed, 102 insertions(+), 63 deletions(-)
diff --git a/net/vhost-vdpa.c b/net/vhost-vdpa.c
index ef4d242811..4b7c3b81b8 100644
--- a/net/vhost-vdpa.c
+++ b/net/vhost-vdpa.c
@@ -661,6 +661,31 @@ static void vhost_vdpa_net_load_cursor_reset(VhostVDPAState *s,
in_cursor->iov_len = vhost_vdpa_net_cvq_cmd_page_len();
}
+/*
+ * Poll SVQ for multiple pending control commands and check the device's ack.
+ *
+ * Caller should hold the BQL when invoking this function.
+ *
+ * @s: The VhostVDPAState
+ * @len: The length of the pending status shadow buffer
+ */
+static ssize_t vhost_vdpa_net_svq_flush(VhostVDPAState *s, size_t len)
+{
+ /* device uses a one-byte length ack for each control command */
+ ssize_t dev_written = vhost_vdpa_net_svq_poll(s, len);
+ if (unlikely(dev_written != len)) {
+ return -EIO;
+ }
+
+ /* check the device's ack */
+ for (int i = 0; i < len; ++i) {
+ if (s->status[i] != VIRTIO_NET_OK) {
+ return -EIO;
+ }
+ }
+ return 0;
+}
+
static ssize_t vhost_vdpa_net_load_cmd(VhostVDPAState *s,
struct iovec *out_cursor,
struct iovec *in_cursor, uint8_t class,
@@ -671,11 +696,31 @@ static ssize_t vhost_vdpa_net_load_cmd(VhostVDPAState *s,
.class = class,
.cmd = cmd,
};
- size_t data_size = iov_size(data_sg, data_num);
+ size_t data_size = iov_size(data_sg, data_num), cmd_size;
struct iovec out, in;
ssize_t r;
+ unsigned dummy_cursor_iov_cnt;
+ VhostShadowVirtqueue *svq = g_ptr_array_index(s->vhost_vdpa.shadow_vqs, 0);
assert(data_size < vhost_vdpa_net_cvq_cmd_page_len() - sizeof(ctrl));
+ cmd_size = sizeof(ctrl) + data_size;
+ if (vhost_svq_available_slots(svq) < 2 ||
+ iov_size(out_cursor, 1) < cmd_size) {
+ /*
+ * It is time to flush all pending control commands if SVQ is full
+ * or control commands shadow buffers are full.
+ *
+ * We can poll here since we've had BQL from the time
+ * we sent the descriptor.
+ */
+ r = vhost_vdpa_net_svq_flush(s, in_cursor->iov_base -
+ (void *)s->status);
+ if (unlikely(r < 0)) {
+ return r;
+ }
+
+ vhost_vdpa_net_load_cursor_reset(s, out_cursor, in_cursor);
+ }
/* pack the CVQ command header */
iov_from_buf(out_cursor, 1, 0, &ctrl, sizeof(ctrl));
@@ -684,7 +729,7 @@ static ssize_t vhost_vdpa_net_load_cmd(VhostVDPAState *s,
out_cursor->iov_base + sizeof(ctrl), data_size);
/* extract the required buffer from the cursor for output */
- iov_copy(&out, 1, out_cursor, 1, 0, sizeof(ctrl) + data_size);
+ iov_copy(&out, 1, out_cursor, 1, 0, cmd_size);
/* extract the required buffer from the cursor for input */
iov_copy(&in, 1, in_cursor, 1, 0, sizeof(*s->status));
@@ -693,11 +738,13 @@ static ssize_t vhost_vdpa_net_load_cmd(VhostVDPAState *s,
return r;
}
- /*
- * We can poll here since we've had BQL from the time
- * we sent the descriptor.
- */
- return vhost_vdpa_net_svq_poll(s, 1);
+ /* iterate the cursors */
+ dummy_cursor_iov_cnt = 1;
+ iov_discard_front(&out_cursor, &dummy_cursor_iov_cnt, cmd_size);
+ dummy_cursor_iov_cnt = 1;
+ iov_discard_front(&in_cursor, &dummy_cursor_iov_cnt, sizeof(*s->status));
+
+ return 0;
}
static int vhost_vdpa_net_load_mac(VhostVDPAState *s, const VirtIONet *n,
@@ -709,15 +756,12 @@ static int vhost_vdpa_net_load_mac(VhostVDPAState *s, const VirtIONet *n,
.iov_base = (void *)n->mac,
.iov_len = sizeof(n->mac),
};
- ssize_t dev_written = vhost_vdpa_net_load_cmd(s, out_cursor, in_cursor,
- VIRTIO_NET_CTRL_MAC,
- VIRTIO_NET_CTRL_MAC_ADDR_SET,
- &data, 1);
- if (unlikely(dev_written < 0)) {
- return dev_written;
- }
- if (*s->status != VIRTIO_NET_OK) {
- return -EIO;
+ ssize_t r = vhost_vdpa_net_load_cmd(s, out_cursor, in_cursor,
+ VIRTIO_NET_CTRL_MAC,
+ VIRTIO_NET_CTRL_MAC_ADDR_SET,
+ &data, 1);
+ if (unlikely(r < 0)) {
+ return r;
}
}
@@ -762,15 +806,12 @@ static int vhost_vdpa_net_load_mac(VhostVDPAState *s, const VirtIONet *n,
.iov_len = mul_macs_size,
},
};
- ssize_t dev_written = vhost_vdpa_net_load_cmd(s, out_cursor, in_cursor,
- VIRTIO_NET_CTRL_MAC,
- VIRTIO_NET_CTRL_MAC_TABLE_SET,
- data, ARRAY_SIZE(data));
- if (unlikely(dev_written < 0)) {
- return dev_written;
- }
- if (*s->status != VIRTIO_NET_OK) {
- return -EIO;
+ ssize_t r = vhost_vdpa_net_load_cmd(s, out_cursor, in_cursor,
+ VIRTIO_NET_CTRL_MAC,
+ VIRTIO_NET_CTRL_MAC_TABLE_SET,
+ data, ARRAY_SIZE(data));
+ if (unlikely(r < 0)) {
+ return r;
}
return 0;
@@ -782,7 +823,7 @@ static int vhost_vdpa_net_load_mq(VhostVDPAState *s,
struct iovec *in_cursor)
{
struct virtio_net_ctrl_mq mq;
- ssize_t dev_written;
+ ssize_t r;
if (!virtio_vdev_has_feature(&n->parent_obj, VIRTIO_NET_F_MQ)) {
return 0;
@@ -793,15 +834,12 @@ static int vhost_vdpa_net_load_mq(VhostVDPAState *s,
.iov_base = &mq,
.iov_len = sizeof(mq),
};
- dev_written = vhost_vdpa_net_load_cmd(s, out_cursor, in_cursor,
- VIRTIO_NET_CTRL_MQ,
- VIRTIO_NET_CTRL_MQ_VQ_PAIRS_SET,
- &data, 1);
- if (unlikely(dev_written < 0)) {
- return dev_written;
- }
- if (*s->status != VIRTIO_NET_OK) {
- return -EIO;
+ r = vhost_vdpa_net_load_cmd(s, out_cursor, in_cursor,
+ VIRTIO_NET_CTRL_MQ,
+ VIRTIO_NET_CTRL_MQ_VQ_PAIRS_SET,
+ &data, 1);
+ if (unlikely(r < 0)) {
+ return r;
}
return 0;
@@ -813,7 +851,7 @@ static int vhost_vdpa_net_load_offloads(VhostVDPAState *s,
struct iovec *in_cursor)
{
uint64_t offloads;
- ssize_t dev_written;
+ ssize_t r;
if (!virtio_vdev_has_feature(&n->parent_obj,
VIRTIO_NET_F_CTRL_GUEST_OFFLOADS)) {
@@ -841,15 +879,12 @@ static int vhost_vdpa_net_load_offloads(VhostVDPAState *s,
.iov_base = &offloads,
.iov_len = sizeof(offloads),
};
- dev_written = vhost_vdpa_net_load_cmd(s, out_cursor, in_cursor,
- VIRTIO_NET_CTRL_GUEST_OFFLOADS,
- VIRTIO_NET_CTRL_GUEST_OFFLOADS_SET,
- &data, 1);
- if (unlikely(dev_written < 0)) {
- return dev_written;
- }
- if (*s->status != VIRTIO_NET_OK) {
- return -EIO;
+ r = vhost_vdpa_net_load_cmd(s, out_cursor, in_cursor,
+ VIRTIO_NET_CTRL_GUEST_OFFLOADS,
+ VIRTIO_NET_CTRL_GUEST_OFFLOADS_SET,
+ &data, 1);
+ if (unlikely(r < 0)) {
+ return r;
}
return 0;
@@ -865,16 +900,12 @@ static int vhost_vdpa_net_load_rx_mode(VhostVDPAState *s,
.iov_base = &on,
.iov_len = sizeof(on),
};
- ssize_t dev_written;
+ ssize_t r;
- dev_written = vhost_vdpa_net_load_cmd(s, out_cursor, in_cursor,
- VIRTIO_NET_CTRL_RX,
- cmd, &data, 1);
- if (unlikely(dev_written < 0)) {
- return dev_written;
- }
- if (*s->status != VIRTIO_NET_OK) {
- return -EIO;
+ r = vhost_vdpa_net_load_cmd(s, out_cursor, in_cursor,
+ VIRTIO_NET_CTRL_RX, cmd, &data, 1);
+ if (unlikely(r < 0)) {
+ return r;
}
return 0;
@@ -1031,15 +1062,12 @@ static int vhost_vdpa_net_load_single_vlan(VhostVDPAState *s,
.iov_base = &vid,
.iov_len = sizeof(vid),
};
- ssize_t dev_written = vhost_vdpa_net_load_cmd(s, out_cursor, in_cursor,
- VIRTIO_NET_CTRL_VLAN,
- VIRTIO_NET_CTRL_VLAN_ADD,
- &data, 1);
- if (unlikely(dev_written < 0)) {
- return dev_written;
- }
- if (unlikely(*s->status != VIRTIO_NET_OK)) {
- return -EIO;
+ ssize_t r = vhost_vdpa_net_load_cmd(s, out_cursor, in_cursor,
+ VIRTIO_NET_CTRL_VLAN,
+ VIRTIO_NET_CTRL_VLAN_ADD,
+ &data, 1);
+ if (unlikely(r < 0)) {
+ return r;
}
return 0;
@@ -1106,6 +1134,17 @@ static int vhost_vdpa_net_cvq_load(NetClientState *nc)
if (unlikely(r)) {
return r;
}
+
+ /*
+ * We need to poll and check all pending device's used buffers.
+ *
+ * We can poll here since we've had BQL from the time
+ * we sent the descriptor.
+ */
+ r = vhost_vdpa_net_svq_flush(s, in_cursor.iov_base - (void *)s->status);
+ if (unlikely(r)) {
+ return r;
+ }
}
for (int i = 0; i < v->dev->vq_index; ++i) {
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 08/78] tests: test-smp-parse: Add the test for cores/threads per socket helpers
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (6 preceding siblings ...)
2023-10-19 18:21 ` [PULL v2 07/78] vdpa: Send cvq state load commands in parallel Michael S. Tsirkin
@ 2023-10-19 18:21 ` Michael S. Tsirkin
2023-10-19 18:21 ` [PULL v2 09/78] tests: bios-tables-test: Prepare the ACPI table change for smbios type4 count test Michael S. Tsirkin
` (70 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:21 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Zhao Liu, Igor Mammedov, Eduardo Habkost,
Marcel Apfelbaum, Philippe Mathieu-Daudé, Yanan Wang
From: Zhao Liu <zhao1.liu@intel.com>
Use the different ways to calculate cores/threads per socket, so that
the new CPU topology levels won't be missed in these 2 helpes:
* machine_topo_get_cores_per_socket()
* machine_topo_get_threads_per_socket()
Test the commit a1d027be95bc3 ("machine: Add helpers to get cores/
threads per socket").
Suggested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Acked-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <20230928125943.1816922-2-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
tests/unit/test-smp-parse.c | 67 ++++++++++++++++++++++++++++++-------
1 file changed, 54 insertions(+), 13 deletions(-)
diff --git a/tests/unit/test-smp-parse.c b/tests/unit/test-smp-parse.c
index fdc39a846c..24972666a7 100644
--- a/tests/unit/test-smp-parse.c
+++ b/tests/unit/test-smp-parse.c
@@ -394,20 +394,47 @@ static char *smp_config_to_string(const SMPConfiguration *config)
config->has_maxcpus ? "true" : "false", config->maxcpus);
}
-static char *cpu_topology_to_string(const CpuTopology *topo)
+/* Use the different calculation than machine_topo_get_threads_per_socket(). */
+static unsigned int cpu_topology_get_threads_per_socket(const CpuTopology *topo)
+{
+ /* Check the divisor to avoid invalid topology examples causing SIGFPE. */
+ if (!topo->sockets) {
+ return 0;
+ } else {
+ return topo->max_cpus / topo->sockets;
+ }
+}
+
+/* Use the different calculation than machine_topo_get_cores_per_socket(). */
+static unsigned int cpu_topology_get_cores_per_socket(const CpuTopology *topo)
+{
+ /* Check the divisor to avoid invalid topology examples causing SIGFPE. */
+ if (!topo->threads) {
+ return 0;
+ } else {
+ return cpu_topology_get_threads_per_socket(topo) / topo->threads;
+ }
+}
+
+static char *cpu_topology_to_string(const CpuTopology *topo,
+ unsigned int threads_per_socket,
+ unsigned int cores_per_socket)
{
return g_strdup_printf(
"(CpuTopology) {\n"
- " .cpus = %u,\n"
- " .sockets = %u,\n"
- " .dies = %u,\n"
- " .clusters = %u,\n"
- " .cores = %u,\n"
- " .threads = %u,\n"
- " .max_cpus = %u,\n"
+ " .cpus = %u,\n"
+ " .sockets = %u,\n"
+ " .dies = %u,\n"
+ " .clusters = %u,\n"
+ " .cores = %u,\n"
+ " .threads = %u,\n"
+ " .max_cpus = %u,\n"
+ " .threads_per_socket = %u,\n"
+ " .cores_per_socket = %u,\n"
"}",
topo->cpus, topo->sockets, topo->dies, topo->clusters,
- topo->cores, topo->threads, topo->max_cpus);
+ topo->cores, topo->threads, topo->max_cpus,
+ threads_per_socket, cores_per_socket);
}
static void check_parse(MachineState *ms, const SMPConfiguration *config,
@@ -415,14 +442,26 @@ static void check_parse(MachineState *ms, const SMPConfiguration *config,
bool is_valid)
{
g_autofree char *config_str = smp_config_to_string(config);
- g_autofree char *expect_topo_str = cpu_topology_to_string(expect_topo);
- g_autofree char *output_topo_str = NULL;
+ g_autofree char *expect_topo_str = NULL, *output_topo_str = NULL;
+ unsigned int expect_threads_per_socket, expect_cores_per_socket;
+ unsigned int ms_threads_per_socket, ms_cores_per_socket;
Error *err = NULL;
+ expect_threads_per_socket =
+ cpu_topology_get_threads_per_socket(expect_topo);
+ expect_cores_per_socket =
+ cpu_topology_get_cores_per_socket(expect_topo);
+ expect_topo_str = cpu_topology_to_string(expect_topo,
+ expect_threads_per_socket,
+ expect_cores_per_socket);
+
/* call the generic parser */
machine_parse_smp_config(ms, config, &err);
- output_topo_str = cpu_topology_to_string(&ms->smp);
+ ms_threads_per_socket = machine_topo_get_threads_per_socket(ms);
+ ms_cores_per_socket = machine_topo_get_cores_per_socket(ms);
+ output_topo_str = cpu_topology_to_string(&ms->smp, ms_threads_per_socket,
+ ms_cores_per_socket);
/* when the configuration is supposed to be valid */
if (is_valid) {
@@ -433,7 +472,9 @@ static void check_parse(MachineState *ms, const SMPConfiguration *config,
(ms->smp.clusters == expect_topo->clusters) &&
(ms->smp.cores == expect_topo->cores) &&
(ms->smp.threads == expect_topo->threads) &&
- (ms->smp.max_cpus == expect_topo->max_cpus)) {
+ (ms->smp.max_cpus == expect_topo->max_cpus) &&
+ (ms_threads_per_socket == expect_threads_per_socket) &&
+ (ms_cores_per_socket == expect_cores_per_socket)) {
return;
}
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 09/78] tests: bios-tables-test: Prepare the ACPI table change for smbios type4 count test
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (7 preceding siblings ...)
2023-10-19 18:21 ` [PULL v2 08/78] tests: test-smp-parse: Add the test for cores/threads per socket helpers Michael S. Tsirkin
@ 2023-10-19 18:21 ` Michael S. Tsirkin
2023-10-19 18:21 ` [PULL v2 10/78] tests: bios-tables-test: Add test for smbios type4 count Michael S. Tsirkin
` (69 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:21 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Zhao Liu, Igor Mammedov, Ani Sinha
From: Zhao Liu <zhao1.liu@intel.com>
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 1 - 3.
List the ACPI tables that will be added to test the type 4 count.
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Message-Id: <20230928125943.1816922-3-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
tests/qtest/bios-tables-test-allowed-diff.h | 3 +++
tests/data/acpi/q35/APIC.type4-count | 0
tests/data/acpi/q35/DSDT.type4-count | 0
tests/data/acpi/q35/FACP.type4-count | 0
4 files changed, 3 insertions(+)
create mode 100644 tests/data/acpi/q35/APIC.type4-count
create mode 100644 tests/data/acpi/q35/DSDT.type4-count
create mode 100644 tests/data/acpi/q35/FACP.type4-count
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..0ce6f8fc72 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1 +1,4 @@
/* List of comma-separated changed AML files to ignore */
+"tests/data/acpi/q35/APIC.type4-count",
+"tests/data/acpi/q35/DSDT.type4-count",
+"tests/data/acpi/q35/FACP.type4-count",
diff --git a/tests/data/acpi/q35/APIC.type4-count b/tests/data/acpi/q35/APIC.type4-count
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/tests/data/acpi/q35/DSDT.type4-count b/tests/data/acpi/q35/DSDT.type4-count
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/tests/data/acpi/q35/FACP.type4-count b/tests/data/acpi/q35/FACP.type4-count
new file mode 100644
index 0000000000..e69de29bb2
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 10/78] tests: bios-tables-test: Add test for smbios type4 count
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (8 preceding siblings ...)
2023-10-19 18:21 ` [PULL v2 09/78] tests: bios-tables-test: Prepare the ACPI table change for smbios type4 count test Michael S. Tsirkin
@ 2023-10-19 18:21 ` Michael S. Tsirkin
2023-10-19 18:21 ` [PULL v2 11/78] tests: bios-tables-test: Add ACPI table binaries for smbios type4 count test Michael S. Tsirkin
` (68 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:21 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Zhao Liu, Igor Mammedov, Ani Sinha
From: Zhao Liu <zhao1.liu@intel.com>
This tests the commit d79a284a44bb7 ("hw/smbios: Fix smbios_smp_sockets
calculation").
In smbios_get_tables() (hw/smbios/smbios.c), smbios type4 table is built
for each socket, so the count of type4 tables should be equal to the
number of sockets.
Thus for the topology in this case, there're the following considerations:
1. The topology should include multiple sockets to ensure smbios could
create type4 tables for each socket.
2. In addition to sockets, for the more general topology, we should also
configure as many topology levels as possible (multiple dies, no
module since x86 hasn't supported it), to ensure that smbios is able
to exclude the effect of other topology levels to create the type4
tables only for sockets.
3. The original miscalculation bug also misused "smp.cpus", so it's
necessary to configure "cpus" (presented threads for machine) and
"maxcpus" (total threads for machine) as well to make sure that
configuring unpluged CPUs in smp (cpus < maxcpus) does not affect
the correctness of the count of type4 tables.
Based on these considerations, select the topology as the follow:
-smp cpus=100,maxcpus=120,sockets=5,dies=2,cores=4,threads=3
The expected count of type4 tables = sockets (5).
Suggested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Message-Id: <20230928125943.1816922-4-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
tests/qtest/bios-tables-test.c | 33 ++++++++++++++++++++++++++++++++-
1 file changed, 32 insertions(+), 1 deletion(-)
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index 9f4bc15aab..cdbfb51559 100644
--- a/tests/qtest/bios-tables-test.c
+++ b/tests/qtest/bios-tables-test.c
@@ -97,6 +97,7 @@ typedef struct {
uint16_t smbios_core_count2;
uint8_t *required_struct_types;
int required_struct_types_len;
+ int type4_count;
QTestState *qts;
} test_data;
@@ -673,12 +674,21 @@ static void smbios_cpu_test(test_data *data, uint32_t addr,
}
}
+static void smbios_type4_count_test(test_data *data, int type4_count)
+{
+ int expected_type4_count = data->type4_count;
+
+ if (expected_type4_count) {
+ g_assert_cmpuint(type4_count, ==, expected_type4_count);
+ }
+}
+
static void test_smbios_structs(test_data *data, SmbiosEntryPointType ep_type)
{
DECLARE_BITMAP(struct_bitmap, SMBIOS_MAX_TYPE+1) = { 0 };
SmbiosEntryPoint *ep_table = &data->smbios_ep_table;
- int i = 0, len, max_len = 0;
+ int i = 0, len, max_len = 0, type4_count = 0;
uint8_t type, prv, crt;
uint64_t addr;
@@ -704,6 +714,7 @@ static void test_smbios_structs(test_data *data, SmbiosEntryPointType ep_type)
if (type == 4) {
smbios_cpu_test(data, addr, ep_type);
+ type4_count++;
}
/* seek to end of unformatted string area of this struct ("\0\0") */
@@ -747,6 +758,8 @@ static void test_smbios_structs(test_data *data, SmbiosEntryPointType ep_type)
for (i = 0; i < data->required_struct_types_len; i++) {
g_assert(test_bit(data->required_struct_types[i], struct_bitmap));
}
+
+ smbios_type4_count_test(data, type4_count);
}
static void test_acpi_load_tables(test_data *data)
@@ -970,6 +983,22 @@ static void test_acpi_q35_tcg(void)
free_test_data(&data);
}
+static void test_acpi_q35_tcg_type4_count(void)
+{
+ test_data data = {
+ .machine = MACHINE_Q35,
+ .variant = ".type4-count",
+ .required_struct_types = base_required_struct_types,
+ .required_struct_types_len = ARRAY_SIZE(base_required_struct_types),
+ .type4_count = 5,
+ };
+
+ test_acpi_one("-machine smbios-entry-point-type=64 "
+ "-smp cpus=100,maxcpus=120,sockets=5,"
+ "dies=2,cores=4,threads=3", &data);
+ free_test_data(&data);
+}
+
static void test_acpi_q35_tcg_core_count2(void)
{
test_data data = {
@@ -2147,6 +2176,8 @@ int main(int argc, char *argv[])
if (has_kvm) {
qtest_add_func("acpi/q35/kvm/xapic", test_acpi_q35_kvm_xapic);
qtest_add_func("acpi/q35/kvm/dmar", test_acpi_q35_kvm_dmar);
+ qtest_add_func("acpi/q35/type4-count",
+ test_acpi_q35_tcg_type4_count);
qtest_add_func("acpi/q35/core-count2",
test_acpi_q35_tcg_core_count2);
}
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 11/78] tests: bios-tables-test: Add ACPI table binaries for smbios type4 count test
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (9 preceding siblings ...)
2023-10-19 18:21 ` [PULL v2 10/78] tests: bios-tables-test: Add test for smbios type4 count Michael S. Tsirkin
@ 2023-10-19 18:21 ` Michael S. Tsirkin
2023-10-19 18:21 ` [PULL v2 12/78] tests: bios-tables-test: Prepare the ACPI table change for smbios type4 core " Michael S. Tsirkin
` (67 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:21 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Zhao Liu, Igor Mammedov, Ani Sinha
From: Zhao Liu <zhao1.liu@intel.com>
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 5 and 6.
Changes in the tables:
FACP:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembly of /tmp/aml-W37791, Wed Aug 23 10:36:32 2023
+ *
+ * ACPI Data Table [FACP]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)]
+[004h 0004 4] Table Length : 000000F4
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : B3
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPC "
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] FACS Address : 00000000
+[028h 0040 4] DSDT Address : 00000000
+[02Ch 0044 1] Model : 01
+[02Dh 0045 1] PM Profile : 00 [Unspecified]
+[02Eh 0046 2] SCI Interrupt : 0009
+[030h 0048 4] SMI Command Port : 000000B2
+[034h 0052 1] ACPI Enable Value : 02
+[035h 0053 1] ACPI Disable Value : 03
+[036h 0054 1] S4BIOS Command : 00
+[037h 0055 1] P-State Control : 00
+[038h 0056 4] PM1A Event Block Address : 00000600
+[03Ch 0060 4] PM1B Event Block Address : 00000000
+[040h 0064 4] PM1A Control Block Address : 00000604
+[044h 0068 4] PM1B Control Block Address : 00000000
+[048h 0072 4] PM2 Control Block Address : 00000000
+[04Ch 0076 4] PM Timer Block Address : 00000608
+[050h 0080 4] GPE0 Block Address : 00000620
+[054h 0084 4] GPE1 Block Address : 00000000
+[058h 0088 1] PM1 Event Block Length : 04
+[059h 0089 1] PM1 Control Block Length : 02
+[05Ah 0090 1] PM2 Control Block Length : 00
+[05Bh 0091 1] PM Timer Block Length : 04
+[05Ch 0092 1] GPE0 Block Length : 10
+[05Dh 0093 1] GPE1 Block Length : 00
+[05Eh 0094 1] GPE1 Base Offset : 00
+[05Fh 0095 1] _CST Support : 00
+[060h 0096 2] C2 Latency : 0FFF
+[062h 0098 2] C3 Latency : 0FFF
+[064h 0100 2] CPU Cache Size : 0000
+[066h 0102 2] Cache Flush Stride : 0000
+[068h 0104 1] Duty Cycle Offset : 00
+[069h 0105 1] Duty Cycle Width : 00
+[06Ah 0106 1] RTC Day Alarm Index : 00
+[06Bh 0107 1] RTC Month Alarm Index : 00
+[06Ch 0108 1] RTC Century Index : 32
+[06Dh 0109 2] Boot Flags (decoded below) : 0002
+ Legacy Devices Supported (V2) : 0
+ 8042 Present on ports 60/64 (V2) : 1
+ VGA Not Present (V4) : 0
+ MSI Not Supported (V4) : 0
+ PCIe ASPM Not Supported (V4) : 0
+ CMOS RTC Not Present (V5) : 0
+[06Fh 0111 1] Reserved : 00
+[070h 0112 4] Flags (decoded below) : 000484A5
+ WBINVD instruction is operational (V1) : 1
+ WBINVD flushes all caches (V1) : 0
+ All CPUs support C1 (V1) : 1
+ C2 works on MP system (V1) : 0
+ Control Method Power Button (V1) : 0
+ Control Method Sleep Button (V1) : 1
+ RTC wake not in fixed reg space (V1) : 0
+ RTC can wake system from S4 (V1) : 1
+ 32-bit PM Timer (V1) : 0
+ Docking Supported (V1) : 0
+ Reset Register Supported (V2) : 1
+ Sealed Case (V3) : 0
+ Headless - No Video (V3) : 0
+ Use native instr after SLP_TYPx (V3) : 0
+ PCIEXP_WAK Bits Supported (V4) : 0
+ Use Platform Timer (V4) : 1
+ RTC_STS valid on S4 wake (V4) : 0
+ Remote Power-on capable (V4) : 0
+ Use APIC Cluster Model (V4) : 1
+ Use APIC Physical Destination Mode (V4) : 0
+ Hardware Reduced (V5) : 0
+ Low Power S0 Idle (V5) : 0
+
+[074h 0116 12] Reset Register : [Generic Address Structure]
+[074h 0116 1] Space ID : 01 [SystemIO]
+[075h 0117 1] Bit Width : 08
+[076h 0118 1] Bit Offset : 00
+[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy]
+[078h 0120 8] Address : 0000000000000CF9
+
+[080h 0128 1] Value to cause reset : 0F
+[081h 0129 2] ARM Flags (decoded below) : 0000
+ PSCI Compliant : 0
+ Must use HVC for PSCI : 0
+
+[083h 0131 1] FADT Minor Revision : 00
+[084h 0132 8] FACS Address : 0000000000000000
+[08Ch 0140 8] DSDT Address : 0000000000000000
+[094h 0148 12] PM1A Event Block : [Generic Address Structure]
+[094h 0148 1] Space ID : 01 [SystemIO]
+[095h 0149 1] Bit Width : 20
+[096h 0150 1] Bit Offset : 00
+[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy]
+[098h 0152 8] Address : 0000000000000600
+
+[0A0h 0160 12] PM1B Event Block : [Generic Address Structure]
+[0A0h 0160 1] Space ID : 00 [SystemMemory]
+[0A1h 0161 1] Bit Width : 00
+[0A2h 0162 1] Bit Offset : 00
+[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0A4h 0164 8] Address : 0000000000000000
+
+[0ACh 0172 12] PM1A Control Block : [Generic Address Structure]
+[0ACh 0172 1] Space ID : 01 [SystemIO]
+[0ADh 0173 1] Bit Width : 10
+[0AEh 0174 1] Bit Offset : 00
+[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0B0h 0176 8] Address : 0000000000000604
+
+[0B8h 0184 12] PM1B Control Block : [Generic Address Structure]
+[0B8h 0184 1] Space ID : 00 [SystemMemory]
+[0B9h 0185 1] Bit Width : 00
+[0BAh 0186 1] Bit Offset : 00
+[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0BCh 0188 8] Address : 0000000000000000
+
+[0C4h 0196 12] PM2 Control Block : [Generic Address Structure]
+[0C4h 0196 1] Space ID : 00 [SystemMemory]
+[0C5h 0197 1] Bit Width : 00
+[0C6h 0198 1] Bit Offset : 00
+[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0C8h 0200 8] Address : 0000000000000000
+
+[0D0h 0208 12] PM Timer Block : [Generic Address Structure]
+[0D0h 0208 1] Space ID : 01 [SystemIO]
+[0D1h 0209 1] Bit Width : 20
+[0D2h 0210 1] Bit Offset : 00
+[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0D4h 0212 8] Address : 0000000000000608
+
+[0DCh 0220 12] GPE0 Block : [Generic Address Structure]
+[0DCh 0220 1] Space ID : 01 [SystemIO]
+[0DDh 0221 1] Bit Width : 80
+[0DEh 0222 1] Bit Offset : 00
+[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0E0h 0224 8] Address : 0000000000000620
+
+[0E8h 0232 12] GPE1 Block : [Generic Address Structure]
+[0E8h 0232 1] Space ID : 00 [SystemMemory]
+[0E9h 0233 1] Bit Width : 00
+[0EAh 0234 1] Bit Offset : 00
+[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0ECh 0236 8] Address : 0000000000000000
+
...
APIC:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembly of /tmp/aml-687791, Wed Aug 23 10:36:32 2023
+ *
+ * ACPI Data Table [APIC]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)]
+[004h 0004 4] Table Length : 00000430
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : C5
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPC "
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Local Apic Address : FEE00000
+[028h 0040 4] Flags (decoded below) : 00000001
+ PC-AT Compatibility : 1
+
+[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC]
+[02Dh 0045 1] Length : 08
+[02Eh 0046 1] Processor ID : 00
+[02Fh 0047 1] Local Apic ID : 00
+[030h 0048 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
+
+[034h 0052 1] Subtable Type : 00 [Processor Local APIC]
+[035h 0053 1] Length : 08
+[036h 0054 1] Processor ID : 01
+[037h 0055 1] Local Apic ID : 01
+[038h 0056 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
[snip]
+[3E4h 0996 1] Subtable Type : 00 [Processor Local APIC]
+[3E5h 0997 1] Length : 08
+[3E6h 0998 1] Processor ID : 77
+[3E7h 0999 1] Local Apic ID : 9E
+[3E8h 1000 4] Flags (decoded below) : 00000000
+ Processor Enabled : 0
+ Runtime Online Capable : 0
+
+[3ECh 1004 1] Subtable Type : 01 [I/O APIC]
+[3EDh 1005 1] Length : 0C
+[3EEh 1006 1] I/O Apic ID : 00
+[3EFh 1007 1] Reserved : 00
+[3F0h 1008 4] Address : FEC00000
+[3F4h 1012 4] Interrupt : 00000000
+
+[3F8h 1016 1] Subtable Type : 02 [Interrupt Source Override]
+[3F9h 1017 1] Length : 0A
+[3FAh 1018 1] Bus : 00
+[3FBh 1019 1] Source : 00
+[3FCh 1020 4] Interrupt : 00000002
+[400h 1024 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+
+[402h 1026 1] Subtable Type : 02 [Interrupt Source Override]
+[403h 1027 1] Length : 0A
+[404h 1028 1] Bus : 00
+[405h 1029 1] Source : 05
+[406h 1030 4] Interrupt : 00000005
+[40Ah 1034 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[40Ch 1036 1] Subtable Type : 02 [Interrupt Source Override]
+[40Dh 1037 1] Length : 0A
+[40Eh 1038 1] Bus : 00
+[40Fh 1039 1] Source : 09
+[410h 1040 4] Interrupt : 00000009
+[414h 1044 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[416h 1046 1] Subtable Type : 02 [Interrupt Source Override]
+[417h 1047 1] Length : 0A
+[418h 1048 1] Bus : 00
+[419h 1049 1] Source : 0A
+[41Ah 1050 4] Interrupt : 0000000A
+[41Eh 1054 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[420h 1056 1] Subtable Type : 02 [Interrupt Source Override]
+[421h 1057 1] Length : 0A
+[422h 1058 1] Bus : 00
+[423h 1059 1] Source : 0B
+[424h 1060 4] Interrupt : 0000000B
+[428h 1064 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[42Ah 1066 1] Subtable Type : 04 [Local APIC NMI]
+[42Bh 1067 1] Length : 06
+[42Ch 1068 1] Processor ID : FF
+[42Dh 1069 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+[42Fh 1071 1] Interrupt Input LINT : 01
+
...
DSDT:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembling to symbolic ASL+ operators
+ *
+ * Disassembly of /tmp/aml-8G8791, Wed Aug 23 10:36:32 2023
+ *
+ * Original Table Header:
+ * Signature "DSDT"
+ * Length 0x0000489D (18589)
+ * Revision 0x01 **** 32-bit table (V1), no 64-bit math support
+ * Checksum 0xDB
+ * OEM ID "BOCHS "
+ * OEM Table ID "BXPC "
+ * OEM Revision 0x00000001 (1)
+ * Compiler ID "BXPC"
+ * Compiler Version 0x00000001 (1)
+ */
+DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001)
+{
+ Scope (\)
+ {
+ OperationRegion (DBG, SystemIO, 0x0402, One)
+ Field (DBG, ByteAcc, NoLock, Preserve)
+ {
+ DBGB, 8
+ }
+
+ Method (DBUG, 1, NotSerialized)
+ {
+ ToHexString (Arg0, Local0)
+ ToBuffer (Local0, Local0)
+ Local1 = (SizeOf (Local0) - One)
+ Local2 = Zero
+ While ((Local2 < Local1))
+ {
+ DBGB = DerefOf (Local0 [Local2])
+ Local2++
+ }
+
+ DBGB = 0x0A
+ }
+ }
+
[snip]
+
+ Processor (C000, 0x00, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (Zero))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........
+ })
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (Zero, Arg0, Arg1, Arg2)
+ }
+ }
+
+ Processor (C001, 0x01, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (One))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00 // ........
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (One)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (One, Arg0, Arg1, Arg2)
+ }
+ }
[snip]
+ Processor (C077, 0x77, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (0x77))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x77, 0x9E, 0x01, 0x00, 0x00, 0x00 // ..w.....
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (0x77)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (0x77, Arg0, Arg1, Arg2)
+ }
+ }
+ }
+ }
+
...
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Message-Id: <20230928125943.1816922-5-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
tests/qtest/bios-tables-test-allowed-diff.h | 3 ---
tests/data/acpi/q35/APIC.type4-count | Bin 0 -> 1072 bytes
tests/data/acpi/q35/DSDT.type4-count | Bin 0 -> 18589 bytes
tests/data/acpi/q35/FACP.type4-count | Bin 0 -> 244 bytes
4 files changed, 3 deletions(-)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index 0ce6f8fc72..dfb8523c8b 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1,4 +1 @@
/* List of comma-separated changed AML files to ignore */
-"tests/data/acpi/q35/APIC.type4-count",
-"tests/data/acpi/q35/DSDT.type4-count",
-"tests/data/acpi/q35/FACP.type4-count",
diff --git a/tests/data/acpi/q35/APIC.type4-count b/tests/data/acpi/q35/APIC.type4-count
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..ab60a6ef065d8ce53ae93d311d3777d2d4afb9f6 100644
GIT binary patch
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literal 0
HcmV?d00001
diff --git a/tests/data/acpi/q35/DSDT.type4-count b/tests/data/acpi/q35/DSDT.type4-count
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..edc23198cdb47a981bcbc82bc8e392b815abb554 100644
GIT binary patch
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zAxa8Kk_}&*R8p9b!V#4erlhbWrQrgGN@^jbmUflYLP;%>lz|HxDyfx_T02xyD<!o`
zQWh?7s3iDa=ROPCqAID4lG<ESJcg?p${B}s50@0#qLLz%6p^GjE?y`kSn_a5?ORn+
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z+jgs@ZIrZ4l7``ei%Qx~NZZ*~O8Ty{oszao(g<9DQAs-pX~$l*rX7^DLz0rPqd_Hg
z5mHyLO6sDdE=fwk1savKlaO}qS4lf5X{RLFaKT0;brVwe0hQEEN!^l^h6^|<X%`{w
zI;fI%QPM6+%D@F3m9(3Xb{|$ryD4e6BxT_Ok4oA@NPCW`q&<|h$0a3VJvym}ka~`)
zq#jD@k)-%uowS#b_8wPBdnswJBqe%vQZFI(o={1>l+-IpefxCMK0?}eQYG!9q<xaq
zzh5WqC#3x`m9(Fd_Dj;h0iAS!kPfg<q4X7efRYYK(%?azbdZn^Ce)e^Qqn<58akwt
z4iVC!ewB2Hk`77I@L`>Fn2-(+sHDS`bXbx`j_9N#gmh$3B^{xpBa)Ons*{cq($Qg+
zbd-{gN>b{WPC7<N$3|4rF-kfnN%nD_bexcmpH@l7De1T*rBCRj6NGf)tV%jTNhc&J
zb5bXrB&3t)RMJUGIw?unQ#$DsA)Pv}l1@?5DVNkIzRr2ROTk8dcXGxqs-zet#Uv>n
z*K3LsQaq`W;*=DZq(nj|B?u{zQb`F)N=Q;)pHAu{q`tID>Z7DSN$T&{N&SS>pHWHu
zl+-Ut0|Po~fRF~@S^<2NA>XA2C}}{F1_yQ0AR!IrRMH?N4NB6`kWLyRq@lb@8lt2j
zNg5v3NyCIRJf@O{DQQ@eMn-hf2qBG3sH71}8j+;rX`OVMkWLp=(rHRMElH^}I_V4{
zotacgXDI26B-v+m(pf?}TU1GBDe0^vrO)Z4bA)tmN+q46q;ry#Ij@t>6VmyTN;*$T
z=Orn7K_^`xqzlt3=>jEPa7q2Ki#q8dAzhqNNf#;Uq9nzWItebByYF<#%PJ{JNl8gc
zq;wKoEq6(&t11aMvAF9`DM{+HbrM`CcS-g&m4y3IT#_wG{b`*9*T`K``npQOttBog
zElC3zodlOvT~cONCE+d+mz0sD!K_Y#E8{LHdqXARh7XsNm879jodg%fUDD`Hm4tgY
zT+*l{4d-+cTn~3ixtdDCZ5S>oCrKlDos=h}{G3Y4Q&L`%l4Ck)jF86WRnizGjY(2!
zTqlha()glE8mFXjNwOz&(gYz*+)_yslr$kp>4HvzjRWo(FWgp11xhMNQf5*oO%l@N
zl1iGSq)AE2UeZaI2<g(YO1eZzmt4|7tf-TUgjBq%l8Tg6l%)8SPMRX5Dfl0A-p>V7
zlr$wtiIPq#5mM=aN-9xONs{`?ItjKUxQ|`=p-L)KQdyGvr*#tS7;#C{b(J(tNz;-v
zFr$-Z2x;cAN}8dh8A%$vtdlMi(&Z;A=`tl<mZYI8I_U}_U3sRGu29kyNgBSYldcld
z)fJU=m6EPX(#SQPbd8X%Jy%KBDCwFcC9mtG>x6Xu6P0wGlCDcqs-lxBgj9K{k}8x`
zktBOoC(RPl?58SemXc;ADSbmH-5{hJf1;9ZP|^)a%G}gRHwo$HE0uJUl5R>;wyKk=
zgjD@gl~kpqs!JM-)pSygkZP}0QjL;ok`$lQNpplW_eLenQPP|wCFXU~JR!}ms-$^J
znwO-$1)a1&NDF_ak`^dwL6Z6xb<!dsE&jPmTBM{!NgBANlWq~xtuIv4ElRp2NrSg_
z(rrSz{iRB}O-Z*UY3Pnlx<g2JzEVkdDCv$Q4KL}WB|=(ytCE%|X-SesmUYrHAua!f
zN?N9*Wl2ij)k${=>F!^uq`Q=KSCUfqbkaRSy7yNq=^iEBlO+4TPP$J>_kXF9?o-lz
zNlHJ^Ne>9=!PhG30VO?<q|8H|^pKDqexs5eQqn_7%0ALbj|l0}uT;__N_ymyhGKP{
zR41hRw<@VlNp(qzKh{Z)3F+~7D(NvLJ(i@z6P@&gke>WnB|V{}Cz90nR3|+pq^Eza
zlAco1Q%UN7rjwo#(zCx&NzW+hnIsLY=%f`wTKQX*v_eTMk~H{SCp{;m=f6=&&nfA-
zBn`dLNiPWL#owu<7nJk@NYS0JX%;pBS2MAMA-4MB23p*=6e(=sJ8Ic4L9p$^V<GFG
zzicsl{4)D{OmB{wKZkz~n?X2khS|=LKfv8Thh4h`emKG~{)hdn2fH8tAI<ys{Gz{M
z_zcevegxq+E&hS^Wf*_&x#u1H638F<J@3xHg*9)UP52tvEB+t`-zwo8HE?eY>~pTH
z+5zYj7HQ$vR@iTjBw?d7-@}Z@$>wF)o;{tkU;_efm}Z-odm4KhP5AYZ%Ia94m@C4!
z0v!S;X_Jl6I_q8dUD(_X8?TSdLi%!FwWBd$LhYdYs~y3B<+EU;4p;+t54I6GBOiv!
z>dEXC8<qpGfT>Jj26h%D&|9fE(hzCD?beaZ&RN_*7b$e%qgYuDm18mZOq5KQpqr!R
z*f2NX5i<?AvR#g+4ftIX5D7>0p@7b#<*anxgB!W?r753Pv%(QOz>-wnoId5pH0X)<
zn)v^l;QwMxrSQhan{?2CZR}GS)LFb4#hYBPvf4kMN<%UH$8h|xp9p(`?G5-SY`3<I
znl+<lnDBI4G#24+ua7;d`wN$5+^9CV%1@$#RzolTXiQ}_F;Sd`Rdvn|!1;o$>#&E4
z_(rUjQS%f3C;nit_cbFY>`MhVrUAS+kNMgEv)>5zMp(>&(zNYX6M{TgJVV!wx?u);
k4HL_0D`%79y!#9|m3SZ}4*20fB#f^~_-_Ll_+6a;1CLN!@c;k-
literal 0
HcmV?d00001
diff --git a/tests/data/acpi/q35/FACP.type4-count b/tests/data/acpi/q35/FACP.type4-count
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..31fa5dd19c213034eef4eeefa6a04e61dadd8a2a 100644
GIT binary patch
literal 244
zcmZ>BbPo8!z`($~*~#D8BUr&HBEVSz2pEB4AU24G0Y(N+hD|^Y6El!tgNU*~X%LSC
z$X0-fGcm9T0LA|E|L2FOWMD92VqjR>!otAF!NBm72O<iWged~jj0!*k$y^{03>bk1
YBHITON2VDSAnpK(F*YFF1LDH~0O^Si0RR91
literal 0
HcmV?d00001
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 12/78] tests: bios-tables-test: Prepare the ACPI table change for smbios type4 core count test
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (10 preceding siblings ...)
2023-10-19 18:21 ` [PULL v2 11/78] tests: bios-tables-test: Add ACPI table binaries for smbios type4 count test Michael S. Tsirkin
@ 2023-10-19 18:21 ` Michael S. Tsirkin
2023-10-19 18:21 ` [PULL v2 13/78] tests: bios-tables-test: Add test for smbios type4 core count Michael S. Tsirkin
` (66 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:21 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Zhao Liu, Igor Mammedov, Ani Sinha
From: Zhao Liu <zhao1.liu@intel.com>
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 1 - 3.
List the ACPI tables that will be added to test the type 4 core count
field.
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Message-Id: <20230928125943.1816922-6-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
tests/qtest/bios-tables-test-allowed-diff.h | 3 +++
tests/data/acpi/q35/APIC.core-count | 0
tests/data/acpi/q35/DSDT.core-count | 0
tests/data/acpi/q35/FACP.core-count | 0
4 files changed, 3 insertions(+)
create mode 100644 tests/data/acpi/q35/APIC.core-count
create mode 100644 tests/data/acpi/q35/DSDT.core-count
create mode 100644 tests/data/acpi/q35/FACP.core-count
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..b9bc196130 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1 +1,4 @@
/* List of comma-separated changed AML files to ignore */
+"tests/data/acpi/q35/APIC.core-count",
+"tests/data/acpi/q35/DSDT.core-count",
+"tests/data/acpi/q35/FACP.core-count",
diff --git a/tests/data/acpi/q35/APIC.core-count b/tests/data/acpi/q35/APIC.core-count
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/tests/data/acpi/q35/DSDT.core-count b/tests/data/acpi/q35/DSDT.core-count
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/tests/data/acpi/q35/FACP.core-count b/tests/data/acpi/q35/FACP.core-count
new file mode 100644
index 0000000000..e69de29bb2
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 13/78] tests: bios-tables-test: Add test for smbios type4 core count
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (11 preceding siblings ...)
2023-10-19 18:21 ` [PULL v2 12/78] tests: bios-tables-test: Prepare the ACPI table change for smbios type4 core " Michael S. Tsirkin
@ 2023-10-19 18:21 ` Michael S. Tsirkin
2023-10-19 18:21 ` [PULL v2 14/78] tests: bios-tables-test: Add ACPI table binaries for smbios type4 core count test Michael S. Tsirkin
` (65 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:21 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Zhao Liu, Igor Mammedov, Ani Sinha
From: Zhao Liu <zhao1.liu@intel.com>
This tests the commit 196ea60a734c3 ("hw/smbios: Fix core count in
type4").
In smbios_build_type_4_table() (hw/smbios/smbios.c), if the number of
cores in the socket is not more than 255, then smbios type4 table
encodes cores per socket into the core count field.
So for the topology in this case, there're the following considerations:
1. cores per socket should be not more than 255 to ensure we could cover
the core count field.
2. The original bug was that cores per socket was miscalculated, so now
we should include as many topology levels as possible (mutiple
sockets & dies, no module since x86 hasn't supported it) to cover
more general topology scenarios, to ensure that the cores per socket
encoded in the core count field is correct.
Based on these considerations, select the topology with multiple sockets
and dies:
-smp 54,sockets=2,dies=3,cores=3,threads=3
The expected core count = cores per socket = cores (3) * dies (3) = 9.
Suggested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Message-Id: <20230928125943.1816922-7-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
tests/qtest/bios-tables-test.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index cdbfb51559..c20f6f73d0 100644
--- a/tests/qtest/bios-tables-test.c
+++ b/tests/qtest/bios-tables-test.c
@@ -999,6 +999,23 @@ static void test_acpi_q35_tcg_type4_count(void)
free_test_data(&data);
}
+static void test_acpi_q35_tcg_core_count(void)
+{
+ test_data data = {
+ .machine = MACHINE_Q35,
+ .variant = ".core-count",
+ .required_struct_types = base_required_struct_types,
+ .required_struct_types_len = ARRAY_SIZE(base_required_struct_types),
+ .smbios_core_count = 9,
+ .smbios_core_count2 = 9,
+ };
+
+ test_acpi_one("-machine smbios-entry-point-type=64 "
+ "-smp 54,sockets=2,dies=3,cores=3,threads=3",
+ &data);
+ free_test_data(&data);
+}
+
static void test_acpi_q35_tcg_core_count2(void)
{
test_data data = {
@@ -2178,6 +2195,8 @@ int main(int argc, char *argv[])
qtest_add_func("acpi/q35/kvm/dmar", test_acpi_q35_kvm_dmar);
qtest_add_func("acpi/q35/type4-count",
test_acpi_q35_tcg_type4_count);
+ qtest_add_func("acpi/q35/core-count",
+ test_acpi_q35_tcg_core_count);
qtest_add_func("acpi/q35/core-count2",
test_acpi_q35_tcg_core_count2);
}
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 14/78] tests: bios-tables-test: Add ACPI table binaries for smbios type4 core count test
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (12 preceding siblings ...)
2023-10-19 18:21 ` [PULL v2 13/78] tests: bios-tables-test: Add test for smbios type4 core count Michael S. Tsirkin
@ 2023-10-19 18:21 ` Michael S. Tsirkin
2023-10-19 18:21 ` [PULL v2 15/78] tests: bios-tables-test: Prepare the ACPI table change for smbios type4 core count2 test Michael S. Tsirkin
` (64 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:21 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Zhao Liu, Igor Mammedov, Ani Sinha
From: Zhao Liu <zhao1.liu@intel.com>
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 5 and 6.
Changes in the tables:
FACP:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembly of /tmp/aml-Y6WW91, Wed Aug 23 15:43:43 2023
+ *
+ * ACPI Data Table [FACP]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)]
+[004h 0004 4] Table Length : 000000F4
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : B3
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPC "
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] FACS Address : 00000000
+[028h 0040 4] DSDT Address : 00000000
+[02Ch 0044 1] Model : 01
+[02Dh 0045 1] PM Profile : 00 [Unspecified]
+[02Eh 0046 2] SCI Interrupt : 0009
+[030h 0048 4] SMI Command Port : 000000B2
+[034h 0052 1] ACPI Enable Value : 02
+[035h 0053 1] ACPI Disable Value : 03
+[036h 0054 1] S4BIOS Command : 00
+[037h 0055 1] P-State Control : 00
+[038h 0056 4] PM1A Event Block Address : 00000600
+[03Ch 0060 4] PM1B Event Block Address : 00000000
+[040h 0064 4] PM1A Control Block Address : 00000604
+[044h 0068 4] PM1B Control Block Address : 00000000
+[048h 0072 4] PM2 Control Block Address : 00000000
+[04Ch 0076 4] PM Timer Block Address : 00000608
+[050h 0080 4] GPE0 Block Address : 00000620
+[054h 0084 4] GPE1 Block Address : 00000000
+[058h 0088 1] PM1 Event Block Length : 04
+[059h 0089 1] PM1 Control Block Length : 02
+[05Ah 0090 1] PM2 Control Block Length : 00
+[05Bh 0091 1] PM Timer Block Length : 04
+[05Ch 0092 1] GPE0 Block Length : 10
+[05Dh 0093 1] GPE1 Block Length : 00
+[05Eh 0094 1] GPE1 Base Offset : 00
+[05Fh 0095 1] _CST Support : 00
+[060h 0096 2] C2 Latency : 0FFF
+[062h 0098 2] C3 Latency : 0FFF
+[064h 0100 2] CPU Cache Size : 0000
+[066h 0102 2] Cache Flush Stride : 0000
+[068h 0104 1] Duty Cycle Offset : 00
+[069h 0105 1] Duty Cycle Width : 00
+[06Ah 0106 1] RTC Day Alarm Index : 00
+[06Bh 0107 1] RTC Month Alarm Index : 00
+[06Ch 0108 1] RTC Century Index : 32
+[06Dh 0109 2] Boot Flags (decoded below) : 0002
+ Legacy Devices Supported (V2) : 0
+ 8042 Present on ports 60/64 (V2) : 1
+ VGA Not Present (V4) : 0
+ MSI Not Supported (V4) : 0
+ PCIe ASPM Not Supported (V4) : 0
+ CMOS RTC Not Present (V5) : 0
+[06Fh 0111 1] Reserved : 00
+[070h 0112 4] Flags (decoded below) : 000484A5
+ WBINVD instruction is operational (V1) : 1
+ WBINVD flushes all caches (V1) : 0
+ All CPUs support C1 (V1) : 1
+ C2 works on MP system (V1) : 0
+ Control Method Power Button (V1) : 0
+ Control Method Sleep Button (V1) : 1
+ RTC wake not in fixed reg space (V1) : 0
+ RTC can wake system from S4 (V1) : 1
+ 32-bit PM Timer (V1) : 0
+ Docking Supported (V1) : 0
+ Reset Register Supported (V2) : 1
+ Sealed Case (V3) : 0
+ Headless - No Video (V3) : 0
+ Use native instr after SLP_TYPx (V3) : 0
+ PCIEXP_WAK Bits Supported (V4) : 0
+ Use Platform Timer (V4) : 1
+ RTC_STS valid on S4 wake (V4) : 0
+ Remote Power-on capable (V4) : 0
+ Use APIC Cluster Model (V4) : 1
+ Use APIC Physical Destination Mode (V4) : 0
+ Hardware Reduced (V5) : 0
+ Low Power S0 Idle (V5) : 0
+
+[074h 0116 12] Reset Register : [Generic Address Structure]
+[074h 0116 1] Space ID : 01 [SystemIO]
+[075h 0117 1] Bit Width : 08
+[076h 0118 1] Bit Offset : 00
+[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy]
+[078h 0120 8] Address : 0000000000000CF9
+
+[080h 0128 1] Value to cause reset : 0F
+[081h 0129 2] ARM Flags (decoded below) : 0000
+ PSCI Compliant : 0
+ Must use HVC for PSCI : 0
+
+[083h 0131 1] FADT Minor Revision : 00
+[084h 0132 8] FACS Address : 0000000000000000
+[08Ch 0140 8] DSDT Address : 0000000000000000
+[094h 0148 12] PM1A Event Block : [Generic Address Structure]
+[094h 0148 1] Space ID : 01 [SystemIO]
+[095h 0149 1] Bit Width : 20
+[096h 0150 1] Bit Offset : 00
+[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy]
+[098h 0152 8] Address : 0000000000000600
+
+[0A0h 0160 12] PM1B Event Block : [Generic Address Structure]
+[0A0h 0160 1] Space ID : 00 [SystemMemory]
+[0A1h 0161 1] Bit Width : 00
+[0A2h 0162 1] Bit Offset : 00
+[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0A4h 0164 8] Address : 0000000000000000
+
+[0ACh 0172 12] PM1A Control Block : [Generic Address Structure]
+[0ACh 0172 1] Space ID : 01 [SystemIO]
+[0ADh 0173 1] Bit Width : 10
+[0AEh 0174 1] Bit Offset : 00
+[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0B0h 0176 8] Address : 0000000000000604
+
+[0B8h 0184 12] PM1B Control Block : [Generic Address Structure]
+[0B8h 0184 1] Space ID : 00 [SystemMemory]
+[0B9h 0185 1] Bit Width : 00
+[0BAh 0186 1] Bit Offset : 00
+[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0BCh 0188 8] Address : 0000000000000000
+
+[0C4h 0196 12] PM2 Control Block : [Generic Address Structure]
+[0C4h 0196 1] Space ID : 00 [SystemMemory]
+[0C5h 0197 1] Bit Width : 00
+[0C6h 0198 1] Bit Offset : 00
+[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0C8h 0200 8] Address : 0000000000000000
+
+[0D0h 0208 12] PM Timer Block : [Generic Address Structure]
+[0D0h 0208 1] Space ID : 01 [SystemIO]
+[0D1h 0209 1] Bit Width : 20
+[0D2h 0210 1] Bit Offset : 00
+[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0D4h 0212 8] Address : 0000000000000608
+
+[0DCh 0220 12] GPE0 Block : [Generic Address Structure]
+[0DCh 0220 1] Space ID : 01 [SystemIO]
+[0DDh 0221 1] Bit Width : 80
+[0DEh 0222 1] Bit Offset : 00
+[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0E0h 0224 8] Address : 0000000000000620
+
+[0E8h 0232 12] GPE1 Block : [Generic Address Structure]
+[0E8h 0232 1] Space ID : 00 [SystemMemory]
+[0E9h 0233 1] Bit Width : 00
+[0EAh 0234 1] Bit Offset : 00
+[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0ECh 0236 8] Address : 0000000000000000
...
APIC:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembly of /tmp/aml-FFXW91, Wed Aug 23 15:43:43 2023
+ *
+ * ACPI Data Table [APIC]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)]
+[004h 0004 4] Table Length : 00000220
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : 3C
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPC "
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Local Apic Address : FEE00000
+[028h 0040 4] Flags (decoded below) : 00000001
+ PC-AT Compatibility : 1
+
+[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC]
+[02Dh 0045 1] Length : 08
+[02Eh 0046 1] Processor ID : 00
+[02Fh 0047 1] Local Apic ID : 00
+[030h 0048 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
[snip]
+[1D4h 0468 1] Subtable Type : 00 [Processor Local APIC]
+[1D5h 0469 1] Length : 08
+[1D6h 0470 1] Processor ID : 35
+[1D7h 0471 1] Local Apic ID : 6A
+[1D8h 0472 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
+
+[1DCh 0476 1] Subtable Type : 01 [I/O APIC]
+[1DDh 0477 1] Length : 0C
+[1DEh 0478 1] I/O Apic ID : 00
+[1DFh 0479 1] Reserved : 00
+[1E0h 0480 4] Address : FEC00000
+[1E4h 0484 4] Interrupt : 00000000
+
+[1E8h 0488 1] Subtable Type : 02 [Interrupt Source Override]
+[1E9h 0489 1] Length : 0A
+[1EAh 0490 1] Bus : 00
+[1EBh 0491 1] Source : 00
+[1ECh 0492 4] Interrupt : 00000002
+[1F0h 0496 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+
+[1F2h 0498 1] Subtable Type : 02 [Interrupt Source Override]
+[1F3h 0499 1] Length : 0A
+[1F4h 0500 1] Bus : 00
+[1F5h 0501 1] Source : 05
+[1F6h 0502 4] Interrupt : 00000005
+[1FAh 0506 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[1FCh 0508 1] Subtable Type : 02 [Interrupt Source Override]
+[1FDh 0509 1] Length : 0A
+[1FEh 0510 1] Bus : 00
+[1FFh 0511 1] Source : 09
+[200h 0512 4] Interrupt : 00000009
+[204h 0516 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[206h 0518 1] Subtable Type : 02 [Interrupt Source Override]
+[207h 0519 1] Length : 0A
+[208h 0520 1] Bus : 00
+[209h 0521 1] Source : 0A
+[20Ah 0522 4] Interrupt : 0000000A
+[20Eh 0526 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[210h 0528 1] Subtable Type : 02 [Interrupt Source Override]
+[211h 0529 1] Length : 0A
+[212h 0530 1] Bus : 00
+[213h 0531 1] Source : 0B
+[214h 0532 4] Interrupt : 0000000B
+[218h 0536 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[21Ah 0538 1] Subtable Type : 04 [Local APIC NMI]
+[21Bh 0539 1] Length : 06
+[21Ch 0540 1] Processor ID : FF
+[21Dh 0541 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+[21Fh 0543 1] Interrupt Input LINT : 01
...
DSDT:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembling to symbolic ASL+ operators
+ *
+ * Disassembly of /tmp/aml-9ZXW91, Wed Aug 23 15:43:43 2023
+ *
+ * Original Table Header:
+ * Signature "DSDT"
+ * Length 0x00003271 (12913)
+ * Revision 0x01 **** 32-bit table (V1), no 64-bit math support
+ * Checksum 0xAF
+ * OEM ID "BOCHS "
+ * OEM Table ID "BXPC "
+ * OEM Revision 0x00000001 (1)
+ * Compiler ID "BXPC"
+ * Compiler Version 0x00000001 (1)
+ */
+DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001)
+{
+ Scope (\)
+ {
+ OperationRegion (DBG, SystemIO, 0x0402, One)
+ Field (DBG, ByteAcc, NoLock, Preserve)
+ {
+ DBGB, 8
+ }
+
+ Method (DBUG, 1, NotSerialized)
+ {
+ ToHexString (Arg0, Local0)
+ ToBuffer (Local0, Local0)
+ Local1 = (SizeOf (Local0) - One)
+ Local2 = Zero
+ While ((Local2 < Local1))
+ {
+ DBGB = DerefOf (Local0 [Local2])
+ Local2++
+ }
+
+ DBGB = 0x0A
+ }
+ }
[snip]
+ Device (\_SB.CPUS)
+ {
+ Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
+ Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID
+ Method (CTFY, 2, NotSerialized)
+ {
+ If ((Arg0 == Zero))
+ {
+ Notify (C000, Arg1)
+ }
+
+ If ((Arg0 == One))
+ {
+ Notify (C001, Arg1)
+ }
[snip]
+ If ((Arg0 == 0x35))
+ {
+ Notify (C035, Arg1)
+ }
+ }
[snip]
+ Processor (C000, 0x00, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (Zero))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........
+ })
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (Zero, Arg0, Arg1, Arg2)
+ }
+ }
+
+ Processor (C001, 0x01, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (One))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00 // ........
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (One)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (One, Arg0, Arg1, Arg2)
+ }
+ }
[snip]
+ Processor (C035, 0x35, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (0x35))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x35, 0x6A, 0x01, 0x00, 0x00, 0x00 // ..5j....
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (0x35)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (0x35, Arg0, Arg1, Arg2)
+ }
+ }
...
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Message-Id: <20230928125943.1816922-8-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
tests/qtest/bios-tables-test-allowed-diff.h | 3 ---
tests/data/acpi/q35/APIC.core-count | Bin 0 -> 544 bytes
tests/data/acpi/q35/DSDT.core-count | Bin 0 -> 12913 bytes
tests/data/acpi/q35/FACP.core-count | Bin 0 -> 244 bytes
4 files changed, 3 deletions(-)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index b9bc196130..dfb8523c8b 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1,4 +1 @@
/* List of comma-separated changed AML files to ignore */
-"tests/data/acpi/q35/APIC.core-count",
-"tests/data/acpi/q35/DSDT.core-count",
-"tests/data/acpi/q35/FACP.core-count",
diff --git a/tests/data/acpi/q35/APIC.core-count b/tests/data/acpi/q35/APIC.core-count
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..d9d7ca9a896159791f6e74842d02786dc2608cb3 100644
GIT binary patch
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literal 0
HcmV?d00001
diff --git a/tests/data/acpi/q35/DSDT.core-count b/tests/data/acpi/q35/DSDT.core-count
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..a24b04cbdbf09383b933a42a2a15182545543a87 100644
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zf~0GVbnS;G=^7_p^GVM2An7_IUH?0ibe)r~`=s)XAn67p-RPL48=Q2*Csl3+NjDkk
z=8j3a$w@bTQgtavT4JQ7U6ZuLNlQJ_vb&tq)>8Pva!)yPk4;jJlX5;OpAYtwXQcc`
zCMnNJd7o4$1W5%(D*VVK6*#Hjla`l*q-920-Zx3hoV4tdR#t+f6-HV)Fi9(%wBnOi
zSA(QgMp}Jhl2$os6{O5GHbSwf+pgpa!ri{5O;OsTN!3QxE~)%=uiO&88@K=ci=+st
zCB-R~x7MsTi8l!=hT~R3u7dxFr{5%ceiA<h7UK8vr`l?jjC-S}r)q&CL`Y~q;*Q~W
z%D<I!3GuJmGq3UM?mww#UjOYYe7;pRH&$*I(2tzevd}v!XdeN4*R4Y*f;rVM=;iOo
zi`cwY`_gorZAfFweY<F5u|=EUazi@Xm+iCgi}Kdt-AH}C-jEyH1_USRjLq#J>viIF
z!kWNl`jtm0-&}5|`y#Yk0ehvLjz#Q{jZF!7tMm+wk@{=@WoRAVtbX9An;*#smD)q>
zq7*3F=r|QkMQIB?RhfPyf1_QSqF1qX7;ols?O3~5ZeW_L&D<U3;1#n3zQs55Wr5$S
z!zg&hG8vdW)2#Zzv$Q$C(RdKDJ9Z-FL}ZcH%fDI*QyGe+XDzyCjr;2lO7!5+LpdgJ
zYvMtL>?%F1(ZhPIb+~e`R7NxEKRAT3cS19{w<0F&(KV|hI>N%+?Xh@_zjGn^s?OK$
zKkQ`<VMW8TVs><n{v$x^u&`O*#uY@dBRF5U9fAEK7Mrq@Yu3-gKMTiVb1x*h;M}kE
za-xVnJLgUKO<2U{QZi?uvF-G_iK7m^g(SKwy26Uh35(hpYF3Nxc@GJkN;*(-4}@_b
Pm7vcgZUt5Fe;xh|kQQ*J
literal 0
HcmV?d00001
diff --git a/tests/data/acpi/q35/FACP.core-count b/tests/data/acpi/q35/FACP.core-count
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..31fa5dd19c213034eef4eeefa6a04e61dadd8a2a 100644
GIT binary patch
literal 244
zcmZ>BbPo8!z`($~*~#D8BUr&HBEVSz2pEB4AU24G0Y(N+hD|^Y6El!tgNU*~X%LSC
z$X0-fGcm9T0LA|E|L2FOWMD92VqjR>!otAF!NBm72O<iWged~jj0!*k$y^{03>bk1
YBHITON2VDSAnpK(F*YFF1LDH~0O^Si0RR91
literal 0
HcmV?d00001
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 15/78] tests: bios-tables-test: Prepare the ACPI table change for smbios type4 core count2 test
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (13 preceding siblings ...)
2023-10-19 18:21 ` [PULL v2 14/78] tests: bios-tables-test: Add ACPI table binaries for smbios type4 core count test Michael S. Tsirkin
@ 2023-10-19 18:21 ` Michael S. Tsirkin
2023-10-19 18:21 ` [PULL v2 16/78] tests: bios-tables-test: Extend smbios core count2 test to cover general topology Michael S. Tsirkin
` (63 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:21 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Zhao Liu, Igor Mammedov, Ani Sinha
From: Zhao Liu <zhao1.liu@intel.com>
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 1 - 3.
List the ACPI tables that will be changed about the type 4 core count2
test case.
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Message-Id: <20230928125943.1816922-9-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
tests/qtest/bios-tables-test-allowed-diff.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..0f95d1344b 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1 +1,3 @@
/* List of comma-separated changed AML files to ignore */
+"tests/data/acpi/q35/APIC.core-count2",
+"tests/data/acpi/q35/DSDT.core-count2",
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 16/78] tests: bios-tables-test: Extend smbios core count2 test to cover general topology
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (14 preceding siblings ...)
2023-10-19 18:21 ` [PULL v2 15/78] tests: bios-tables-test: Prepare the ACPI table change for smbios type4 core count2 test Michael S. Tsirkin
@ 2023-10-19 18:21 ` Michael S. Tsirkin
2023-10-19 18:21 ` [PULL v2 17/78] tests: bios-tables-test: Update ACPI table binaries for smbios core count2 test Michael S. Tsirkin
` (62 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:21 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Zhao Liu, Igor Mammedov, Ani Sinha
From: Zhao Liu <zhao1.liu@intel.com>
The commit 196ea60a734c3 ("hw/smbios: Fix core count in type4") fixed
the miscalculation of cores per socket.
The original core count2 test (with the topology configured by
"-smp 275") didn't recognize that topology-related but because it just
created a special topology with only one socket and one die by default,
ignoring the effect of more topology levels (between socket and core) on
the cores per socket calculation.
So for the topology in this case, there're the following considerations:
1. cores per socket should be more than 255 to ensure we could cover
the core count2 field.
2. The original bug was that cores per socket was miscalculated, so now
we should include as many topology levels as possible (mutiple
sockets or dies, no module since x86 hasn't supported it) to cover
more general topology scenarios, to ensure that the cores per socket
encoded in the core count2 field is correct.
Based on these considerations, select the topology with multiple dies:
-smp 260,dies=2,cores=130,threads=1
Note, here we doesn't configure multiple sockets to avoid the error
("kvm_init_vcpu: kvm_get_vcpu failed (*): Too many open files") if user
uses the default ulimit seeting on his machine.
And the cores per socket calculation for multiple sockets has already
been covered by the core count test case, so that only multiple dies
configuration is enough.
The expected core count2 = cores per socket = cores (130) * dies (2) =
260.
Suggested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Acked-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <20230928125943.1816922-10-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
tests/qtest/bios-tables-test.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index c20f6f73d0..f3af20cf2c 100644
--- a/tests/qtest/bios-tables-test.c
+++ b/tests/qtest/bios-tables-test.c
@@ -1024,10 +1024,12 @@ static void test_acpi_q35_tcg_core_count2(void)
.required_struct_types = base_required_struct_types,
.required_struct_types_len = ARRAY_SIZE(base_required_struct_types),
.smbios_core_count = 0xFF,
- .smbios_core_count2 = 275,
+ .smbios_core_count2 = 260,
};
- test_acpi_one("-machine smbios-entry-point-type=64 -smp 275", &data);
+ test_acpi_one("-machine smbios-entry-point-type=64 "
+ "-smp 260,dies=2,cores=130,threads=1",
+ &data);
free_test_data(&data);
}
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 17/78] tests: bios-tables-test: Update ACPI table binaries for smbios core count2 test
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (15 preceding siblings ...)
2023-10-19 18:21 ` [PULL v2 16/78] tests: bios-tables-test: Extend smbios core count2 test to cover general topology Michael S. Tsirkin
@ 2023-10-19 18:21 ` Michael S. Tsirkin
2023-10-19 18:21 ` [PULL v2 18/78] tests: bios-tables-test: Prepare the ACPI table change for smbios type4 thread count test Michael S. Tsirkin
` (61 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:21 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Zhao Liu, Igor Mammedov, Ani Sinha
From: Zhao Liu <zhao1.liu@intel.com>
Change the core count2 from 275 to 260.
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 5 and 6.
Changes in the tables:
APIC:
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20200925 (64-bit version)
* Copyright (c) 2000 - 2020 Intel Corporation
*
- * Disassembly of tests/data/acpi/q35/APIC.core-count2, Wed Aug 23 16:29:51 2023
+ * Disassembly of /tmp/aml-KQDX91, Wed Aug 23 16:29:51 2023
*
* ACPI Data Table [APIC]
*
* Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
*/
[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)]
-[004h 0004 4] Table Length : 000009AE
+[004h 0004 4] Table Length : 00000CA6
[008h 0008 1] Revision : 03
-[009h 0009 1] Checksum : CE
+[009h 0009 1] Checksum : FA
[00Ah 0010 6] Oem ID : "BOCHS "
[010h 0016 8] Oem Table ID : "BXPC "
[018h 0024 4] Oem Revision : 00000001
[01Ch 0028 4] Asl Compiler ID : "BXPC"
[020h 0032 4] Asl Compiler Revision : 00000001
[024h 0036 4] Local Apic Address : FEE00000
[028h 0040 4] Flags (decoded below) : 00000001
PC-AT Compatibility : 1
[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC]
[02Dh 0045 1] Length : 08
[02Eh 0046 1] Processor ID : 00
[02Fh 0047 1] Local Apic ID : 00
[030h 0048 4] Flags (decoded below) : 00000001
Processor Enabled : 1
@@ -1051,1256 +1051,1136 @@
[42Ch 1068 1] Subtable Type : 00 [Processor Local APIC]
[42Dh 1069 1] Length : 08
[42Eh 1070 1] Processor ID : 80
[42Fh 1071 1] Local Apic ID : 80
[430h 1072 4] Flags (decoded below) : 00000001
Processor Enabled : 1
Runtime Online Capable : 0
[434h 1076 1] Subtable Type : 00 [Processor Local APIC]
[435h 1077 1] Length : 08
[436h 1078 1] Processor ID : 81
[437h 1079 1] Local Apic ID : 81
[438h 1080 4] Flags (decoded below) : 00000001
Processor Enabled : 1
Runtime Online Capable : 0
-[43Ch 1084 1] Subtable Type : 00 [Processor Local APIC]
-[43Dh 1085 1] Length : 08
-[43Eh 1086 1] Processor ID : 82
-[43Fh 1087 1] Local Apic ID : 82
-[440h 1088 4] Flags (decoded below) : 00000001
- Processor Enabled : 1
- Runtime Online Capable : 0
-
-[444h 1092 1] Subtable Type : 00 [Processor Local APIC]
-[445h 1093 1] Length : 08
-[446h 1094 1] Processor ID : 83
-[447h 1095 1] Local Apic ID : 83
-[448h 1096 4] Flags (decoded below) : 00000001
- Processor Enabled : 1
- Runtime Online Capable : 0
[snip]
-
-[964h 2404 1] Subtable Type : 01 [I/O APIC]
-[965h 2405 1] Length : 0C
-[966h 2406 1] I/O Apic ID : 00
-[967h 2407 1] Reserved : 00
-[968h 2408 4] Address : FEC00000
-[96Ch 2412 4] Interrupt : 00000000
-
-[970h 2416 1] Subtable Type : 02 [Interrupt Source Override]
-[971h 2417 1] Length : 0A
-[972h 2418 1] Bus : 00
-[973h 2419 1] Source : 00
-[974h 2420 4] Interrupt : 00000002
-[978h 2424 2] Flags (decoded below) : 0000
+[43Ch 1084 1] Subtable Type : 09 [Processor Local x2APIC]
+[43Dh 1085 1] Length : 10
+[43Eh 1086 2] Reserved : 0000
+[440h 1088 4] Processor x2Apic ID : 00000100
+[444h 1092 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+[448h 1096 4] Processor UID : 00000082
+
+[44Ch 1100 1] Subtable Type : 09 [Processor Local x2APIC]
+[44Dh 1101 1] Length : 10
+[44Eh 1102 2] Reserved : 0000
+[450h 1104 4] Processor x2Apic ID : 00000101
+[454h 1108 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+[458h 1112 4] Processor UID : 00000083
+
[snip]
+
+[C68h 3176 1] Subtable Type : 02 [Interrupt Source Override]
+[C69h 3177 1] Length : 0A
+[C6Ah 3178 1] Bus : 00
+[C6Bh 3179 1] Source : 00
+[C6Ch 3180 4] Interrupt : 00000002
+[C70h 3184 2] Flags (decoded below) : 0000
Polarity : 0
Trigger Mode : 0
-[97Ah 2426 1] Subtable Type : 02 [Interrupt Source Override]
-[97Bh 2427 1] Length : 0A
-[97Ch 2428 1] Bus : 00
-[97Dh 2429 1] Source : 05
-[97Eh 2430 4] Interrupt : 00000005
-[982h 2434 2] Flags (decoded below) : 000D
+[C72h 3186 1] Subtable Type : 02 [Interrupt Source Override]
+[C73h 3187 1] Length : 0A
+[C74h 3188 1] Bus : 00
+[C75h 3189 1] Source : 05
+[C76h 3190 4] Interrupt : 00000005
+[C7Ah 3194 2] Flags (decoded below) : 000D
Polarity : 1
Trigger Mode : 3
-[984h 2436 1] Subtable Type : 02 [Interrupt Source Override]
-[985h 2437 1] Length : 0A
-[986h 2438 1] Bus : 00
-[987h 2439 1] Source : 09
-[988h 2440 4] Interrupt : 00000009
-[98Ch 2444 2] Flags (decoded below) : 000D
+[C7Ch 3196 1] Subtable Type : 02 [Interrupt Source Override]
+[C7Dh 3197 1] Length : 0A
+[C7Eh 3198 1] Bus : 00
+[C7Fh 3199 1] Source : 09
+[C80h 3200 4] Interrupt : 00000009
+[C84h 3204 2] Flags (decoded below) : 000D
Polarity : 1
Trigger Mode : 3
-[98Eh 2446 1] Subtable Type : 02 [Interrupt Source Override]
-[98Fh 2447 1] Length : 0A
-[990h 2448 1] Bus : 00
-[991h 2449 1] Source : 0A
-[992h 2450 4] Interrupt : 0000000A
-[996h 2454 2] Flags (decoded below) : 000D
+[C86h 3206 1] Subtable Type : 02 [Interrupt Source Override]
+[C87h 3207 1] Length : 0A
+[C88h 3208 1] Bus : 00
+[C89h 3209 1] Source : 0A
+[C8Ah 3210 4] Interrupt : 0000000A
+[C8Eh 3214 2] Flags (decoded below) : 000D
Polarity : 1
Trigger Mode : 3
-[998h 2456 1] Subtable Type : 02 [Interrupt Source Override]
-[999h 2457 1] Length : 0A
-[99Ah 2458 1] Bus : 00
-[99Bh 2459 1] Source : 0B
-[99Ch 2460 4] Interrupt : 0000000B
-[9A0h 2464 2] Flags (decoded below) : 000D
+[C90h 3216 1] Subtable Type : 02 [Interrupt Source Override]
+[C91h 3217 1] Length : 0A
+[C92h 3218 1] Bus : 00
+[C93h 3219 1] Source : 0B
+[C94h 3220 4] Interrupt : 0000000B
+[C98h 3224 2] Flags (decoded below) : 000D
Polarity : 1
Trigger Mode : 3
-[9A2h 2466 1] Subtable Type : 0A [Local x2APIC NMI]
-[9A3h 2467 1] Length : 0C
-[9A4h 2468 2] Flags (decoded below) : 0000
+[C9Ah 3226 1] Subtable Type : 0A [Local x2APIC NMI]
+[C9Bh 3227 1] Length : 0C
+[C9Ch 3228 2] Flags (decoded below) : 0000
Polarity : 0
Trigger Mode : 0
-[9A6h 2470 4] Processor UID : FFFFFFFF
-[9AAh 2474 1] Interrupt Input LINT : 01
-[9ABh 2475 3] Reserved : 000000
+[C9Eh 3230 4] Processor UID : FFFFFFFF
+[CA2h 3234 1] Interrupt Input LINT : 01
+[CA3h 3235 3] Reserved : 000000
...
DSDT:
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20200925 (64-bit version)
* Copyright (c) 2000 - 2020 Intel Corporation
*
* Disassembling to symbolic ASL+ operators
*
- * Disassembly of tests/data/acpi/q35/DSDT.core-count2, Wed Aug 23 16:29:51 2023
+ * Disassembly of /tmp/aml-6DDX91, Wed Aug 23 16:29:51 2023
*
* Original Table Header:
* Signature "DSDT"
- * Length 0x00007EEF (32495)
+ * Length 0x000083EA (33770)
* Revision 0x01 **** 32-bit table (V1), no 64-bit math support
- * Checksum 0x52
+ * Checksum 0x01
* OEM ID "BOCHS "
* OEM Table ID "BXPC "
* OEM Revision 0x00000001 (1)
* Compiler ID "BXPC"
* Compiler Version 0x00000001 (1)
*/
DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001)
{
Scope (\)
{
OperationRegion (DBG, SystemIO, 0x0402, One)
Field (DBG, ByteAcc, NoLock, Preserve)
{
DBGB, 8
}
@@ -4196,107 +4196,32 @@
}
If ((Arg0 == 0x0101))
{
Notify (C101, Arg1)
}
If ((Arg0 == 0x0102))
{
Notify (C102, Arg1)
}
If ((Arg0 == 0x0103))
{
Notify (C103, Arg1)
}
-
- If ((Arg0 == 0x0104))
- {
- Notify (C104, Arg1)
- }
-
- If ((Arg0 == 0x0105))
- {
- Notify (C105, Arg1)
- }
-
- If ((Arg0 == 0x0106))
- {
- Notify (C106, Arg1)
- }
-
[snip]
- If ((Arg0 == 0x0112))
- {
- Notify (C112, Arg1)
- }
}
Method (CSTA, 1, Serialized)
{
Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
\_SB.PCI0.PRES.CSEL = Arg0
Local0 = Zero
If ((\_SB.PCI0.PRES.CPEN == One))
{
Local0 = 0x0F
}
Release (\_SB.PCI0.PRES.CPLK)
Return (Local0)
}
@@ -4306,33 +4231,33 @@
\_SB.PCI0.PRES.CSEL = Arg0
\_SB.PCI0.PRES.CEJ0 = One
Release (\_SB.PCI0.PRES.CPLK)
}
Method (CSCN, 0, Serialized)
{
Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
Name (CNEW, Package (0xFF) {})
Local3 = Zero
Local4 = One
While ((Local4 == One))
{
Local4 = Zero
Local0 = One
Local1 = Zero
- While (((Local0 == One) && (Local3 < 0x0113)))
+ While (((Local0 == One) && (Local3 < 0x0104)))
{
Local0 = Zero
\_SB.PCI0.PRES.CSEL = Local3
\_SB.PCI0.PRES.CCMD = Zero
If ((\_SB.PCI0.PRES.CDAT < Local3))
{
Break
}
If ((Local1 == 0xFF))
{
Local4 = One
Break
}
Local3 = \_SB.PCI0.PRES.CDAT
@@ -7220,3281 +7145,3281 @@
Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
{
0x00, 0x08, 0x81, 0x81, 0x01, 0x00, 0x00, 0x00 // ........
})
Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
{
CEJ0 (0x81)
}
Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
{
COST (0x81, Arg0, Arg1, Arg2)
}
}
- Processor (C082, 0x82, 0x00000000, 0x00)
+ Device (C082)
{
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
+ Name (_UID, 0x82) // _UID: Unique ID
Method (_STA, 0, Serialized) // _STA: Status
{
Return (CSTA (0x82))
}
- Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ Name (_MAT, Buffer (0x10) // _MAT: Multiple APIC Table Entry
{
- 0x00, 0x08, 0x82, 0x82, 0x01, 0x00, 0x00, 0x00 // ........
+ /* 0000 */ 0x09, 0x10, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, // ........
+ /* 0008 */ 0x01, 0x00, 0x00, 0x00, 0x82, 0x00, 0x00, 0x00 // ........
})
Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
{
CEJ0 (0x82)
}
Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
{
COST (0x82, Arg0, Arg1, Arg2)
}
}
- Processor (C083, 0x83, 0x00000000, 0x00)
+ Device (C083)
{
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
+ Name (_UID, 0x83) // _UID: Unique ID
Method (_STA, 0, Serialized) // _STA: Status
{
Return (CSTA (0x83))
}
- Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ Name (_MAT, Buffer (0x10) // _MAT: Multiple APIC Table Entry
{
- 0x00, 0x08, 0x83, 0x83, 0x01, 0x00, 0x00, 0x00 // ........
+ /* 0000 */ 0x09, 0x10, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, // ........
+ /* 0008 */ 0x01, 0x00, 0x00, 0x00, 0x83, 0x00, 0x00, 0x00 // ........
})
Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
{
CEJ0 (0x83)
}
Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
{
COST (0x83, Arg0, Arg1, Arg2)
}
}
- Processor (C084, 0x84, 0x00000000, 0x00)
+ Device (C084)
{
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
+ Name (_UID, 0x84) // _UID: Unique ID
Method (_STA, 0, Serialized) // _STA: Status
{
Return (CSTA (0x84))
}
- Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ Name (_MAT, Buffer (0x10) // _MAT: Multiple APIC Table Entry
{
- 0x00, 0x08, 0x84, 0x84, 0x01, 0x00, 0x00, 0x00 // ........
+ /* 0000 */ 0x09, 0x10, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, // ........
+ /* 0008 */ 0x01, 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0x00 // ........
})
Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
{
CEJ0 (0x84)
}
Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
{
COST (0x84, Arg0, Arg1, Arg2)
}
}
[snip]
- Processor (C0FE, 0xFE, 0x00000000, 0x00)
+ Device (C0FE)
{
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
+ Name (_UID, 0xFE) // _UID: Unique ID
Method (_STA, 0, Serialized) // _STA: Status
{
Return (CSTA (0xFE))
}
- Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ Name (_MAT, Buffer (0x10) // _MAT: Multiple APIC Table Entry
{
- 0x00, 0x08, 0xFE, 0xFE, 0x01, 0x00, 0x00, 0x00 // ........
+ /* 0000 */ 0x09, 0x10, 0x00, 0x00, 0x7C, 0x01, 0x00, 0x00, // ....|...
+ /* 0008 */ 0x01, 0x00, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x00 // ........
})
Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
{
CEJ0 (0xFE)
}
Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
{
COST (0xFE, Arg0, Arg1, Arg2)
}
}
...
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Message-Id: <20230928125943.1816922-11-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
tests/qtest/bios-tables-test-allowed-diff.h | 2 --
tests/data/acpi/q35/APIC.core-count2 | Bin 2478 -> 3238 bytes
tests/data/acpi/q35/DSDT.core-count2 | Bin 32495 -> 33770 bytes
3 files changed, 2 deletions(-)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index 0f95d1344b..dfb8523c8b 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1,3 +1 @@
/* List of comma-separated changed AML files to ignore */
-"tests/data/acpi/q35/APIC.core-count2",
-"tests/data/acpi/q35/DSDT.core-count2",
diff --git a/tests/data/acpi/q35/APIC.core-count2 b/tests/data/acpi/q35/APIC.core-count2
index f5da2eb1e8a93d961b39f665f2e8b02acf1aeb3c..4f2428443430b7da8321e9edd816219deb7929a2 100644
GIT binary patch
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diff --git a/tests/data/acpi/q35/DSDT.core-count2 b/tests/data/acpi/q35/DSDT.core-count2
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GIT binary patch
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--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 18/78] tests: bios-tables-test: Prepare the ACPI table change for smbios type4 thread count test
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (16 preceding siblings ...)
2023-10-19 18:21 ` [PULL v2 17/78] tests: bios-tables-test: Update ACPI table binaries for smbios core count2 test Michael S. Tsirkin
@ 2023-10-19 18:21 ` Michael S. Tsirkin
2023-10-19 18:22 ` [PULL v2 19/78] tests: bios-tables-test: Add test for smbios type4 thread count Michael S. Tsirkin
` (60 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:21 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Zhao Liu, Igor Mammedov, Ani Sinha
From: Zhao Liu <zhao1.liu@intel.com>
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 1 - 3.
List the ACPI tables that will be added to test the thread count field
of smbios type4 table.
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Message-Id: <20230928125943.1816922-12-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
tests/qtest/bios-tables-test-allowed-diff.h | 3 +++
tests/data/acpi/q35/APIC.thread-count | 0
tests/data/acpi/q35/DSDT.thread-count | 0
tests/data/acpi/q35/FACP.thread-count | 0
4 files changed, 3 insertions(+)
create mode 100644 tests/data/acpi/q35/APIC.thread-count
create mode 100644 tests/data/acpi/q35/DSDT.thread-count
create mode 100644 tests/data/acpi/q35/FACP.thread-count
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..4d139d7f6b 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1 +1,4 @@
/* List of comma-separated changed AML files to ignore */
+"tests/data/acpi/q35/APIC.thread-count",
+"tests/data/acpi/q35/DSDT.thread-count",
+"tests/data/acpi/q35/FACP.thread-count",
diff --git a/tests/data/acpi/q35/APIC.thread-count b/tests/data/acpi/q35/APIC.thread-count
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/tests/data/acpi/q35/DSDT.thread-count b/tests/data/acpi/q35/DSDT.thread-count
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/tests/data/acpi/q35/FACP.thread-count b/tests/data/acpi/q35/FACP.thread-count
new file mode 100644
index 0000000000..e69de29bb2
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 19/78] tests: bios-tables-test: Add test for smbios type4 thread count
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (17 preceding siblings ...)
2023-10-19 18:21 ` [PULL v2 18/78] tests: bios-tables-test: Prepare the ACPI table change for smbios type4 thread count test Michael S. Tsirkin
@ 2023-10-19 18:22 ` Michael S. Tsirkin
2023-10-19 18:22 ` [PULL v2 20/78] tests: bios-tables-test: Add ACPI table binaries for smbios type4 thread count test Michael S. Tsirkin
` (59 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:22 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Zhao Liu, Igor Mammedov, Ani Sinha
From: Zhao Liu <zhao1.liu@intel.com>
This tests the commit 7298fd7de5551 ("hw/smbios: Fix thread count in
type4").
In smbios_build_type_4_table() (hw/smbios/smbios.c), if the number of
threads in the socket is not more than 255, then smbios type4 table
encodes threads per socket into the thread count field.
So for the topology in this case, there're the following considerations:
1. threads per socket should be not more than 255 to ensure we could
cover the thread count field.
2. The original bug was that threads per socket was miscalculated, so
now we should configure as many topology levels as possible (mutiple
sockets & dies, no module since x86 hasn't supported it) to cover
more general topology scenarios, to ensure that the threads per
socket encoded in the thread count field is correct.
3. For the more general topology, we should also add "cpus" (presented
threads for machine) and "maxcpus" (total threads for machine) to
make sure that configuring unpluged CPUs in smp (cpus < maxcpus)
does not affect the correctness of threads per socket for thread
count field.
Based on these considerations, select the topology as the follow:
-smp cpus=15,maxcpus=54,sockets=2,dies=3,cores=3,threads=3
The expected thread count = threads per socket = threads (3) * cores (3)
* dies (3) = 27.
Suggested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Acked-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <20230928125943.1816922-13-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
tests/qtest/bios-tables-test.c | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index f3af20cf2c..395ed7f9ff 100644
--- a/tests/qtest/bios-tables-test.c
+++ b/tests/qtest/bios-tables-test.c
@@ -95,6 +95,7 @@ typedef struct {
uint16_t smbios_cpu_curr_speed;
uint8_t smbios_core_count;
uint16_t smbios_core_count2;
+ uint8_t smbios_thread_count;
uint8_t *required_struct_types;
int required_struct_types_len;
int type4_count;
@@ -640,6 +641,7 @@ static void smbios_cpu_test(test_data *data, uint32_t addr,
SmbiosEntryPointType ep_type)
{
uint8_t core_count, expected_core_count = data->smbios_core_count;
+ uint8_t thread_count, expected_thread_count = data->smbios_thread_count;
uint16_t speed, expected_speed[2];
uint16_t core_count2, expected_core_count2 = data->smbios_core_count2;
int offset[2];
@@ -663,6 +665,13 @@ static void smbios_cpu_test(test_data *data, uint32_t addr,
g_assert_cmpuint(core_count, ==, expected_core_count);
}
+ thread_count = qtest_readb(data->qts,
+ addr + offsetof(struct smbios_type_4, thread_count));
+
+ if (expected_thread_count) {
+ g_assert_cmpuint(thread_count, ==, expected_thread_count);
+ }
+
if (ep_type == SMBIOS_ENTRY_POINT_TYPE_64) {
core_count2 = qtest_readw(data->qts,
addr + offsetof(struct smbios_type_4, core_count2));
@@ -1033,6 +1042,22 @@ static void test_acpi_q35_tcg_core_count2(void)
free_test_data(&data);
}
+static void test_acpi_q35_tcg_thread_count(void)
+{
+ test_data data = {
+ .machine = MACHINE_Q35,
+ .variant = ".thread-count",
+ .required_struct_types = base_required_struct_types,
+ .required_struct_types_len = ARRAY_SIZE(base_required_struct_types),
+ .smbios_thread_count = 27,
+ };
+
+ test_acpi_one("-machine smbios-entry-point-type=64 "
+ "-smp cpus=15,maxcpus=54,sockets=2,dies=3,cores=3,threads=3",
+ &data);
+ free_test_data(&data);
+}
+
static void test_acpi_q35_tcg_bridge(void)
{
test_data data = {};
@@ -2201,6 +2226,8 @@ int main(int argc, char *argv[])
test_acpi_q35_tcg_core_count);
qtest_add_func("acpi/q35/core-count2",
test_acpi_q35_tcg_core_count2);
+ qtest_add_func("acpi/q35/thread-count",
+ test_acpi_q35_tcg_thread_count);
}
if (qtest_has_device("virtio-iommu-pci")) {
qtest_add_func("acpi/q35/viot", test_acpi_q35_viot);
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 20/78] tests: bios-tables-test: Add ACPI table binaries for smbios type4 thread count test
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (18 preceding siblings ...)
2023-10-19 18:22 ` [PULL v2 19/78] tests: bios-tables-test: Add test for smbios type4 thread count Michael S. Tsirkin
@ 2023-10-19 18:22 ` Michael S. Tsirkin
2023-10-19 18:22 ` [PULL v2 21/78] tests: bios-tables-test: Prepare the ACPI table change for smbios type4 thread count2 test Michael S. Tsirkin
` (58 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:22 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Zhao Liu, Igor Mammedov, Ani Sinha
From: Zhao Liu <zhao1.liu@intel.com>
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 5 and 6.
Changes in the tables:
FACP:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembly of /tmp/aml-1NP791, Wed Aug 23 21:51:31 2023
+ *
+ * ACPI Data Table [FACP]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)]
+[004h 0004 4] Table Length : 000000F4
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : B3
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPC "
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] FACS Address : 00000000
+[028h 0040 4] DSDT Address : 00000000
+[02Ch 0044 1] Model : 01
+[02Dh 0045 1] PM Profile : 00 [Unspecified]
+[02Eh 0046 2] SCI Interrupt : 0009
+[030h 0048 4] SMI Command Port : 000000B2
+[034h 0052 1] ACPI Enable Value : 02
+[035h 0053 1] ACPI Disable Value : 03
+[036h 0054 1] S4BIOS Command : 00
+[037h 0055 1] P-State Control : 00
+[038h 0056 4] PM1A Event Block Address : 00000600
+[03Ch 0060 4] PM1B Event Block Address : 00000000
+[040h 0064 4] PM1A Control Block Address : 00000604
+[044h 0068 4] PM1B Control Block Address : 00000000
+[048h 0072 4] PM2 Control Block Address : 00000000
+[04Ch 0076 4] PM Timer Block Address : 00000608
+[050h 0080 4] GPE0 Block Address : 00000620
+[054h 0084 4] GPE1 Block Address : 00000000
+[058h 0088 1] PM1 Event Block Length : 04
+[059h 0089 1] PM1 Control Block Length : 02
+[05Ah 0090 1] PM2 Control Block Length : 00
+[05Bh 0091 1] PM Timer Block Length : 04
+[05Ch 0092 1] GPE0 Block Length : 10
+[05Dh 0093 1] GPE1 Block Length : 00
+[05Eh 0094 1] GPE1 Base Offset : 00
+[05Fh 0095 1] _CST Support : 00
+[060h 0096 2] C2 Latency : 0FFF
+[062h 0098 2] C3 Latency : 0FFF
+[064h 0100 2] CPU Cache Size : 0000
+[066h 0102 2] Cache Flush Stride : 0000
+[068h 0104 1] Duty Cycle Offset : 00
+[069h 0105 1] Duty Cycle Width : 00
+[06Ah 0106 1] RTC Day Alarm Index : 00
+[06Bh 0107 1] RTC Month Alarm Index : 00
+[06Ch 0108 1] RTC Century Index : 32
+[06Dh 0109 2] Boot Flags (decoded below) : 0002
+ Legacy Devices Supported (V2) : 0
+ 8042 Present on ports 60/64 (V2) : 1
+ VGA Not Present (V4) : 0
+ MSI Not Supported (V4) : 0
+ PCIe ASPM Not Supported (V4) : 0
+ CMOS RTC Not Present (V5) : 0
+[06Fh 0111 1] Reserved : 00
+[070h 0112 4] Flags (decoded below) : 000484A5
+ WBINVD instruction is operational (V1) : 1
+ WBINVD flushes all caches (V1) : 0
+ All CPUs support C1 (V1) : 1
+ C2 works on MP system (V1) : 0
+ Control Method Power Button (V1) : 0
+ Control Method Sleep Button (V1) : 1
+ RTC wake not in fixed reg space (V1) : 0
+ RTC can wake system from S4 (V1) : 1
+ 32-bit PM Timer (V1) : 0
+ Docking Supported (V1) : 0
+ Reset Register Supported (V2) : 1
+ Sealed Case (V3) : 0
+ Headless - No Video (V3) : 0
+ Use native instr after SLP_TYPx (V3) : 0
+ PCIEXP_WAK Bits Supported (V4) : 0
+ Use Platform Timer (V4) : 1
+ RTC_STS valid on S4 wake (V4) : 0
+ Remote Power-on capable (V4) : 0
+ Use APIC Cluster Model (V4) : 1
+ Use APIC Physical Destination Mode (V4) : 0
+ Hardware Reduced (V5) : 0
+ Low Power S0 Idle (V5) : 0
+
+[074h 0116 12] Reset Register : [Generic Address Structure]
+[074h 0116 1] Space ID : 01 [SystemIO]
+[075h 0117 1] Bit Width : 08
+[076h 0118 1] Bit Offset : 00
+[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy]
+[078h 0120 8] Address : 0000000000000CF9
+
+[080h 0128 1] Value to cause reset : 0F
+[081h 0129 2] ARM Flags (decoded below) : 0000
+ PSCI Compliant : 0
+ Must use HVC for PSCI : 0
+
+[083h 0131 1] FADT Minor Revision : 00
+[084h 0132 8] FACS Address : 0000000000000000
+[08Ch 0140 8] DSDT Address : 0000000000000000
+[094h 0148 12] PM1A Event Block : [Generic Address Structure]
+[094h 0148 1] Space ID : 01 [SystemIO]
+[095h 0149 1] Bit Width : 20
+[096h 0150 1] Bit Offset : 00
+[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy]
+[098h 0152 8] Address : 0000000000000600
+
+[0A0h 0160 12] PM1B Event Block : [Generic Address Structure]
+[0A0h 0160 1] Space ID : 00 [SystemMemory]
+[0A1h 0161 1] Bit Width : 00
+[0A2h 0162 1] Bit Offset : 00
+[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0A4h 0164 8] Address : 0000000000000000
+
+[0ACh 0172 12] PM1A Control Block : [Generic Address Structure]
+[0ACh 0172 1] Space ID : 01 [SystemIO]
+[0ADh 0173 1] Bit Width : 10
+[0AEh 0174 1] Bit Offset : 00
+[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0B0h 0176 8] Address : 0000000000000604
+
+[0B8h 0184 12] PM1B Control Block : [Generic Address Structure]
+[0B8h 0184 1] Space ID : 00 [SystemMemory]
+[0B9h 0185 1] Bit Width : 00
+[0BAh 0186 1] Bit Offset : 00
+[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0BCh 0188 8] Address : 0000000000000000
+
+[0C4h 0196 12] PM2 Control Block : [Generic Address Structure]
+[0C4h 0196 1] Space ID : 00 [SystemMemory]
+[0C5h 0197 1] Bit Width : 00
+[0C6h 0198 1] Bit Offset : 00
+[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0C8h 0200 8] Address : 0000000000000000
+
+[0D0h 0208 12] PM Timer Block : [Generic Address Structure]
+[0D0h 0208 1] Space ID : 01 [SystemIO]
+[0D1h 0209 1] Bit Width : 20
+[0D2h 0210 1] Bit Offset : 00
+[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0D4h 0212 8] Address : 0000000000000608
+
+[0DCh 0220 12] GPE0 Block : [Generic Address Structure]
+[0DCh 0220 1] Space ID : 01 [SystemIO]
+[0DDh 0221 1] Bit Width : 80
+[0DEh 0222 1] Bit Offset : 00
+[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0E0h 0224 8] Address : 0000000000000620
+
+[0E8h 0232 12] GPE1 Block : [Generic Address Structure]
+[0E8h 0232 1] Space ID : 00 [SystemMemory]
+[0E9h 0233 1] Bit Width : 00
+[0EAh 0234 1] Bit Offset : 00
+[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0ECh 0236 8] Address : 0000000000000000
...
APIC:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembly of /tmp/aml-2JP791, Wed Aug 23 21:51:31 2023
+ *
+ * ACPI Data Table [APIC]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)]
+[004h 0004 4] Table Length : 00000220
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : 63
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPC "
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Local Apic Address : FEE00000
+[028h 0040 4] Flags (decoded below) : 00000001
+ PC-AT Compatibility : 1
+
+[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC]
+[02Dh 0045 1] Length : 08
+[02Eh 0046 1] Processor ID : 00
+[02Fh 0047 1] Local Apic ID : 00
+[030h 0048 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
+
+[034h 0052 1] Subtable Type : 00 [Processor Local APIC]
+[035h 0053 1] Length : 08
+[036h 0054 1] Processor ID : 01
+[037h 0055 1] Local Apic ID : 01
+[038h 0056 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
[snip]
+[1D4h 0468 1] Subtable Type : 00 [Processor Local APIC]
+[1D5h 0469 1] Length : 08
+[1D6h 0470 1] Processor ID : 35
+[1D7h 0471 1] Local Apic ID : 6A
+[1D8h 0472 4] Flags (decoded below) : 00000000
+ Processor Enabled : 0
+ Runtime Online Capable : 0
+
+[1DCh 0476 1] Subtable Type : 01 [I/O APIC]
+[1DDh 0477 1] Length : 0C
+[1DEh 0478 1] I/O Apic ID : 00
+[1DFh 0479 1] Reserved : 00
+[1E0h 0480 4] Address : FEC00000
+[1E4h 0484 4] Interrupt : 00000000
+
+[1E8h 0488 1] Subtable Type : 02 [Interrupt Source Override]
+[1E9h 0489 1] Length : 0A
+[1EAh 0490 1] Bus : 00
+[1EBh 0491 1] Source : 00
+[1ECh 0492 4] Interrupt : 00000002
+[1F0h 0496 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+
+[1F2h 0498 1] Subtable Type : 02 [Interrupt Source Override]
+[1F3h 0499 1] Length : 0A
+[1F4h 0500 1] Bus : 00
+[1F5h 0501 1] Source : 05
+[1F6h 0502 4] Interrupt : 00000005
+[1FAh 0506 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[1FCh 0508 1] Subtable Type : 02 [Interrupt Source Override]
+[1FDh 0509 1] Length : 0A
+[1FEh 0510 1] Bus : 00
+[1FFh 0511 1] Source : 09
+[200h 0512 4] Interrupt : 00000009
+[204h 0516 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[206h 0518 1] Subtable Type : 02 [Interrupt Source Override]
+[207h 0519 1] Length : 0A
+[208h 0520 1] Bus : 00
+[209h 0521 1] Source : 0A
+[20Ah 0522 4] Interrupt : 0000000A
+[20Eh 0526 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[210h 0528 1] Subtable Type : 02 [Interrupt Source Override]
+[211h 0529 1] Length : 0A
+[212h 0530 1] Bus : 00
+[213h 0531 1] Source : 0B
+[214h 0532 4] Interrupt : 0000000B
+[218h 0536 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[21Ah 0538 1] Subtable Type : 04 [Local APIC NMI]
+[21Bh 0539 1] Length : 06
+[21Ch 0540 1] Processor ID : FF
+[21Dh 0541 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+[21Fh 0543 1] Interrupt Input LINT : 01
...
DSDT:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembling to symbolic ASL+ operators
+ *
+ * Disassembly of /tmp/aml-00O791, Wed Aug 23 21:51:31 2023
+ *
+ * Original Table Header:
+ * Signature "DSDT"
+ * Length 0x00003271 (12913)
+ * Revision 0x01 **** 32-bit table (V1), no 64-bit math support
+ * Checksum 0xAF
+ * OEM ID "BOCHS "
+ * OEM Table ID "BXPC "
+ * OEM Revision 0x00000001 (1)
+ * Compiler ID "BXPC"
+ * Compiler Version 0x00000001 (1)
+ */
+DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001)
+{
+ Scope (\)
+ {
+ OperationRegion (DBG, SystemIO, 0x0402, One)
+ Field (DBG, ByteAcc, NoLock, Preserve)
+ {
+ DBGB, 8
+ }
+
+ Method (DBUG, 1, NotSerialized)
+ {
+ ToHexString (Arg0, Local0)
+ ToBuffer (Local0, Local0)
+ Local1 = (SizeOf (Local0) - One)
+ Local2 = Zero
+ While ((Local2 < Local1))
+ {
+ DBGB = DerefOf (Local0 [Local2])
+ Local2++
+ }
+
+ DBGB = 0x0A
+ }
+ }
[snip]
+ Processor (C000, 0x00, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (Zero))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........
+ })
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (Zero, Arg0, Arg1, Arg2)
+ }
+ }
+
+ Processor (C001, 0x01, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (One))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00 // ........
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (One)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (One, Arg0, Arg1, Arg2)
+ }
+ }
[snip]
+ Processor (C035, 0x35, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (0x35))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x35, 0x6A, 0x01, 0x00, 0x00, 0x00 // ..5j....
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (0x35)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (0x35, Arg0, Arg1, Arg2)
+ }
+ }
...
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Message-Id: <20230928125943.1816922-14-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
tests/qtest/bios-tables-test-allowed-diff.h | 3 ---
tests/data/acpi/q35/APIC.thread-count | Bin 0 -> 544 bytes
tests/data/acpi/q35/DSDT.thread-count | Bin 0 -> 12913 bytes
tests/data/acpi/q35/FACP.thread-count | Bin 0 -> 244 bytes
4 files changed, 3 deletions(-)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index 4d139d7f6b..dfb8523c8b 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1,4 +1 @@
/* List of comma-separated changed AML files to ignore */
-"tests/data/acpi/q35/APIC.thread-count",
-"tests/data/acpi/q35/DSDT.thread-count",
-"tests/data/acpi/q35/FACP.thread-count",
diff --git a/tests/data/acpi/q35/APIC.thread-count b/tests/data/acpi/q35/APIC.thread-count
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..c27e87fcf1c04a2e75f9a20f2bc6a28f19aadf66 100644
GIT binary patch
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literal 0
HcmV?d00001
diff --git a/tests/data/acpi/q35/DSDT.thread-count b/tests/data/acpi/q35/DSDT.thread-count
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..a24b04cbdbf09383b933a42a2a15182545543a87 100644
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literal 0
HcmV?d00001
diff --git a/tests/data/acpi/q35/FACP.thread-count b/tests/data/acpi/q35/FACP.thread-count
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..31fa5dd19c213034eef4eeefa6a04e61dadd8a2a 100644
GIT binary patch
literal 244
zcmZ>BbPo8!z`($~*~#D8BUr&HBEVSz2pEB4AU24G0Y(N+hD|^Y6El!tgNU*~X%LSC
z$X0-fGcm9T0LA|E|L2FOWMD92VqjR>!otAF!NBm72O<iWged~jj0!*k$y^{03>bk1
YBHITON2VDSAnpK(F*YFF1LDH~0O^Si0RR91
literal 0
HcmV?d00001
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 21/78] tests: bios-tables-test: Prepare the ACPI table change for smbios type4 thread count2 test
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (19 preceding siblings ...)
2023-10-19 18:22 ` [PULL v2 20/78] tests: bios-tables-test: Add ACPI table binaries for smbios type4 thread count test Michael S. Tsirkin
@ 2023-10-19 18:22 ` Michael S. Tsirkin
2023-10-19 18:22 ` [PULL v2 22/78] tests: bios-tables-test: Add test for smbios type4 thread count2 Michael S. Tsirkin
` (57 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:22 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Zhao Liu, Igor Mammedov, Ani Sinha
From: Zhao Liu <zhao1.liu@intel.com>
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 1 - 3.
List the ACPI tables that will be added to test the thread count2 field
of smbios type4 table.
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Message-Id: <20230928125943.1816922-15-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
tests/qtest/bios-tables-test-allowed-diff.h | 3 +++
tests/data/acpi/q35/APIC.thread-count2 | 0
tests/data/acpi/q35/DSDT.thread-count2 | 0
tests/data/acpi/q35/FACP.thread-count2 | 0
4 files changed, 3 insertions(+)
create mode 100644 tests/data/acpi/q35/APIC.thread-count2
create mode 100644 tests/data/acpi/q35/DSDT.thread-count2
create mode 100644 tests/data/acpi/q35/FACP.thread-count2
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..d17d80e21a 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1 +1,4 @@
/* List of comma-separated changed AML files to ignore */
+"tests/data/acpi/q35/APIC.thread-count2",
+"tests/data/acpi/q35/DSDT.thread-count2",
+"tests/data/acpi/q35/FACP.thread-count2",
diff --git a/tests/data/acpi/q35/APIC.thread-count2 b/tests/data/acpi/q35/APIC.thread-count2
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/tests/data/acpi/q35/DSDT.thread-count2 b/tests/data/acpi/q35/DSDT.thread-count2
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/tests/data/acpi/q35/FACP.thread-count2 b/tests/data/acpi/q35/FACP.thread-count2
new file mode 100644
index 0000000000..e69de29bb2
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 22/78] tests: bios-tables-test: Add test for smbios type4 thread count2
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (20 preceding siblings ...)
2023-10-19 18:22 ` [PULL v2 21/78] tests: bios-tables-test: Prepare the ACPI table change for smbios type4 thread count2 test Michael S. Tsirkin
@ 2023-10-19 18:22 ` Michael S. Tsirkin
2023-10-19 18:22 ` [PULL v2 23/78] tests: bios-tables-test: Add ACPI table binaries for smbios type4 thread count2 test Michael S. Tsirkin
` (56 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:22 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Zhao Liu, Igor Mammedov, Ani Sinha
From: Zhao Liu <zhao1.liu@intel.com>
This tests the commit 7298fd7de5551 ("hw/smbios: Fix thread count in
type4").
In smbios_build_type_4_table() (hw/smbios/smbios.c), if the number of
threads in the socket is more than 255, then smbios type4 table encodes
threads per socket into the thread count2 field.
So for the topology in this case, there're the following considerations:
1. threads per socket should be more than 255 to ensure we could cover
the thread count2 field.
2. The original bug was that threads per socket was miscalculated, so
now we should configure as many topology levels as possible (mutiple
sockets & dies, no module since x86 hasn't supported it) to cover
more general topology scenarios, to ensure that the threads per
socket encoded in the thread count2 field is correct.
3. For the more general topology, we should also add "cpus" (presented
threads for machine) and "maxcpus" (total threads for machine) to
make sure that configuring unpluged CPUs in smp (cpus < maxcpus)
does not affect the correctness of threads per socket for thread
count2 field.
Based on these considerations, select the topology as the follow:
-smp cpus=210,maxcpus=520,sockets=2,dies=2,cores=65,threads=2
The expected thread count2 = threads per socket = threads (2)
* cores (65) * dies (2) = 260.
Suggested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Message-Id: <20230928125943.1816922-16-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
tests/qtest/bios-tables-test.c | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index 395ed7f9ff..1e61ead539 100644
--- a/tests/qtest/bios-tables-test.c
+++ b/tests/qtest/bios-tables-test.c
@@ -96,6 +96,7 @@ typedef struct {
uint8_t smbios_core_count;
uint16_t smbios_core_count2;
uint8_t smbios_thread_count;
+ uint16_t smbios_thread_count2;
uint8_t *required_struct_types;
int required_struct_types_len;
int type4_count;
@@ -644,6 +645,7 @@ static void smbios_cpu_test(test_data *data, uint32_t addr,
uint8_t thread_count, expected_thread_count = data->smbios_thread_count;
uint16_t speed, expected_speed[2];
uint16_t core_count2, expected_core_count2 = data->smbios_core_count2;
+ uint16_t thread_count2, expected_thread_count2 = data->smbios_thread_count2;
int offset[2];
int i;
@@ -680,6 +682,15 @@ static void smbios_cpu_test(test_data *data, uint32_t addr,
if (expected_core_count == 0xFF && expected_core_count2) {
g_assert_cmpuint(core_count2, ==, expected_core_count2);
}
+
+ thread_count2 = qtest_readw(data->qts,
+ addr + offsetof(struct smbios_type_4,
+ thread_count2));
+
+ /* Thread Count has reached its limit, checking Thread Count 2 */
+ if (expected_thread_count == 0xFF && expected_thread_count2) {
+ g_assert_cmpuint(thread_count2, ==, expected_thread_count2);
+ }
}
}
@@ -1050,6 +1061,7 @@ static void test_acpi_q35_tcg_thread_count(void)
.required_struct_types = base_required_struct_types,
.required_struct_types_len = ARRAY_SIZE(base_required_struct_types),
.smbios_thread_count = 27,
+ .smbios_thread_count2 = 27,
};
test_acpi_one("-machine smbios-entry-point-type=64 "
@@ -1058,6 +1070,23 @@ static void test_acpi_q35_tcg_thread_count(void)
free_test_data(&data);
}
+static void test_acpi_q35_tcg_thread_count2(void)
+{
+ test_data data = {
+ .machine = MACHINE_Q35,
+ .variant = ".thread-count2",
+ .required_struct_types = base_required_struct_types,
+ .required_struct_types_len = ARRAY_SIZE(base_required_struct_types),
+ .smbios_thread_count = 0xFF,
+ .smbios_thread_count2 = 260,
+ };
+
+ test_acpi_one("-machine smbios-entry-point-type=64 "
+ "-smp cpus=210,maxcpus=520,sockets=2,dies=2,cores=65,threads=2",
+ &data);
+ free_test_data(&data);
+}
+
static void test_acpi_q35_tcg_bridge(void)
{
test_data data = {};
@@ -2228,6 +2257,8 @@ int main(int argc, char *argv[])
test_acpi_q35_tcg_core_count2);
qtest_add_func("acpi/q35/thread-count",
test_acpi_q35_tcg_thread_count);
+ qtest_add_func("acpi/q35/thread-count2",
+ test_acpi_q35_tcg_thread_count2);
}
if (qtest_has_device("virtio-iommu-pci")) {
qtest_add_func("acpi/q35/viot", test_acpi_q35_viot);
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 23/78] tests: bios-tables-test: Add ACPI table binaries for smbios type4 thread count2 test
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (21 preceding siblings ...)
2023-10-19 18:22 ` [PULL v2 22/78] tests: bios-tables-test: Add test for smbios type4 thread count2 Michael S. Tsirkin
@ 2023-10-19 18:22 ` Michael S. Tsirkin
2023-10-19 18:22 ` [PULL v2 24/78] vhost-user: strip superfluous whitespace Michael S. Tsirkin
` (55 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:22 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Zhao Liu, Igor Mammedov, Ani Sinha
From: Zhao Liu <zhao1.liu@intel.com>
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 5 and 6.
Changes in the tables:
FACP:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembly of /tmp/aml-WOA191, Wed Aug 23 22:29:53 2023
+ *
+ * ACPI Data Table [FACP]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)]
+[004h 0004 4] Table Length : 000000F4
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : B3
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPC "
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] FACS Address : 00000000
+[028h 0040 4] DSDT Address : 00000000
+[02Ch 0044 1] Model : 01
+[02Dh 0045 1] PM Profile : 00 [Unspecified]
+[02Eh 0046 2] SCI Interrupt : 0009
+[030h 0048 4] SMI Command Port : 000000B2
+[034h 0052 1] ACPI Enable Value : 02
+[035h 0053 1] ACPI Disable Value : 03
+[036h 0054 1] S4BIOS Command : 00
+[037h 0055 1] P-State Control : 00
+[038h 0056 4] PM1A Event Block Address : 00000600
+[03Ch 0060 4] PM1B Event Block Address : 00000000
+[040h 0064 4] PM1A Control Block Address : 00000604
+[044h 0068 4] PM1B Control Block Address : 00000000
+[048h 0072 4] PM2 Control Block Address : 00000000
+[04Ch 0076 4] PM Timer Block Address : 00000608
+[050h 0080 4] GPE0 Block Address : 00000620
+[054h 0084 4] GPE1 Block Address : 00000000
+[058h 0088 1] PM1 Event Block Length : 04
+[059h 0089 1] PM1 Control Block Length : 02
+[05Ah 0090 1] PM2 Control Block Length : 00
+[05Bh 0091 1] PM Timer Block Length : 04
+[05Ch 0092 1] GPE0 Block Length : 10
+[05Dh 0093 1] GPE1 Block Length : 00
+[05Eh 0094 1] GPE1 Base Offset : 00
+[05Fh 0095 1] _CST Support : 00
+[060h 0096 2] C2 Latency : 0FFF
+[062h 0098 2] C3 Latency : 0FFF
+[064h 0100 2] CPU Cache Size : 0000
+[066h 0102 2] Cache Flush Stride : 0000
+[068h 0104 1] Duty Cycle Offset : 00
+[069h 0105 1] Duty Cycle Width : 00
+[06Ah 0106 1] RTC Day Alarm Index : 00
+[06Bh 0107 1] RTC Month Alarm Index : 00
+[06Ch 0108 1] RTC Century Index : 32
+[06Dh 0109 2] Boot Flags (decoded below) : 0002
+ Legacy Devices Supported (V2) : 0
+ 8042 Present on ports 60/64 (V2) : 1
+ VGA Not Present (V4) : 0
+ MSI Not Supported (V4) : 0
+ PCIe ASPM Not Supported (V4) : 0
+ CMOS RTC Not Present (V5) : 0
+[06Fh 0111 1] Reserved : 00
+[070h 0112 4] Flags (decoded below) : 000484A5
+ WBINVD instruction is operational (V1) : 1
+ WBINVD flushes all caches (V1) : 0
+ All CPUs support C1 (V1) : 1
+ C2 works on MP system (V1) : 0
+ Control Method Power Button (V1) : 0
+ Control Method Sleep Button (V1) : 1
+ RTC wake not in fixed reg space (V1) : 0
+ RTC can wake system from S4 (V1) : 1
+ 32-bit PM Timer (V1) : 0
+ Docking Supported (V1) : 0
+ Reset Register Supported (V2) : 1
+ Sealed Case (V3) : 0
+ Headless - No Video (V3) : 0
+ Use native instr after SLP_TYPx (V3) : 0
+ PCIEXP_WAK Bits Supported (V4) : 0
+ Use Platform Timer (V4) : 1
+ RTC_STS valid on S4 wake (V4) : 0
+ Remote Power-on capable (V4) : 0
+ Use APIC Cluster Model (V4) : 1
+ Use APIC Physical Destination Mode (V4) : 0
+ Hardware Reduced (V5) : 0
+ Low Power S0 Idle (V5) : 0
+
+[074h 0116 12] Reset Register : [Generic Address Structure]
+[074h 0116 1] Space ID : 01 [SystemIO]
+[075h 0117 1] Bit Width : 08
+[076h 0118 1] Bit Offset : 00
+[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy]
+[078h 0120 8] Address : 0000000000000CF9
+
+[080h 0128 1] Value to cause reset : 0F
+[081h 0129 2] ARM Flags (decoded below) : 0000
+ PSCI Compliant : 0
+ Must use HVC for PSCI : 0
+
+[083h 0131 1] FADT Minor Revision : 00
+[084h 0132 8] FACS Address : 0000000000000000
+[08Ch 0140 8] DSDT Address : 0000000000000000
+[094h 0148 12] PM1A Event Block : [Generic Address Structure]
+[094h 0148 1] Space ID : 01 [SystemIO]
+[095h 0149 1] Bit Width : 20
+[096h 0150 1] Bit Offset : 00
+[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy]
+[098h 0152 8] Address : 0000000000000600
+
+[0A0h 0160 12] PM1B Event Block : [Generic Address Structure]
+[0A0h 0160 1] Space ID : 00 [SystemMemory]
+[0A1h 0161 1] Bit Width : 00
+[0A2h 0162 1] Bit Offset : 00
+[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0A4h 0164 8] Address : 0000000000000000
+
+[0ACh 0172 12] PM1A Control Block : [Generic Address Structure]
+[0ACh 0172 1] Space ID : 01 [SystemIO]
+[0ADh 0173 1] Bit Width : 10
+[0AEh 0174 1] Bit Offset : 00
+[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0B0h 0176 8] Address : 0000000000000604
+
+[0B8h 0184 12] PM1B Control Block : [Generic Address Structure]
+[0B8h 0184 1] Space ID : 00 [SystemMemory]
+[0B9h 0185 1] Bit Width : 00
+[0BAh 0186 1] Bit Offset : 00
+[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0BCh 0188 8] Address : 0000000000000000
+
+[0C4h 0196 12] PM2 Control Block : [Generic Address Structure]
+[0C4h 0196 1] Space ID : 00 [SystemMemory]
+[0C5h 0197 1] Bit Width : 00
+[0C6h 0198 1] Bit Offset : 00
+[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0C8h 0200 8] Address : 0000000000000000
+
+[0D0h 0208 12] PM Timer Block : [Generic Address Structure]
+[0D0h 0208 1] Space ID : 01 [SystemIO]
+[0D1h 0209 1] Bit Width : 20
+[0D2h 0210 1] Bit Offset : 00
+[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0D4h 0212 8] Address : 0000000000000608
+
+[0DCh 0220 12] GPE0 Block : [Generic Address Structure]
+[0DCh 0220 1] Space ID : 01 [SystemIO]
+[0DDh 0221 1] Bit Width : 80
+[0DEh 0222 1] Bit Offset : 00
+[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0E0h 0224 8] Address : 0000000000000620
+
+[0E8h 0232 12] GPE1 Block : [Generic Address Structure]
+[0E8h 0232 1] Space ID : 00 [SystemMemory]
+[0E9h 0233 1] Bit Width : 00
+[0EAh 0234 1] Bit Offset : 00
+[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0ECh 0236 8] Address : 0000000000000000
...
APIC:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembly of /tmp/aml-UMA191, Wed Aug 23 22:29:53 2023
+ *
+ * ACPI Data Table [APIC]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)]
+[004h 0004 4] Table Length : 00001CE6
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : CA
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPC "
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Local Apic Address : FEE00000
+[028h 0040 4] Flags (decoded below) : 00000001
+ PC-AT Compatibility : 1
+
+[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC]
+[02Dh 0045 1] Length : 08
+[02Eh 0046 1] Processor ID : 00
+[02Fh 0047 1] Local Apic ID : 00
+[030h 0048 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
+
+[034h 0052 1] Subtable Type : 00 [Processor Local APIC]
+[035h 0053 1] Length : 08
+[036h 0054 1] Processor ID : 01
+[037h 0055 1] Local Apic ID : 01
+[038h 0056 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
[snip]
+[434h 1076 1] Subtable Type : 00 [Processor Local APIC]
+[435h 1077 1] Length : 08
+[436h 1078 1] Processor ID : 81
+[437h 1079 1] Local Apic ID : 81
+[438h 1080 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
+
+[43Ch 1084 1] Subtable Type : 09 [Processor Local x2APIC]
+[43Dh 1085 1] Length : 10
+[43Eh 1086 2] Reserved : 0000
+[440h 1088 4] Processor x2Apic ID : 00000100
+[444h 1092 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+[448h 1096 4] Processor UID : 00000082
[snip]
+[1C8Ch 7308 1] Subtable Type : 09 [Processor Local x2APIC]
+[1C8Dh 7309 1] Length : 10
+[1C8Eh 7310 2] Reserved : 0000
+[1C90h 7312 4] Processor x2Apic ID : 00000381
+[1C94h 7316 4] Flags (decoded below) : 00000000
+ Processor Enabled : 0
+[1C98h 7320 4] Processor UID : 00000207
+
+[1C9Ch 7324 1] Subtable Type : 01 [I/O APIC]
+[1C9Dh 7325 1] Length : 0C
+[1C9Eh 7326 1] I/O Apic ID : 00
+[1C9Fh 7327 1] Reserved : 00
+[1CA0h 7328 4] Address : FEC00000
+[1CA4h 7332 4] Interrupt : 00000000
+
+[1CA8h 7336 1] Subtable Type : 02 [Interrupt Source Override]
+[1CA9h 7337 1] Length : 0A
+[1CAAh 7338 1] Bus : 00
+[1CABh 7339 1] Source : 00
+[1CACh 7340 4] Interrupt : 00000002
+[1CB0h 7344 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+
+[1CB2h 7346 1] Subtable Type : 02 [Interrupt Source Override]
+[1CB3h 7347 1] Length : 0A
+[1CB4h 7348 1] Bus : 00
+[1CB5h 7349 1] Source : 05
+[1CB6h 7350 4] Interrupt : 00000005
+[1CBAh 7354 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[1CBCh 7356 1] Subtable Type : 02 [Interrupt Source Override]
+[1CBDh 7357 1] Length : 0A
+[1CBEh 7358 1] Bus : 00
+[1CBFh 7359 1] Source : 09
+[1CC0h 7360 4] Interrupt : 00000009
+[1CC4h 7364 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[1CC6h 7366 1] Subtable Type : 02 [Interrupt Source Override]
+[1CC7h 7367 1] Length : 0A
+[1CC8h 7368 1] Bus : 00
+[1CC9h 7369 1] Source : 0A
+[1CCAh 7370 4] Interrupt : 0000000A
+[1CCEh 7374 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[1CD0h 7376 1] Subtable Type : 02 [Interrupt Source Override]
+[1CD1h 7377 1] Length : 0A
+[1CD2h 7378 1] Bus : 00
+[1CD3h 7379 1] Source : 0B
+[1CD4h 7380 4] Interrupt : 0000000B
+[1CD8h 7384 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[1CDAh 7386 1] Subtable Type : 0A [Local x2APIC NMI]
+[1CDBh 7387 1] Length : 0C
+[1CDCh 7388 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+[1CDEh 7390 4] Processor UID : FFFFFFFF
+[1CE2h 7394 1] Interrupt Input LINT : 01
+[1CE3h 7395 3] Reserved : 000000
...
DSDT:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembling to symbolic ASL+ operators
+ *
+ * Disassembly of /tmp/aml-LWJ191, Wed Aug 23 22:29:53 2023
+ *
+ * Original Table Header:
+ * Signature "DSDT"
+ * Length 0x0000F8B7 (63671)
+ * Revision 0x01 **** 32-bit table (V1), no 64-bit math support
+ * Checksum 0xB7
+ * OEM ID "BOCHS "
+ * OEM Table ID "BXPC "
+ * OEM Revision 0x00000001 (1)
+ * Compiler ID "BXPC"
+ * Compiler Version 0x00000001 (1)
+ */
+DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001)
+{
+ Scope (\)
+ {
+ OperationRegion (DBG, SystemIO, 0x0402, One)
+ Field (DBG, ByteAcc, NoLock, Preserve)
+ {
+ DBGB, 8
+ }
+
+ Method (DBUG, 1, NotSerialized)
+ {
+ ToHexString (Arg0, Local0)
+ ToBuffer (Local0, Local0)
+ Local1 = (SizeOf (Local0) - One)
+ Local2 = Zero
+ While ((Local2 < Local1))
+ {
+ DBGB = DerefOf (Local0 [Local2])
+ Local2++
+ }
+
+ DBGB = 0x0A
+ }
+ }
[snip]
+ Processor (C000, 0x00, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (Zero))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........
+ })
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (Zero, Arg0, Arg1, Arg2)
+ }
+ }
+
+ Processor (C001, 0x01, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (One))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00 // ........
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (One)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (One, Arg0, Arg1, Arg2)
+ }
+ }
[snip]
+ Processor (C081, 0x81, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (0x81))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x81, 0x81, 0x01, 0x00, 0x00, 0x00 // ........
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (0x81)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (0x81, Arg0, Arg1, Arg2)
+ }
+ }
...
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Message-Id: <20230928125943.1816922-17-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
tests/qtest/bios-tables-test-allowed-diff.h | 3 ---
tests/data/acpi/q35/APIC.thread-count2 | Bin 0 -> 7398 bytes
tests/data/acpi/q35/DSDT.thread-count2 | Bin 0 -> 63671 bytes
tests/data/acpi/q35/FACP.thread-count2 | Bin 0 -> 244 bytes
4 files changed, 3 deletions(-)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index d17d80e21a..dfb8523c8b 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1,4 +1 @@
/* List of comma-separated changed AML files to ignore */
-"tests/data/acpi/q35/APIC.thread-count2",
-"tests/data/acpi/q35/DSDT.thread-count2",
-"tests/data/acpi/q35/FACP.thread-count2",
diff --git a/tests/data/acpi/q35/APIC.thread-count2 b/tests/data/acpi/q35/APIC.thread-count2
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..2c6ab5d96c275f8e4872ff91ce3006f992ef3c36 100644
GIT binary patch
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diff --git a/tests/data/acpi/q35/DSDT.thread-count2 b/tests/data/acpi/q35/DSDT.thread-count2
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..cd542c4b5cdd79eb5c6f4054e07bd6a11c3c8657 100644
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zjzU?W+zm?9J74b6$~{^cBFa6ELRp~P1B!pX+^dy)wNfm~y^cazpxg_Jf4<zOmHV_Z
zRFwN1g|a}o4;24=xnC>yYh{=y_d5z@fpR}6{`vBNRvysGa8Vv`6v_hS0Z{z&<w31H
zsFe|-Jm@Ht1<Hd~@xT8`)^@FI*UCPkY<CpO0%bcW{`vBdRvyyIzM?$jD3k@tL!kKQ
z%fniESS$O9^01>&7AOyc;-4>%Xyp;D>@UhAjzU?WJOYY;zC5axN40W*D33Y{Wr6Z2
zDE|5Km{uOs%7LOh<|vc}%44AT=gZ?-d0Z<aMS0v&C<~OwLGjO*C$#c}R-&Rj;V6^^
z$`hdY=gX5?c~UDSqCDv+lm*I@p!ny@Q(AdSD=|@?aumt}<tb32-ud#hR-V>MsVGl7
z3T1)vG${W0@{CrV(Mp*p&o~NYf$|I}{`vB(R-V;LxhT&%3T1)vEGYi@@|;$l(@KRX
z&p8TZf$|(E{`vB}R-V^Nr6|uk3T1)vJShJ8@`6@g&`OmkFE|Qif%1Y?{O_NVwL>dA
zv@%MR9gad-pzHv}KVM$d%8ObVEy|0ILRp}^2#SBcyrh+vv@%ANmmGz%KzRui|9p8_
zD=%xMT9lU^g|a|-85I9~c||L)Xl1M@uQ&>2f$|C{{`vB%R$kT0I8k186v_hSRZ#r%
z<u$Fmrj;5|UUL-60_8PO{PX2?t-P+4@uIx$D3k@t>!A4O%NtsGLo2nSyx}O61<D(s
z_~*-;T6t3|b)vlKD3k@to1jF!^W`nAyrq>1qP*oOlm*ILp!ny@+gf>BD-%U|+fgVB
zl(#|g&zE<!@{U#}iSmx4P!=fffa0Go?`q{;txOi>T}PoTP~HW_KVRO{%6nRwBFcM?
zLRp}^2a12byswq_wQ`Us?>h=*f%3jp{O`Y#^?_DC(8|H0eBdaQ1<D7Y_~*-qTKP~b
z^`d;}D3k@thoJc9%ST%INGnrC`N&Zy3zUyQ@z0l!weqo64iV*JN1-fGJ_f}<Up~>w
zCt5jFlusOmvOxI+6#snrR4boqr9qTW9fh($`4klYeECc(pJ}C0l+PT6vOxI^6#snr
zTq~bzWtu3TI|^li@;NB}`SOKUzR=2aQNC~#$^zvJQ2g`dORapVl^LRZ=_r&1%9o%-
zz4PTOt$d}GnWB8<D3k@tSD^Uk%hy`@S}U_e`Pxw^3zV-x@z0lUwDOHsW{dKTqfizo
z-+<zuFW+kATdm9y<y%LgEKt4$#Xn!Z)5>>RnJdb7jzU?Wd<TkuzI?Bh@3k^dl<ysd
zvOxLXD*pFx$@)PnKWJsXC_gv~Wr6YoDE|5KqgH;@$^ub-bQH=0<wsEb^W`V4{G^qI
zqWt72lm*I9p!ny@&szCeD~E~lv!hTJC_jVZpD({?<rl3SF3K;CLRp~v0*ZgW{Hm2-
zwX#T*Umb<AK=~CE|9tsPE5B)_NtE9lg|a~T4HW-;`CTi&Yvl-0es>hg0_As5{PSg}
zR(5J-u_!wog|a}|35tKd{GpXUw6a8$KOBX!K=}idsCT~nsg*yqvQ(5m9fh($`4bfX
zeECZ&e`#fzD1SK$Wr6Y+DE|5Kw^shv%8{b{?I@H5%HN>)=gU7@`9~{9iSm!5P!=fv
zfa0Go|7zu5tt=PiUq_)VQ2qtQKVNofWtUb~h_cI3C<~NbNu}_=-v1><y$e7nMZN#a
zN>M^|5&}=Agi=rmr6k_}r7+(=U&2}mYh{%vVMn1X=p_t_f4-z>B}FSoi^A_Wg1t}{
zC@G-$=S!+qQnj*L6n?)ER45CSR8ai$B~2@7S~*4(e!me^C<~M{Q2g^HT`TEYIaU;Y
zzY$a@3zT$F{PQJ4D;Zi@BMQIY2r85XN(LzY`O-owEwr*$6n?)ER45CS7OdoUn>whW
zqNc2&EWa=`b#Q7!T}eZ%W@25eE;cr&x&wWX9;k^`(Sfp9ZC%?@S&=(7wF;$V^ZO*3
zcVh~LE5bXocV>q(>G3e%7at1!P9NTxos3)U;<s)3d1I$gDE{$KC=%MWD~m6s|D}Y?
zN9fPC`CsO)UAu0S^;PO4+js4Hkl$j8{<r;r%>!+<_+wmva(89M!{o0VuL#wzi=|PY
zaxkuDY)yVNe`qMPVPaKjD}Fq0@vJ3_mMxw!YY9C_{|0U(E8cOdNTed1mywqd&fy}X
z(rPMeYU2}37ojI9uX54SriIJq{6A}L&)%LL?z|$Dv&U4HiW=Hwq=jkkv>wvXE;B8X
z!f$#)Q89mnyU5wsej4i64Jw};lP{v<%c>{l=hG)HxZ|Akob+%uDP`TJ@~1GTx+{Mc
z>(^z~<>xnKHbhHnshd6P@`uL*`izA`xm2g1G_=hu3KNSWUQp+`b>;TrUZMImHC46a
zQzDI#?3`GdLF(7;GdPtQzLGy0uBja#&7@yS_?H;}QkogcqyLogx}1Nh;9n{;>(>n#
zT~bP$sjMo^j_ycJjrY_h{#oc8=}-}F3^mf*W>th|hGx=#>7OF!Pe{M&aTAkSZQ84>
z%t(5lkomL~j;Wat|7uOO)9Cr4Pdm*R{ydA26KPcuUY@!<H8Zo%8dJG2Hm*9ElTKIr
zb9ScgObuoB$uT+oYbV5#yU8Ml|InDyO`)bxII~YE%$sggS00t;Jtag>B|lIi52Vrq
QIobSYGB<<%R2GE(4_Np=IsgCw
literal 0
HcmV?d00001
diff --git a/tests/data/acpi/q35/FACP.thread-count2 b/tests/data/acpi/q35/FACP.thread-count2
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..31fa5dd19c213034eef4eeefa6a04e61dadd8a2a 100644
GIT binary patch
literal 244
zcmZ>BbPo8!z`($~*~#D8BUr&HBEVSz2pEB4AU24G0Y(N+hD|^Y6El!tgNU*~X%LSC
z$X0-fGcm9T0LA|E|L2FOWMD92VqjR>!otAF!NBm72O<iWged~jj0!*k$y^{03>bk1
YBHITON2VDSAnpK(F*YFF1LDH~0O^Si0RR91
literal 0
HcmV?d00001
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 24/78] vhost-user: strip superfluous whitespace
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (22 preceding siblings ...)
2023-10-19 18:22 ` [PULL v2 23/78] tests: bios-tables-test: Add ACPI table binaries for smbios type4 thread count2 test Michael S. Tsirkin
@ 2023-10-19 18:22 ` Michael S. Tsirkin
2023-10-19 18:22 ` [PULL v2 25/78] vhost-user: tighten "reply_supported" scope in "set_vring_addr" Michael S. Tsirkin
` (54 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:22 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Laszlo Ersek, Eugenio Perez Martin,
German Maglione, Liu Jiang, Sergio Lopez Pascual,
Stefano Garzarella, Philippe Mathieu-Daudé, Albert Esteve
From: Laszlo Ersek <lersek@redhat.com>
Cc: "Michael S. Tsirkin" <mst@redhat.com> (supporter:vhost)
Cc: Eugenio Perez Martin <eperezma@redhat.com>
Cc: German Maglione <gmaglione@redhat.com>
Cc: Liu Jiang <gerry@linux.alibaba.com>
Cc: Sergio Lopez Pascual <slp@redhat.com>
Cc: Stefano Garzarella <sgarzare@redhat.com>
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Stefano Garzarella <sgarzare@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Albert Esteve <aesteve@redhat.com>
Reviewed-by: Eugenio Pérez <eperezma@redhat.com>
Message-Id: <20231002203221.17241-2-lersek@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/virtio/vhost-user.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/virtio/vhost-user.c b/hw/virtio/vhost-user.c
index 68eb1f0c99..3e33a2e9e0 100644
--- a/hw/virtio/vhost-user.c
+++ b/hw/virtio/vhost-user.c
@@ -388,7 +388,7 @@ static int vhost_user_write(struct vhost_dev *dev, VhostUserMsg *msg,
* operations such as configuring device memory mappings or issuing device
* resets, which affect the whole device instead of individual VQs,
* vhost-user messages should only be sent once.
- *
+ *
* Devices with multiple vhost_devs are given an associated dev->vq_index
* so per_device requests are only sent if vq_index is 0.
*/
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 25/78] vhost-user: tighten "reply_supported" scope in "set_vring_addr"
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (23 preceding siblings ...)
2023-10-19 18:22 ` [PULL v2 24/78] vhost-user: strip superfluous whitespace Michael S. Tsirkin
@ 2023-10-19 18:22 ` Michael S. Tsirkin
2023-10-19 18:22 ` [PULL v2 26/78] vhost-user: factor out "vhost_user_write_sync" Michael S. Tsirkin
` (53 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:22 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Laszlo Ersek, Eugenio Perez Martin,
German Maglione, Liu Jiang, Sergio Lopez Pascual,
Stefano Garzarella, Albert Esteve, Philippe Mathieu-Daudé
From: Laszlo Ersek <lersek@redhat.com>
In the vhost_user_set_vring_addr() function, we calculate
"reply_supported" unconditionally, even though we'll only need it if
"wait_for_reply" is also true.
Restrict the scope of "reply_supported" to the minimum.
This is purely refactoring -- no observable change.
Cc: "Michael S. Tsirkin" <mst@redhat.com> (supporter:vhost)
Cc: Eugenio Perez Martin <eperezma@redhat.com>
Cc: German Maglione <gmaglione@redhat.com>
Cc: Liu Jiang <gerry@linux.alibaba.com>
Cc: Sergio Lopez Pascual <slp@redhat.com>
Cc: Stefano Garzarella <sgarzare@redhat.com>
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Stefano Garzarella <sgarzare@redhat.com>
Tested-by: Albert Esteve <aesteve@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Eugenio Pérez <eperezma@redhat.com>
Message-Id: <20231002203221.17241-3-lersek@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/virtio/vhost-user.c | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/hw/virtio/vhost-user.c b/hw/virtio/vhost-user.c
index 3e33a2e9e0..6c7b4cc75c 100644
--- a/hw/virtio/vhost-user.c
+++ b/hw/virtio/vhost-user.c
@@ -1321,17 +1321,18 @@ static int vhost_user_set_vring_addr(struct vhost_dev *dev,
.hdr.size = sizeof(msg.payload.addr),
};
- bool reply_supported = virtio_has_feature(dev->protocol_features,
- VHOST_USER_PROTOCOL_F_REPLY_ACK);
-
/*
* wait for a reply if logging is enabled to make sure
* backend is actually logging changes
*/
bool wait_for_reply = addr->flags & (1 << VHOST_VRING_F_LOG);
- if (reply_supported && wait_for_reply) {
- msg.hdr.flags |= VHOST_USER_NEED_REPLY_MASK;
+ if (wait_for_reply) {
+ bool reply_supported = virtio_has_feature(dev->protocol_features,
+ VHOST_USER_PROTOCOL_F_REPLY_ACK);
+ if (reply_supported) {
+ msg.hdr.flags |= VHOST_USER_NEED_REPLY_MASK;
+ }
}
ret = vhost_user_write(dev, &msg, NULL, 0);
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 26/78] vhost-user: factor out "vhost_user_write_sync"
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (24 preceding siblings ...)
2023-10-19 18:22 ` [PULL v2 25/78] vhost-user: tighten "reply_supported" scope in "set_vring_addr" Michael S. Tsirkin
@ 2023-10-19 18:22 ` Michael S. Tsirkin
2023-10-19 18:22 ` [PULL v2 27/78] vhost-user: flatten "enforce_reply" into "vhost_user_write_sync" Michael S. Tsirkin
` (52 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:22 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Laszlo Ersek, Eugenio Perez Martin,
German Maglione, Liu Jiang, Sergio Lopez Pascual,
Stefano Garzarella, Philippe Mathieu-Daudé, Albert Esteve
From: Laszlo Ersek <lersek@redhat.com>
The tails of the "vhost_user_set_vring_addr" and "vhost_user_set_u64"
functions are now byte-for-byte identical. Factor the common tail out to a
new function called "vhost_user_write_sync".
This is purely refactoring -- no observable change.
Cc: "Michael S. Tsirkin" <mst@redhat.com> (supporter:vhost)
Cc: Eugenio Perez Martin <eperezma@redhat.com>
Cc: German Maglione <gmaglione@redhat.com>
Cc: Liu Jiang <gerry@linux.alibaba.com>
Cc: Sergio Lopez Pascual <slp@redhat.com>
Cc: Stefano Garzarella <sgarzare@redhat.com>
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Stefano Garzarella <sgarzare@redhat.com>
Tested-by: Albert Esteve <aesteve@redhat.com>
Reviewed-by: Eugenio Pérez <eperezma@redhat.com>
Message-Id: <20231002203221.17241-4-lersek@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/virtio/vhost-user.c | 66 ++++++++++++++++++------------------------
1 file changed, 28 insertions(+), 38 deletions(-)
diff --git a/hw/virtio/vhost-user.c b/hw/virtio/vhost-user.c
index 6c7b4cc75c..95dbf9880c 100644
--- a/hw/virtio/vhost-user.c
+++ b/hw/virtio/vhost-user.c
@@ -1310,10 +1310,35 @@ static int enforce_reply(struct vhost_dev *dev,
return vhost_user_get_features(dev, &dummy);
}
+/* Note: "msg->hdr.flags" may be modified. */
+static int vhost_user_write_sync(struct vhost_dev *dev, VhostUserMsg *msg,
+ bool wait_for_reply)
+{
+ int ret;
+
+ if (wait_for_reply) {
+ bool reply_supported = virtio_has_feature(dev->protocol_features,
+ VHOST_USER_PROTOCOL_F_REPLY_ACK);
+ if (reply_supported) {
+ msg->hdr.flags |= VHOST_USER_NEED_REPLY_MASK;
+ }
+ }
+
+ ret = vhost_user_write(dev, msg, NULL, 0);
+ if (ret < 0) {
+ return ret;
+ }
+
+ if (wait_for_reply) {
+ return enforce_reply(dev, msg);
+ }
+
+ return 0;
+}
+
static int vhost_user_set_vring_addr(struct vhost_dev *dev,
struct vhost_vring_addr *addr)
{
- int ret;
VhostUserMsg msg = {
.hdr.request = VHOST_USER_SET_VRING_ADDR,
.hdr.flags = VHOST_USER_VERSION,
@@ -1327,24 +1352,7 @@ static int vhost_user_set_vring_addr(struct vhost_dev *dev,
*/
bool wait_for_reply = addr->flags & (1 << VHOST_VRING_F_LOG);
- if (wait_for_reply) {
- bool reply_supported = virtio_has_feature(dev->protocol_features,
- VHOST_USER_PROTOCOL_F_REPLY_ACK);
- if (reply_supported) {
- msg.hdr.flags |= VHOST_USER_NEED_REPLY_MASK;
- }
- }
-
- ret = vhost_user_write(dev, &msg, NULL, 0);
- if (ret < 0) {
- return ret;
- }
-
- if (wait_for_reply) {
- return enforce_reply(dev, &msg);
- }
-
- return 0;
+ return vhost_user_write_sync(dev, &msg, wait_for_reply);
}
static int vhost_user_set_u64(struct vhost_dev *dev, int request, uint64_t u64,
@@ -1356,26 +1364,8 @@ static int vhost_user_set_u64(struct vhost_dev *dev, int request, uint64_t u64,
.payload.u64 = u64,
.hdr.size = sizeof(msg.payload.u64),
};
- int ret;
- if (wait_for_reply) {
- bool reply_supported = virtio_has_feature(dev->protocol_features,
- VHOST_USER_PROTOCOL_F_REPLY_ACK);
- if (reply_supported) {
- msg.hdr.flags |= VHOST_USER_NEED_REPLY_MASK;
- }
- }
-
- ret = vhost_user_write(dev, &msg, NULL, 0);
- if (ret < 0) {
- return ret;
- }
-
- if (wait_for_reply) {
- return enforce_reply(dev, &msg);
- }
-
- return 0;
+ return vhost_user_write_sync(dev, &msg, wait_for_reply);
}
static int vhost_user_set_status(struct vhost_dev *dev, uint8_t status)
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 27/78] vhost-user: flatten "enforce_reply" into "vhost_user_write_sync"
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (25 preceding siblings ...)
2023-10-19 18:22 ` [PULL v2 26/78] vhost-user: factor out "vhost_user_write_sync" Michael S. Tsirkin
@ 2023-10-19 18:22 ` Michael S. Tsirkin
2023-10-19 18:22 ` [PULL v2 28/78] vhost-user: hoist "write_sync", "get_features", "get_u64" Michael S. Tsirkin
` (51 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:22 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Laszlo Ersek, Eugenio Perez Martin,
German Maglione, Liu Jiang, Sergio Lopez Pascual,
Stefano Garzarella, Philippe Mathieu-Daudé, Albert Esteve
From: Laszlo Ersek <lersek@redhat.com>
At this point, only "vhost_user_write_sync" calls "enforce_reply"; embed
the latter into the former.
This is purely refactoring -- no observable change.
Cc: "Michael S. Tsirkin" <mst@redhat.com> (supporter:vhost)
Cc: Eugenio Perez Martin <eperezma@redhat.com>
Cc: German Maglione <gmaglione@redhat.com>
Cc: Liu Jiang <gerry@linux.alibaba.com>
Cc: Sergio Lopez Pascual <slp@redhat.com>
Cc: Stefano Garzarella <sgarzare@redhat.com>
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Stefano Garzarella <sgarzare@redhat.com>
Tested-by: Albert Esteve <aesteve@redhat.com>
Reviewed-by: Eugenio Pérez <eperezma@redhat.com>
Message-Id: <20231002203221.17241-5-lersek@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/virtio/vhost-user.c | 32 +++++++++++++-------------------
1 file changed, 13 insertions(+), 19 deletions(-)
diff --git a/hw/virtio/vhost-user.c b/hw/virtio/vhost-user.c
index 95dbf9880c..23e9039922 100644
--- a/hw/virtio/vhost-user.c
+++ b/hw/virtio/vhost-user.c
@@ -1292,24 +1292,6 @@ static int vhost_user_get_features(struct vhost_dev *dev, uint64_t *features)
return 0;
}
-static int enforce_reply(struct vhost_dev *dev,
- const VhostUserMsg *msg)
-{
- uint64_t dummy;
-
- if (msg->hdr.flags & VHOST_USER_NEED_REPLY_MASK) {
- return process_message_reply(dev, msg);
- }
-
- /*
- * We need to wait for a reply but the backend does not
- * support replies for the command we just sent.
- * Send VHOST_USER_GET_FEATURES which makes all backends
- * send a reply.
- */
- return vhost_user_get_features(dev, &dummy);
-}
-
/* Note: "msg->hdr.flags" may be modified. */
static int vhost_user_write_sync(struct vhost_dev *dev, VhostUserMsg *msg,
bool wait_for_reply)
@@ -1330,7 +1312,19 @@ static int vhost_user_write_sync(struct vhost_dev *dev, VhostUserMsg *msg,
}
if (wait_for_reply) {
- return enforce_reply(dev, msg);
+ uint64_t dummy;
+
+ if (msg->hdr.flags & VHOST_USER_NEED_REPLY_MASK) {
+ return process_message_reply(dev, msg);
+ }
+
+ /*
+ * We need to wait for a reply but the backend does not
+ * support replies for the command we just sent.
+ * Send VHOST_USER_GET_FEATURES which makes all backends
+ * send a reply.
+ */
+ return vhost_user_get_features(dev, &dummy);
}
return 0;
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 28/78] vhost-user: hoist "write_sync", "get_features", "get_u64"
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (26 preceding siblings ...)
2023-10-19 18:22 ` [PULL v2 27/78] vhost-user: flatten "enforce_reply" into "vhost_user_write_sync" Michael S. Tsirkin
@ 2023-10-19 18:22 ` Michael S. Tsirkin
2023-10-19 18:22 ` [PULL v2 29/78] vhost-user: allow "vhost_set_vring" to wait for a reply Michael S. Tsirkin
` (50 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:22 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Laszlo Ersek, Eugenio Perez Martin,
German Maglione, Liu Jiang, Sergio Lopez Pascual,
Stefano Garzarella, Albert Esteve, Philippe Mathieu-Daudé
From: Laszlo Ersek <lersek@redhat.com>
In order to avoid a forward-declaration for "vhost_user_write_sync" in a
subsequent patch, hoist "vhost_user_write_sync" ->
"vhost_user_get_features" -> "vhost_user_get_u64" just above
"vhost_set_vring".
This is purely code movement -- no observable change.
Cc: "Michael S. Tsirkin" <mst@redhat.com> (supporter:vhost)
Cc: Eugenio Perez Martin <eperezma@redhat.com>
Cc: German Maglione <gmaglione@redhat.com>
Cc: Liu Jiang <gerry@linux.alibaba.com>
Cc: Sergio Lopez Pascual <slp@redhat.com>
Cc: Stefano Garzarella <sgarzare@redhat.com>
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Stefano Garzarella <sgarzare@redhat.com>
Tested-by: Albert Esteve <aesteve@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Eugenio Pérez <eperezma@redhat.com>
Message-Id: <20231002203221.17241-6-lersek@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/virtio/vhost-user.c | 170 ++++++++++++++++++++---------------------
1 file changed, 85 insertions(+), 85 deletions(-)
diff --git a/hw/virtio/vhost-user.c b/hw/virtio/vhost-user.c
index 23e9039922..3c14947589 100644
--- a/hw/virtio/vhost-user.c
+++ b/hw/virtio/vhost-user.c
@@ -1073,6 +1073,91 @@ static int vhost_user_set_vring_endian(struct vhost_dev *dev,
return vhost_user_write(dev, &msg, NULL, 0);
}
+static int vhost_user_get_u64(struct vhost_dev *dev, int request, uint64_t *u64)
+{
+ int ret;
+ VhostUserMsg msg = {
+ .hdr.request = request,
+ .hdr.flags = VHOST_USER_VERSION,
+ };
+
+ if (vhost_user_per_device_request(request) && dev->vq_index != 0) {
+ return 0;
+ }
+
+ ret = vhost_user_write(dev, &msg, NULL, 0);
+ if (ret < 0) {
+ return ret;
+ }
+
+ ret = vhost_user_read(dev, &msg);
+ if (ret < 0) {
+ return ret;
+ }
+
+ if (msg.hdr.request != request) {
+ error_report("Received unexpected msg type. Expected %d received %d",
+ request, msg.hdr.request);
+ return -EPROTO;
+ }
+
+ if (msg.hdr.size != sizeof(msg.payload.u64)) {
+ error_report("Received bad msg size.");
+ return -EPROTO;
+ }
+
+ *u64 = msg.payload.u64;
+
+ return 0;
+}
+
+static int vhost_user_get_features(struct vhost_dev *dev, uint64_t *features)
+{
+ if (vhost_user_get_u64(dev, VHOST_USER_GET_FEATURES, features) < 0) {
+ return -EPROTO;
+ }
+
+ return 0;
+}
+
+/* Note: "msg->hdr.flags" may be modified. */
+static int vhost_user_write_sync(struct vhost_dev *dev, VhostUserMsg *msg,
+ bool wait_for_reply)
+{
+ int ret;
+
+ if (wait_for_reply) {
+ bool reply_supported = virtio_has_feature(dev->protocol_features,
+ VHOST_USER_PROTOCOL_F_REPLY_ACK);
+ if (reply_supported) {
+ msg->hdr.flags |= VHOST_USER_NEED_REPLY_MASK;
+ }
+ }
+
+ ret = vhost_user_write(dev, msg, NULL, 0);
+ if (ret < 0) {
+ return ret;
+ }
+
+ if (wait_for_reply) {
+ uint64_t dummy;
+
+ if (msg->hdr.flags & VHOST_USER_NEED_REPLY_MASK) {
+ return process_message_reply(dev, msg);
+ }
+
+ /*
+ * We need to wait for a reply but the backend does not
+ * support replies for the command we just sent.
+ * Send VHOST_USER_GET_FEATURES which makes all backends
+ * send a reply.
+ */
+ return vhost_user_get_features(dev, &dummy);
+ }
+
+ return 0;
+}
+
static int vhost_set_vring(struct vhost_dev *dev,
unsigned long int request,
struct vhost_vring_state *ring)
@@ -1245,91 +1330,6 @@ static int vhost_user_set_vring_err(struct vhost_dev *dev,
return vhost_set_vring_file(dev, VHOST_USER_SET_VRING_ERR, file);
}
-static int vhost_user_get_u64(struct vhost_dev *dev, int request, uint64_t *u64)
-{
- int ret;
- VhostUserMsg msg = {
- .hdr.request = request,
- .hdr.flags = VHOST_USER_VERSION,
- };
-
- if (vhost_user_per_device_request(request) && dev->vq_index != 0) {
- return 0;
- }
-
- ret = vhost_user_write(dev, &msg, NULL, 0);
- if (ret < 0) {
- return ret;
- }
-
- ret = vhost_user_read(dev, &msg);
- if (ret < 0) {
- return ret;
- }
-
- if (msg.hdr.request != request) {
- error_report("Received unexpected msg type. Expected %d received %d",
- request, msg.hdr.request);
- return -EPROTO;
- }
-
- if (msg.hdr.size != sizeof(msg.payload.u64)) {
- error_report("Received bad msg size.");
- return -EPROTO;
- }
-
- *u64 = msg.payload.u64;
-
- return 0;
-}
-
-static int vhost_user_get_features(struct vhost_dev *dev, uint64_t *features)
-{
- if (vhost_user_get_u64(dev, VHOST_USER_GET_FEATURES, features) < 0) {
- return -EPROTO;
- }
-
- return 0;
-}
-
-/* Note: "msg->hdr.flags" may be modified. */
-static int vhost_user_write_sync(struct vhost_dev *dev, VhostUserMsg *msg,
- bool wait_for_reply)
-{
- int ret;
-
- if (wait_for_reply) {
- bool reply_supported = virtio_has_feature(dev->protocol_features,
- VHOST_USER_PROTOCOL_F_REPLY_ACK);
- if (reply_supported) {
- msg->hdr.flags |= VHOST_USER_NEED_REPLY_MASK;
- }
- }
-
- ret = vhost_user_write(dev, msg, NULL, 0);
- if (ret < 0) {
- return ret;
- }
-
- if (wait_for_reply) {
- uint64_t dummy;
-
- if (msg->hdr.flags & VHOST_USER_NEED_REPLY_MASK) {
- return process_message_reply(dev, msg);
- }
-
- /*
- * We need to wait for a reply but the backend does not
- * support replies for the command we just sent.
- * Send VHOST_USER_GET_FEATURES which makes all backends
- * send a reply.
- */
- return vhost_user_get_features(dev, &dummy);
- }
-
- return 0;
-}
-
static int vhost_user_set_vring_addr(struct vhost_dev *dev,
struct vhost_vring_addr *addr)
{
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 29/78] vhost-user: allow "vhost_set_vring" to wait for a reply
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (27 preceding siblings ...)
2023-10-19 18:22 ` [PULL v2 28/78] vhost-user: hoist "write_sync", "get_features", "get_u64" Michael S. Tsirkin
@ 2023-10-19 18:22 ` Michael S. Tsirkin
2023-10-19 18:22 ` [PULL v2 30/78] vhost-user: call VHOST_USER_SET_VRING_ENABLE synchronously Michael S. Tsirkin
` (49 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:22 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Laszlo Ersek, Eugenio Perez Martin,
German Maglione, Liu Jiang, Sergio Lopez Pascual,
Stefano Garzarella, Philippe Mathieu-Daudé, Albert Esteve
From: Laszlo Ersek <lersek@redhat.com>
The "vhost_set_vring" function already centralizes the common parts of
"vhost_user_set_vring_num", "vhost_user_set_vring_base" and
"vhost_user_set_vring_enable". We'll want to allow some of those callers
to wait for a reply.
Therefore, rebase "vhost_set_vring" from just "vhost_user_write" to
"vhost_user_write_sync", exposing the "wait_for_reply" parameter.
This is purely refactoring -- there is no observable change. That's
because:
- all three callers pass in "false" for "wait_for_reply", which disables
all logic in "vhost_user_write_sync" except the call to
"vhost_user_write";
- the fds=NULL and fd_num=0 arguments of the original "vhost_user_write"
call inside "vhost_set_vring" are hard-coded within
"vhost_user_write_sync".
Cc: "Michael S. Tsirkin" <mst@redhat.com> (supporter:vhost)
Cc: Eugenio Perez Martin <eperezma@redhat.com>
Cc: German Maglione <gmaglione@redhat.com>
Cc: Liu Jiang <gerry@linux.alibaba.com>
Cc: Sergio Lopez Pascual <slp@redhat.com>
Cc: Stefano Garzarella <sgarzare@redhat.com>
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Stefano Garzarella <sgarzare@redhat.com>
Tested-by: Albert Esteve <aesteve@redhat.com>
Reviewed-by: Eugenio Pérez <eperezma@redhat.com>
Message-Id: <20231002203221.17241-7-lersek@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/virtio/vhost-user.c | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/hw/virtio/vhost-user.c b/hw/virtio/vhost-user.c
index 3c14947589..7e452849fa 100644
--- a/hw/virtio/vhost-user.c
+++ b/hw/virtio/vhost-user.c
@@ -1160,7 +1160,8 @@ static int vhost_user_write_sync(struct vhost_dev *dev, VhostUserMsg *msg,
static int vhost_set_vring(struct vhost_dev *dev,
unsigned long int request,
- struct vhost_vring_state *ring)
+ struct vhost_vring_state *ring,
+ bool wait_for_reply)
{
VhostUserMsg msg = {
.hdr.request = request,
@@ -1169,13 +1170,13 @@ static int vhost_set_vring(struct vhost_dev *dev,
.hdr.size = sizeof(msg.payload.state),
};
- return vhost_user_write(dev, &msg, NULL, 0);
+ return vhost_user_write_sync(dev, &msg, wait_for_reply);
}
static int vhost_user_set_vring_num(struct vhost_dev *dev,
struct vhost_vring_state *ring)
{
- return vhost_set_vring(dev, VHOST_USER_SET_VRING_NUM, ring);
+ return vhost_set_vring(dev, VHOST_USER_SET_VRING_NUM, ring, false);
}
static void vhost_user_host_notifier_free(VhostUserHostNotifier *n)
@@ -1206,7 +1207,7 @@ static void vhost_user_host_notifier_remove(VhostUserHostNotifier *n,
static int vhost_user_set_vring_base(struct vhost_dev *dev,
struct vhost_vring_state *ring)
{
- return vhost_set_vring(dev, VHOST_USER_SET_VRING_BASE, ring);
+ return vhost_set_vring(dev, VHOST_USER_SET_VRING_BASE, ring, false);
}
static int vhost_user_set_vring_enable(struct vhost_dev *dev, int enable)
@@ -1224,7 +1225,7 @@ static int vhost_user_set_vring_enable(struct vhost_dev *dev, int enable)
.num = enable,
};
- ret = vhost_set_vring(dev, VHOST_USER_SET_VRING_ENABLE, &state);
+ ret = vhost_set_vring(dev, VHOST_USER_SET_VRING_ENABLE, &state, false);
if (ret < 0) {
/*
* Restoring the previous state is likely infeasible, as well as
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 30/78] vhost-user: call VHOST_USER_SET_VRING_ENABLE synchronously
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (28 preceding siblings ...)
2023-10-19 18:22 ` [PULL v2 29/78] vhost-user: allow "vhost_set_vring" to wait for a reply Michael S. Tsirkin
@ 2023-10-19 18:22 ` Michael S. Tsirkin
2023-10-19 18:22 ` [PULL v2 31/78] memory: initialize 'fv' in MemoryRegionCache to make Coverity happy Michael S. Tsirkin
` (48 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:22 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Laszlo Ersek, Eugenio Perez Martin,
German Maglione, Liu Jiang, Sergio Lopez Pascual,
Stefano Garzarella, Albert Esteve
From: Laszlo Ersek <lersek@redhat.com>
(1) The virtio-1.2 specification
<http://docs.oasis-open.org/virtio/virtio/v1.2/virtio-v1.2.html> writes:
> 3 General Initialization And Device Operation
> 3.1 Device Initialization
> 3.1.1 Driver Requirements: Device Initialization
>
> [...]
>
> 7. Perform device-specific setup, including discovery of virtqueues for
> the device, optional per-bus setup, reading and possibly writing the
> device’s virtio configuration space, and population of virtqueues.
>
> 8. Set the DRIVER_OK status bit. At this point the device is “live”.
and
> 4 Virtio Transport Options
> 4.1 Virtio Over PCI Bus
> 4.1.4 Virtio Structure PCI Capabilities
> 4.1.4.3 Common configuration structure layout
> 4.1.4.3.2 Driver Requirements: Common configuration structure layout
>
> [...]
>
> The driver MUST configure the other virtqueue fields before enabling the
> virtqueue with queue_enable.
>
> [...]
(The same statements are present in virtio-1.0 identically, at
<http://docs.oasis-open.org/virtio/virtio/v1.0/virtio-v1.0.html>.)
These together mean that the following sub-sequence of steps is valid for
a virtio-1.0 guest driver:
(1.1) set "queue_enable" for the needed queues as the final part of device
initialization step (7),
(1.2) set DRIVER_OK in step (8),
(1.3) immediately start sending virtio requests to the device.
(2) When vhost-user is enabled, and the VHOST_USER_F_PROTOCOL_FEATURES
special virtio feature is negotiated, then virtio rings start in disabled
state, according to
<https://qemu-project.gitlab.io/qemu/interop/vhost-user.html#ring-states>.
In this case, explicit VHOST_USER_SET_VRING_ENABLE messages are needed for
enabling vrings.
Therefore setting "queue_enable" from the guest (1.1) -- which is
technically "buffered" on the QEMU side until the guest sets DRIVER_OK
(1.2) -- is a *control plane* operation, which -- after (1.2) -- travels
from the guest through QEMU to the vhost-user backend, using a unix domain
socket.
Whereas sending a virtio request (1.3) is a *data plane* operation, which
evades QEMU -- it travels from guest to the vhost-user backend via
eventfd.
This means that operations ((1.1) + (1.2)) and (1.3) travel through
different channels, and their relative order can be reversed, as perceived
by the vhost-user backend.
That's exactly what happens when OVMF's virtiofs driver (VirtioFsDxe) runs
against the Rust-language virtiofsd version 1.7.2. (Which uses version
0.10.1 of the vhost-user-backend crate, and version 0.8.1 of the vhost
crate.)
Namely, when VirtioFsDxe binds a virtiofs device, it goes through the
device initialization steps (i.e., control plane operations), and
immediately sends a FUSE_INIT request too (i.e., performs a data plane
operation). In the Rust-language virtiofsd, this creates a race between
two components that run *concurrently*, i.e., in different threads or
processes:
- Control plane, handling vhost-user protocol messages:
The "VhostUserSlaveReqHandlerMut::set_vring_enable" method
[crates/vhost-user-backend/src/handler.rs] handles
VHOST_USER_SET_VRING_ENABLE messages, and updates each vring's "enabled"
flag according to the message processed.
- Data plane, handling virtio / FUSE requests:
The "VringEpollHandler::handle_event" method
[crates/vhost-user-backend/src/event_loop.rs] handles the incoming
virtio / FUSE request, consuming the virtio kick at the same time. If
the vring's "enabled" flag is set, the virtio / FUSE request is
processed genuinely. If the vring's "enabled" flag is clear, then the
virtio / FUSE request is discarded.
Note that OVMF enables the queue *first*, and sends FUSE_INIT *second*.
However, if the data plane processor in virtiofsd wins the race, then it
sees the FUSE_INIT *before* the control plane processor took notice of
VHOST_USER_SET_VRING_ENABLE and green-lit the queue for the data plane
processor. Therefore the latter drops FUSE_INIT on the floor, and goes
back to waiting for further virtio / FUSE requests with epoll_wait.
Meanwhile OVMF is stuck waiting for the FUSET_INIT response -- a deadlock.
The deadlock is not deterministic. OVMF hangs infrequently during first
boot. However, OVMF hangs almost certainly during reboots from the UEFI
shell.
The race can be "reliably masked" by inserting a very small delay -- a
single debug message -- at the top of "VringEpollHandler::handle_event",
i.e., just before the data plane processor checks the "enabled" field of
the vring. That delay suffices for the control plane processor to act upon
VHOST_USER_SET_VRING_ENABLE.
We can deterministically prevent the race in QEMU, by blocking OVMF inside
step (1.2) -- i.e., in the write to the device status register that
"unleashes" queue enablement -- until VHOST_USER_SET_VRING_ENABLE actually
*completes*. That way OVMF's VCPU cannot advance to the FUSE_INIT
submission before virtiofsd's control plane processor takes notice of the
queue being enabled.
Wait for VHOST_USER_SET_VRING_ENABLE completion by:
- setting the NEED_REPLY flag on VHOST_USER_SET_VRING_ENABLE, and waiting
for the reply, if the VHOST_USER_PROTOCOL_F_REPLY_ACK vhost-user feature
has been negotiated, or
- performing a separate VHOST_USER_GET_FEATURES *exchange*, which requires
a backend response regardless of VHOST_USER_PROTOCOL_F_REPLY_ACK.
Cc: "Michael S. Tsirkin" <mst@redhat.com> (supporter:vhost)
Cc: Eugenio Perez Martin <eperezma@redhat.com>
Cc: German Maglione <gmaglione@redhat.com>
Cc: Liu Jiang <gerry@linux.alibaba.com>
Cc: Sergio Lopez Pascual <slp@redhat.com>
Cc: Stefano Garzarella <sgarzare@redhat.com>
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Stefano Garzarella <sgarzare@redhat.com>
Tested-by: Albert Esteve <aesteve@redhat.com>
[lersek@redhat.com: work Eugenio's explanation into the commit message,
about QEMU containing step (1.1) until step (1.2)]
Reviewed-by: Eugenio Pérez <eperezma@redhat.com>
Message-Id: <20231002203221.17241-8-lersek@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/virtio/vhost-user.c | 16 +++++++++++++++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/hw/virtio/vhost-user.c b/hw/virtio/vhost-user.c
index 7e452849fa..427ee0ebfb 100644
--- a/hw/virtio/vhost-user.c
+++ b/hw/virtio/vhost-user.c
@@ -1225,7 +1225,21 @@ static int vhost_user_set_vring_enable(struct vhost_dev *dev, int enable)
.num = enable,
};
- ret = vhost_set_vring(dev, VHOST_USER_SET_VRING_ENABLE, &state, false);
+ /*
+ * SET_VRING_ENABLE travels from guest to QEMU to vhost-user backend /
+ * control plane thread via unix domain socket. Virtio requests travel
+ * from guest to vhost-user backend / data plane thread via eventfd.
+ * Even if the guest enables the ring first, and pushes its first virtio
+ * request second (conforming to the virtio spec), the data plane thread
+ * in the backend may see the virtio request before the control plane
+ * thread sees the queue enablement. This causes (in fact, requires) the
+ * data plane thread to discard the virtio request (it arrived on a
+ * seemingly disabled queue). To prevent this out-of-order delivery,
+ * don't let the guest proceed to pushing the virtio request until the
+ * backend control plane acknowledges enabling the queue -- IOW, pass
+ * wait_for_reply=true below.
+ */
+ ret = vhost_set_vring(dev, VHOST_USER_SET_VRING_ENABLE, &state, true);
if (ret < 0) {
/*
* Restoring the previous state is likely infeasible, as well as
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 31/78] memory: initialize 'fv' in MemoryRegionCache to make Coverity happy
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (29 preceding siblings ...)
2023-10-19 18:22 ` [PULL v2 30/78] vhost-user: call VHOST_USER_SET_VRING_ENABLE synchronously Michael S. Tsirkin
@ 2023-10-19 18:22 ` Michael S. Tsirkin
2023-10-19 18:22 ` [PULL v2 32/78] vhost-user: do not send RESET_OWNER on device reset Michael S. Tsirkin
` (47 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:22 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Ilya Maximets, David Hildenbrand, Stefan Hajnoczi,
Paolo Bonzini, Peter Xu, Philippe Mathieu-Daudé
From: Ilya Maximets <i.maximets@ovn.org>
Coverity scan reports multiple false-positive "defects" for the
following series of actions in virtio.c:
MemoryRegionCache indirect_desc_cache;
address_space_cache_init_empty(&indirect_desc_cache);
address_space_cache_destroy(&indirect_desc_cache);
For some reason it's unable to recognize the dependency between 'mrs.mr'
and 'fv' and insists that '!mrs.mr' check in address_space_cache_destroy
may take a 'false' branch, even though it is explicitly initialized to
NULL in the address_space_cache_init_empty():
*** CID 1522371: Memory - illegal accesses (UNINIT)
/qemu/hw/virtio/virtio.c: 1627 in virtqueue_split_pop()
1621 }
1622
1623 vq->inuse++;
1624
1625 trace_virtqueue_pop(vq, elem, elem->in_num, elem->out_num);
1626 done:
>>> CID 1522371: Memory - illegal accesses (UNINIT)
>>> Using uninitialized value "indirect_desc_cache.fv" when
>>> calling "address_space_cache_destroy".
1627 address_space_cache_destroy(&indirect_desc_cache);
1628
1629 return elem;
1630
1631 err_undo_map:
1632 virtqueue_undo_map_desc(out_num, in_num, iov);
** CID 1522370: Memory - illegal accesses (UNINIT)
Instead of trying to silence these false positive reports in 4
different places, initializing 'fv' as well, as this doesn't result
in any noticeable performance impact.
Signed-off-by: Ilya Maximets <i.maximets@ovn.org>
Message-Id: <20231009104322.3085887-1-i.maximets@ovn.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: David Hildenbrand <david@redhat.com>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
---
include/exec/memory.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/exec/memory.h b/include/exec/memory.h
index 653a32ea10..9087d02769 100644
--- a/include/exec/memory.h
+++ b/include/exec/memory.h
@@ -2793,6 +2793,8 @@ int64_t address_space_cache_init(MemoryRegionCache *cache,
static inline void address_space_cache_init_empty(MemoryRegionCache *cache)
{
cache->mrs.mr = NULL;
+ /* There is no real need to initialize fv, but it makes Coverity happy. */
+ cache->fv = NULL;
}
/**
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 32/78] vhost-user: do not send RESET_OWNER on device reset
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (30 preceding siblings ...)
2023-10-19 18:22 ` [PULL v2 31/78] memory: initialize 'fv' in MemoryRegionCache to make Coverity happy Michael S. Tsirkin
@ 2023-10-19 18:22 ` Michael S. Tsirkin
2023-10-19 18:22 ` [PULL v2 33/78] vhost-backend: remove vhost_kernel_reset_device() Michael S. Tsirkin
` (46 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:22 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Stefan Hajnoczi, Raphael Norwitz, Paolo Bonzini,
Fam Zheng
From: Stefan Hajnoczi <stefanha@redhat.com>
The VHOST_USER_RESET_OWNER message is deprecated in the spec:
This is no longer used. Used to be sent to request disabling all
rings, but some back-ends interpreted it to also discard connection
state (this interpretation would lead to bugs). It is recommended
that back-ends either ignore this message, or use it to disable all
rings.
The only caller of vhost_user_reset_device() is vhost_user_scsi_reset().
It checks that F_RESET_DEVICE was negotiated before calling it:
static void vhost_user_scsi_reset(VirtIODevice *vdev)
{
VHostSCSICommon *vsc = VHOST_SCSI_COMMON(vdev);
struct vhost_dev *dev = &vsc->dev;
/*
* Historically, reset was not implemented so only reset devices
* that are expecting it.
*/
if (!virtio_has_feature(dev->protocol_features,
VHOST_USER_PROTOCOL_F_RESET_DEVICE)) {
return;
}
if (dev->vhost_ops->vhost_reset_device) {
dev->vhost_ops->vhost_reset_device(dev);
}
}
Therefore VHOST_USER_RESET_OWNER is actually never sent by
vhost_user_reset_device(). Remove the dead code. This effectively moves
the vhost-user protocol specific code from vhost-user-scsi.c into
vhost-user.c where it belongs.
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Message-Id: <20231004014532.1228637-2-stefanha@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Raphael Norwitz <raphael.norwitz@nutanix.com>
---
hw/scsi/vhost-user-scsi.c | 9 ---------
hw/virtio/vhost-user.c | 13 +++++++++----
2 files changed, 9 insertions(+), 13 deletions(-)
diff --git a/hw/scsi/vhost-user-scsi.c b/hw/scsi/vhost-user-scsi.c
index df6b66cc1a..78aef4765f 100644
--- a/hw/scsi/vhost-user-scsi.c
+++ b/hw/scsi/vhost-user-scsi.c
@@ -67,15 +67,6 @@ static void vhost_user_scsi_reset(VirtIODevice *vdev)
VHostSCSICommon *vsc = VHOST_SCSI_COMMON(vdev);
struct vhost_dev *dev = &vsc->dev;
- /*
- * Historically, reset was not implemented so only reset devices
- * that are expecting it.
- */
- if (!virtio_has_feature(dev->protocol_features,
- VHOST_USER_PROTOCOL_F_RESET_DEVICE)) {
- return;
- }
-
if (dev->vhost_ops->vhost_reset_device) {
dev->vhost_ops->vhost_reset_device(dev);
}
diff --git a/hw/virtio/vhost-user.c b/hw/virtio/vhost-user.c
index 427ee0ebfb..f9414f03de 100644
--- a/hw/virtio/vhost-user.c
+++ b/hw/virtio/vhost-user.c
@@ -1482,12 +1482,17 @@ static int vhost_user_reset_device(struct vhost_dev *dev)
{
VhostUserMsg msg = {
.hdr.flags = VHOST_USER_VERSION,
+ .hdr.request = VHOST_USER_RESET_DEVICE,
};
- msg.hdr.request = virtio_has_feature(dev->protocol_features,
- VHOST_USER_PROTOCOL_F_RESET_DEVICE)
- ? VHOST_USER_RESET_DEVICE
- : VHOST_USER_RESET_OWNER;
+ /*
+ * Historically, reset was not implemented so only reset devices
+ * that are expecting it.
+ */
+ if (!virtio_has_feature(dev->protocol_features,
+ VHOST_USER_PROTOCOL_F_RESET_DEVICE)) {
+ return -ENOSYS;
+ }
return vhost_user_write(dev, &msg, NULL, 0);
}
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 33/78] vhost-backend: remove vhost_kernel_reset_device()
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (31 preceding siblings ...)
2023-10-19 18:22 ` [PULL v2 32/78] vhost-user: do not send RESET_OWNER on device reset Michael S. Tsirkin
@ 2023-10-19 18:22 ` Michael S. Tsirkin
2023-10-19 18:22 ` [PULL v2 34/78] virtio: call ->vhost_reset_device() during reset Michael S. Tsirkin
` (45 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:22 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Stefan Hajnoczi, Raphael Norwitz, Hanna Czenczek
From: Stefan Hajnoczi <stefanha@redhat.com>
vhost_kernel_reset_device() invokes RESET_OWNER, which disassociates the
owner process from the device. The device is left non-operational since
SET_OWNER is only called once during startup in vhost_dev_init().
vhost_kernel_reset_device() is never called so this latent bug never
appears. Get rid of vhost_kernel_reset_device() for now. If someone
needs it in the future they'll need to implement it correctly.
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Message-Id: <20231004014532.1228637-3-stefanha@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Raphael Norwitz <raphael.norwitz@nutanix.com>
Reviewed-by: Hanna Czenczek <hreitz@redhat.com>
---
hw/virtio/vhost-backend.c | 6 ------
1 file changed, 6 deletions(-)
diff --git a/hw/virtio/vhost-backend.c b/hw/virtio/vhost-backend.c
index 8e581575c9..17f3fc6a08 100644
--- a/hw/virtio/vhost-backend.c
+++ b/hw/virtio/vhost-backend.c
@@ -197,11 +197,6 @@ static int vhost_kernel_set_owner(struct vhost_dev *dev)
return vhost_kernel_call(dev, VHOST_SET_OWNER, NULL);
}
-static int vhost_kernel_reset_device(struct vhost_dev *dev)
-{
- return vhost_kernel_call(dev, VHOST_RESET_OWNER, NULL);
-}
-
static int vhost_kernel_get_vq_index(struct vhost_dev *dev, int idx)
{
assert(idx >= dev->vq_index && idx < dev->vq_index + dev->nvqs);
@@ -322,7 +317,6 @@ const VhostOps kernel_ops = {
.vhost_get_features = vhost_kernel_get_features,
.vhost_set_backend_cap = vhost_kernel_set_backend_cap,
.vhost_set_owner = vhost_kernel_set_owner,
- .vhost_reset_device = vhost_kernel_reset_device,
.vhost_get_vq_index = vhost_kernel_get_vq_index,
.vhost_vsock_set_guest_cid = vhost_kernel_vsock_set_guest_cid,
.vhost_vsock_set_running = vhost_kernel_vsock_set_running,
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 34/78] virtio: call ->vhost_reset_device() during reset
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (32 preceding siblings ...)
2023-10-19 18:22 ` [PULL v2 33/78] vhost-backend: remove vhost_kernel_reset_device() Michael S. Tsirkin
@ 2023-10-19 18:22 ` Michael S. Tsirkin
2023-10-19 18:22 ` [PULL v2 35/78] hw/i386/acpi-build: Remove build-time assertion on PIIX/ICH9 reset registers being identical Michael S. Tsirkin
` (44 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:22 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Stefan Hajnoczi, Raphael Norwitz, Hanna Czenczek,
Paolo Bonzini, Fam Zheng, Marc-André Lureau,
Daniel P. Berrangé, Thomas Huth, Philippe Mathieu-Daudé
From: Stefan Hajnoczi <stefanha@redhat.com>
vhost-user-scsi has a VirtioDeviceClass->reset() function that calls
->vhost_reset_device(). The other vhost devices don't notify the vhost
device upon reset.
Stateful vhost devices may need to handle device reset in order to free
resources or prevent stale device state from interfering after reset.
Call ->vhost_device_reset() from virtio_reset() so that that vhost
devices are notified of device reset.
This patch affects behavior as follows:
- vhost-kernel: No change in behavior since ->vhost_reset_device() is
not implemented.
- vhost-user: back-ends that negotiate
VHOST_USER_PROTOCOL_F_RESET_DEVICE now receive a
VHOST_USER_DEVICE_RESET message upon device reset. Otherwise there is
no change in behavior. DPDK, SPDK, libvhost-user, and the
vhost-user-backend crate do not negotiate
VHOST_USER_PROTOCOL_F_RESET_DEVICE automatically.
- vhost-vdpa: an extra SET_STATUS 0 call is made during device reset.
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Message-Id: <20231004014532.1228637-4-stefanha@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Raphael Norwitz <raphael.norwitz@nutanix.com>
Reviewed-by: Hanna Czenczek <hreitz@redhat.com>
---
include/hw/virtio/vhost.h | 10 ++++++++++
hw/scsi/vhost-user-scsi.c | 11 -----------
hw/virtio/vhost.c | 9 +++++++++
hw/virtio/virtio.c | 4 ++++
meson.build | 1 +
5 files changed, 24 insertions(+), 11 deletions(-)
diff --git a/include/hw/virtio/vhost.h b/include/hw/virtio/vhost.h
index c7e5467693..00e0a669b8 100644
--- a/include/hw/virtio/vhost.h
+++ b/include/hw/virtio/vhost.h
@@ -339,4 +339,14 @@ int vhost_dev_set_inflight(struct vhost_dev *dev,
int vhost_dev_get_inflight(struct vhost_dev *dev, uint16_t queue_size,
struct vhost_inflight *inflight);
bool vhost_dev_has_iommu(struct vhost_dev *dev);
+
+#ifdef CONFIG_VHOST
+int vhost_reset_device(struct vhost_dev *hdev);
+#else
+static inline int vhost_reset_device(struct vhost_dev *hdev)
+{
+ return -ENOSYS;
+}
+#endif /* CONFIG_VHOST */
+
#endif
diff --git a/hw/scsi/vhost-user-scsi.c b/hw/scsi/vhost-user-scsi.c
index 78aef4765f..b7c6100f3e 100644
--- a/hw/scsi/vhost-user-scsi.c
+++ b/hw/scsi/vhost-user-scsi.c
@@ -62,16 +62,6 @@ static void vhost_user_scsi_set_status(VirtIODevice *vdev, uint8_t status)
}
}
-static void vhost_user_scsi_reset(VirtIODevice *vdev)
-{
- VHostSCSICommon *vsc = VHOST_SCSI_COMMON(vdev);
- struct vhost_dev *dev = &vsc->dev;
-
- if (dev->vhost_ops->vhost_reset_device) {
- dev->vhost_ops->vhost_reset_device(dev);
- }
-}
-
static void vhost_dummy_handle_output(VirtIODevice *vdev, VirtQueue *vq)
{
}
@@ -191,7 +181,6 @@ static void vhost_user_scsi_class_init(ObjectClass *klass, void *data)
vdc->get_features = vhost_scsi_common_get_features;
vdc->set_config = vhost_scsi_common_set_config;
vdc->set_status = vhost_user_scsi_set_status;
- vdc->reset = vhost_user_scsi_reset;
fwc->get_dev_path = vhost_scsi_common_get_fw_dev_path;
}
diff --git a/hw/virtio/vhost.c b/hw/virtio/vhost.c
index 9f37206ba0..92a6933f66 100644
--- a/hw/virtio/vhost.c
+++ b/hw/virtio/vhost.c
@@ -2154,3 +2154,12 @@ int vhost_net_set_backend(struct vhost_dev *hdev,
return -ENOSYS;
}
+
+int vhost_reset_device(struct vhost_dev *hdev)
+{
+ if (hdev->vhost_ops->vhost_reset_device) {
+ return hdev->vhost_ops->vhost_reset_device(hdev);
+ }
+
+ return -ENOSYS;
+}
diff --git a/hw/virtio/virtio.c b/hw/virtio/virtio.c
index 6facd64fbc..fb24bc927b 100644
--- a/hw/virtio/virtio.c
+++ b/hw/virtio/virtio.c
@@ -2136,6 +2136,10 @@ void virtio_reset(void *opaque)
vdev->device_endian = virtio_default_endian();
}
+ if (vdev->vhost_started) {
+ vhost_reset_device(k->get_vhost(vdev));
+ }
+
if (k->reset) {
k->reset(vdev);
}
diff --git a/meson.build b/meson.build
index e0d1f84b26..cbee764817 100644
--- a/meson.build
+++ b/meson.build
@@ -2134,6 +2134,7 @@ config_host_data.set('CONFIG_TPM', have_tpm)
config_host_data.set('CONFIG_TSAN', get_option('tsan'))
config_host_data.set('CONFIG_USB_LIBUSB', libusb.found())
config_host_data.set('CONFIG_VDE', vde.found())
+config_host_data.set('CONFIG_VHOST', have_vhost)
config_host_data.set('CONFIG_VHOST_NET', have_vhost_net)
config_host_data.set('CONFIG_VHOST_NET_USER', have_vhost_net_user)
config_host_data.set('CONFIG_VHOST_NET_VDPA', have_vhost_net_vdpa)
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 35/78] hw/i386/acpi-build: Remove build-time assertion on PIIX/ICH9 reset registers being identical
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (33 preceding siblings ...)
2023-10-19 18:22 ` [PULL v2 34/78] virtio: call ->vhost_reset_device() during reset Michael S. Tsirkin
@ 2023-10-19 18:22 ` Michael S. Tsirkin
2023-10-19 18:22 ` [PULL v2 36/78] timer/i8254: Fix one shot PIT mode Michael S. Tsirkin
` (43 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:22 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Bernhard Beschow, Ani Sinha,
Philippe Mathieu-Daudé, Igor Mammedov, Marcel Apfelbaum,
Paolo Bonzini, Richard Henderson, Eduardo Habkost
From: Bernhard Beschow <shentey@gmail.com>
Commit 6103451aeb74 ("hw/i386: Build-time assertion on pc/q35 reset register
being identical.") introduced a build-time check where the addresses of the
reset registers are expected to be equal. Back then rev3 of the FADT was used
which required the reset register to be populated and there was common code.
In commit 3a3fcc75f92a ("pc: acpi: force FADT rev1 for 440fx based machine
types") the FADT was downgraded to rev1 for PIIX where the reset register isn't
available. Thus, there is no need for the assertion any longer, so remove it.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Ani Sinha <anisinha@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20231004092355.12929-1-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/i386/acpi-build.c | 5 -----
1 file changed, 5 deletions(-)
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 3f2b27cf75..b0e1f074f1 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -56,7 +56,6 @@
/* Supported chipsets: */
#include "hw/southbridge/ich9.h"
-#include "hw/southbridge/piix.h"
#include "hw/acpi/pcihp.h"
#include "hw/i386/fw_cfg.h"
#include "hw/i386/pc.h"
@@ -242,10 +241,6 @@ static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm)
pm->pcihp_io_len =
object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL);
- /* The above need not be conditional on machine type because the reset port
- * happens to be the same on PIIX (pc) and ICH9 (q35). */
- QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != PIIX_RCR_IOPORT);
-
/* Fill in optional s3/s4 related properties */
o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL);
if (o) {
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 36/78] timer/i8254: Fix one shot PIT mode
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (34 preceding siblings ...)
2023-10-19 18:22 ` [PULL v2 35/78] hw/i386/acpi-build: Remove build-time assertion on PIIX/ICH9 reset registers being identical Michael S. Tsirkin
@ 2023-10-19 18:22 ` Michael S. Tsirkin
2023-10-19 18:22 ` [PULL v2 37/78] hw/display: fix memleak from virtio_add_resource Michael S. Tsirkin
` (42 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:22 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Damien Zammit, Paolo Bonzini
From: Damien Zammit <damien@zamaudio.com>
Currently, the one-shot (mode 1) PIT expires far too quickly,
due to the output being set under the wrong logic.
This change fixes the one-shot PIT mode to behave similarly to mode 0.
TESTED: using the one-shot PIT mode to calibrate a local apic timer.
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Message-Id: <20230226015755.52624-1-damien@zamaudio.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/timer/i8254_common.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/hw/timer/i8254_common.c b/hw/timer/i8254_common.c
index e4093e2904..b25da448c8 100644
--- a/hw/timer/i8254_common.c
+++ b/hw/timer/i8254_common.c
@@ -52,10 +52,8 @@ int pit_get_out(PITChannelState *s, int64_t current_time)
switch (s->mode) {
default:
case 0:
- out = (d >= s->count);
- break;
case 1:
- out = (d < s->count);
+ out = (d >= s->count);
break;
case 2:
if ((d % s->count) == 0 && d != 0) {
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 37/78] hw/display: fix memleak from virtio_add_resource
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (35 preceding siblings ...)
2023-10-19 18:22 ` [PULL v2 36/78] timer/i8254: Fix one shot PIT mode Michael S. Tsirkin
@ 2023-10-19 18:22 ` Michael S. Tsirkin
2023-10-19 18:22 ` [PULL v2 38/78] hw/i386/pc: Merge two if statements into one Michael S. Tsirkin
` (41 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:22 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Matheus Tavares Bernardino, Albert Esteve, Matheus,
Tavares, Bernardino, <
From: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
When the given uuid is already present in the hash table,
virtio_add_resource() does not add the passed VirtioSharedObject. In
this case, free it in the callers to avoid leaking memory. This fixed
the following `make check` error, when built with --enable-sanitizers:
4/166 qemu:unit / test-virtio-dmabuf ERROR 1.51s exit status 1
==7716==ERROR: LeakSanitizer: detected memory leaks
Direct leak of 320 byte(s) in 20 object(s) allocated from:
#0 0x7f6fc16e3808 in __interceptor_malloc ../../../../src/libsanitizer/asan/asan_malloc_linux.cc:144
#1 0x7f6fc1503e98 in g_malloc (/lib/x86_64-linux-gnu/libglib-2.0.so.0+0x57e98)
#2 0x564d63cafb6b in test_add_invalid_resource ../tests/unit/test-virtio-dmabuf.c:100
#3 0x7f6fc152659d (/lib/x86_64-linux-gnu/libglib-2.0.so.0+0x7a59d)
SUMMARY: AddressSanitizer: 320 byte(s) leaked in 20 allocation(s).
The changes at virtio_add_resource() itself are not strictly necessary
for the memleak fix, but they make it more obvious that, on an error
return, the passed object is not added to the hash.
Signed-off-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Message-Id: <c61c13f9a0c67dec473bdbfc8789c29ef26c900b.1696624734.git.quic_mathbern@quicinc.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Albert Esteve <aesteve@redhat.com>
Signed-off-by: Matheus Tavares Bernardino <<a href="mailto:quic_mathbern@quicinc.com" target="_blank">quic_mathbern@quicinc.com</a>><br>
---
hw/display/virtio-dmabuf.c | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/hw/display/virtio-dmabuf.c b/hw/display/virtio-dmabuf.c
index 4a8e430f3d..3dba4577ca 100644
--- a/hw/display/virtio-dmabuf.c
+++ b/hw/display/virtio-dmabuf.c
@@ -29,7 +29,7 @@ static int uuid_equal_func(const void *lhv, const void *rhv)
static bool virtio_add_resource(QemuUUID *uuid, VirtioSharedObject *value)
{
- bool result = false;
+ bool result = true;
g_mutex_lock(&lock);
if (resource_uuids == NULL) {
@@ -39,7 +39,9 @@ static bool virtio_add_resource(QemuUUID *uuid, VirtioSharedObject *value)
g_free);
}
if (g_hash_table_lookup(resource_uuids, uuid) == NULL) {
- result = g_hash_table_insert(resource_uuids, uuid, value);
+ g_hash_table_insert(resource_uuids, uuid, value);
+ } else {
+ result = false;
}
g_mutex_unlock(&lock);
@@ -57,6 +59,9 @@ bool virtio_add_dmabuf(QemuUUID *uuid, int udmabuf_fd)
vso->type = TYPE_DMABUF;
vso->value = GINT_TO_POINTER(udmabuf_fd);
result = virtio_add_resource(uuid, vso);
+ if (!result) {
+ g_free(vso);
+ }
return result;
}
@@ -72,6 +77,9 @@ bool virtio_add_vhost_device(QemuUUID *uuid, struct vhost_dev *dev)
vso->type = TYPE_VHOST_DEV;
vso->value = dev;
result = virtio_add_resource(uuid, vso);
+ if (!result) {
+ g_free(vso);
+ }
return result;
}
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 38/78] hw/i386/pc: Merge two if statements into one
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (36 preceding siblings ...)
2023-10-19 18:22 ` [PULL v2 37/78] hw/display: fix memleak from virtio_add_resource Michael S. Tsirkin
@ 2023-10-19 18:22 ` Michael S. Tsirkin
2023-10-19 18:22 ` [PULL v2 39/78] hw/i386/pc_piix: Allow for setting properties before realizing PIIX3 south bridge Michael S. Tsirkin
` (40 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:22 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Bernhard Beschow, Marcel Apfelbaum, Paolo Bonzini,
Richard Henderson, Eduardo Habkost
From: Bernhard Beschow <shentey@gmail.com>
By being the only entity assigning a non-NULL value to "rtc_irq", the first if
statement determines whether the second if statement is executed. So merge the
two statements into one.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20231007123843.127151-2-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/i386/pc.c | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index bb3854d1d0..7e6c4dc526 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1199,7 +1199,6 @@ void pc_basic_device_init(struct PCMachineState *pcms,
DeviceState *hpet = NULL;
int pit_isa_irq = 0;
qemu_irq pit_alt_irq = NULL;
- qemu_irq rtc_irq = NULL;
ISADevice *pit = NULL;
MemoryRegion *ioport80_io = g_new(MemoryRegion, 1);
MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1);
@@ -1219,6 +1218,8 @@ void pc_basic_device_init(struct PCMachineState *pcms,
*/
if (pcms->hpet_enabled && (!kvm_irqchip_in_kernel() ||
kvm_has_pit_state2())) {
+ qemu_irq rtc_irq;
+
hpet = qdev_try_new(TYPE_HPET);
if (!hpet) {
error_report("couldn't create HPET device");
@@ -1243,9 +1244,6 @@ void pc_basic_device_init(struct PCMachineState *pcms,
pit_isa_irq = -1;
pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
- }
-
- if (rtc_irq) {
qdev_connect_gpio_out(DEVICE(rtc_state), 0, rtc_irq);
} else {
uint32_t irq = object_property_get_uint(OBJECT(rtc_state),
@@ -1253,6 +1251,7 @@ void pc_basic_device_init(struct PCMachineState *pcms,
&error_fatal);
isa_connect_gpio_out(rtc_state, 0, irq);
}
+
object_property_add_alias(OBJECT(pcms), "rtc-time", OBJECT(rtc_state),
"date");
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 39/78] hw/i386/pc_piix: Allow for setting properties before realizing PIIX3 south bridge
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (37 preceding siblings ...)
2023-10-19 18:22 ` [PULL v2 38/78] hw/i386/pc: Merge two if statements into one Michael S. Tsirkin
@ 2023-10-19 18:22 ` Michael S. Tsirkin
2023-10-19 18:22 ` [PULL v2 40/78] hw/i386/pc_piix: Assign PIIX3's ISA interrupts before its realize() Michael S. Tsirkin
` (39 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:22 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Bernhard Beschow, Paolo Bonzini, Richard Henderson,
Eduardo Habkost, Marcel Apfelbaum
From: Bernhard Beschow <shentey@gmail.com>
The next patches will need to take advantage of it.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231007123843.127151-3-shentey@gmail.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/i386/pc_piix.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index e36a3262b2..6d2f5509e6 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -264,7 +264,8 @@ static void pc_init1(MachineState *machine,
PIIX3State *piix3;
PCIDevice *pci_dev;
- pci_dev = pci_create_simple_multifunction(pci_bus, -1, TYPE_PIIX3_DEVICE);
+ pci_dev = pci_new_multifunction(-1, TYPE_PIIX3_DEVICE);
+ pci_realize_and_unref(pci_dev, pci_bus, &error_fatal);
if (xen_enabled()) {
pci_device_set_intx_routing_notifier(
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 40/78] hw/i386/pc_piix: Assign PIIX3's ISA interrupts before its realize()
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (38 preceding siblings ...)
2023-10-19 18:22 ` [PULL v2 39/78] hw/i386/pc_piix: Allow for setting properties before realizing PIIX3 south bridge Michael S. Tsirkin
@ 2023-10-19 18:22 ` Michael S. Tsirkin
2023-10-19 18:22 ` [PULL v2 41/78] hw/isa/piix3: Resolve redundant PIIX_NUM_PIC_IRQS Michael S. Tsirkin
` (38 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:22 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Bernhard Beschow, Marcel Apfelbaum, Paolo Bonzini,
Richard Henderson, Eduardo Habkost
From: Bernhard Beschow <shentey@gmail.com>
Unlike its PIIX4 counterpart, TYPE_PIIX3_DEVICE doesn't instantiate a PIC
itself. Instead, it relies on the board to do so. This means that the board
needs to wire the ISA IRQs to the PIIX3 device model. As long as the board
assigns the ISA IRQs after PIIX3's realize(), internal devices can't be wired in
pci_piix3_realize() since the qemu_irqs are still NULL. Fix that by assigning
the ISA interrupts before realize(). This will allow for embedding child devices
into the host device as already done for PIIX4.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20231007123843.127151-4-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/i386/pc_piix.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 6d2f5509e6..a003923788 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -265,6 +265,8 @@ static void pc_init1(MachineState *machine,
PCIDevice *pci_dev;
pci_dev = pci_new_multifunction(-1, TYPE_PIIX3_DEVICE);
+ piix3 = PIIX3_PCI_DEVICE(pci_dev);
+ piix3->pic = x86ms->gsi;
pci_realize_and_unref(pci_dev, pci_bus, &error_fatal);
if (xen_enabled()) {
@@ -281,8 +283,6 @@ static void pc_init1(MachineState *machine,
XEN_IOAPIC_NUM_PIRQS);
}
- piix3 = PIIX3_PCI_DEVICE(pci_dev);
- piix3->pic = x86ms->gsi;
piix3_devfn = piix3->dev.devfn;
isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0"));
rtc_state = ISA_DEVICE(object_resolve_path_component(OBJECT(pci_dev),
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 41/78] hw/isa/piix3: Resolve redundant PIIX_NUM_PIC_IRQS
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (39 preceding siblings ...)
2023-10-19 18:22 ` [PULL v2 40/78] hw/i386/pc_piix: Assign PIIX3's ISA interrupts before its realize() Michael S. Tsirkin
@ 2023-10-19 18:22 ` Michael S. Tsirkin
2023-10-19 18:23 ` [PULL v2 42/78] hw/i386/pc_piix: Wire PIIX3's ISA interrupts by new "isa-irqs" property Michael S. Tsirkin
` (37 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:22 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Bernhard Beschow, Hervé Poussineau,
Philippe Mathieu-Daudé, Marcel Apfelbaum, Aurelien Jarno
From: Bernhard Beschow <shentey@gmail.com>
PIIX_NUM_PIC_IRQS is assumed to be the same as ISA_NUM_IRQS, otherwise
inconsistencies can occur.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231007123843.127151-5-shentey@gmail.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
include/hw/southbridge/piix.h | 5 ++---
hw/isa/piix3.c | 8 ++++----
2 files changed, 6 insertions(+), 7 deletions(-)
diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
index 278171752f..2317bb7974 100644
--- a/include/hw/southbridge/piix.h
+++ b/include/hw/southbridge/piix.h
@@ -27,7 +27,6 @@
*/
#define PIIX_RCR_IOPORT 0xcf9
-#define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */
#define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */
struct PIIXState {
@@ -39,10 +38,10 @@ struct PIIXState {
* So one PIC level is tracked by PIIX_NUM_PIRQS bits.
*
* PIRQ is mapped to PIC pins, we track it by
- * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with
+ * PIIX_NUM_PIRQS * ISA_NUM_IRQS = 64 bits with
* pic_irq * PIIX_NUM_PIRQS + pirq
*/
-#if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
+#if ISA_NUM_IRQS * PIIX_NUM_PIRQS > 64
#error "unable to encode pic state in 64bit in pic_levels."
#endif
uint64_t pic_levels;
diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c
index 117024e450..7240c91440 100644
--- a/hw/isa/piix3.c
+++ b/hw/isa/piix3.c
@@ -48,7 +48,7 @@ static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level)
uint64_t mask;
pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
- if (pic_irq >= PIIX_NUM_PIC_IRQS) {
+ if (pic_irq >= ISA_NUM_IRQS) {
return;
}
@@ -62,7 +62,7 @@ static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
int pic_irq;
pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
- if (pic_irq >= PIIX_NUM_PIC_IRQS) {
+ if (pic_irq >= ISA_NUM_IRQS) {
return;
}
@@ -83,7 +83,7 @@ static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
int irq = piix3->dev.config[PIIX_PIRQCA + pin];
PCIINTxRoute route;
- if (irq < PIIX_NUM_PIC_IRQS) {
+ if (irq < ISA_NUM_IRQS) {
route.mode = PCI_INTX_ENABLED;
route.irq = irq;
} else {
@@ -115,7 +115,7 @@ static void piix3_write_config(PCIDevice *dev,
pci_bus_fire_intx_routing_notifier(pci_get_bus(&piix3->dev));
piix3_update_irq_levels(piix3);
- for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) {
+ for (pic_irq = 0; pic_irq < ISA_NUM_IRQS; pic_irq++) {
piix3_set_irq_pic(piix3, pic_irq);
}
}
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 42/78] hw/i386/pc_piix: Wire PIIX3's ISA interrupts by new "isa-irqs" property
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (40 preceding siblings ...)
2023-10-19 18:22 ` [PULL v2 41/78] hw/isa/piix3: Resolve redundant PIIX_NUM_PIC_IRQS Michael S. Tsirkin
@ 2023-10-19 18:23 ` Michael S. Tsirkin
2023-10-19 18:23 ` [PULL v2 43/78] hw/i386/pc_piix: Remove redundant "piix3" variable Michael S. Tsirkin
` (36 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:23 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Bernhard Beschow, Paolo Bonzini, Richard Henderson,
Eduardo Habkost, Marcel Apfelbaum, Hervé Poussineau,
Philippe Mathieu-Daudé, Aurelien Jarno
From: Bernhard Beschow <shentey@gmail.com>
Avoid assigning the private member of struct PIIX3State from outside which goes
against best QOM practices. Instead, implement best QOM practice by adding an
"isa-irqs" array property to TYPE_PIIX3_DEVICE and assign it in board code, i.e.
from outside.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20231007123843.127151-6-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
include/hw/southbridge/piix.h | 2 +-
hw/i386/pc_piix.c | 7 ++++++-
hw/isa/piix3.c | 2 ++
3 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
index 2317bb7974..bb898c6c88 100644
--- a/include/hw/southbridge/piix.h
+++ b/include/hw/southbridge/piix.h
@@ -46,7 +46,7 @@ struct PIIXState {
#endif
uint64_t pic_levels;
- qemu_irq *pic;
+ qemu_irq pic[ISA_NUM_IRQS];
/* This member isn't used. Just for save/load compatibility */
int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index a003923788..4dc7298c15 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -263,10 +263,15 @@ static void pc_init1(MachineState *machine,
if (pcmc->pci_enabled) {
PIIX3State *piix3;
PCIDevice *pci_dev;
+ DeviceState *dev;
+ size_t i;
pci_dev = pci_new_multifunction(-1, TYPE_PIIX3_DEVICE);
piix3 = PIIX3_PCI_DEVICE(pci_dev);
- piix3->pic = x86ms->gsi;
+ dev = DEVICE(pci_dev);
+ for (i = 0; i < ISA_NUM_IRQS; i++) {
+ qdev_connect_gpio_out_named(dev, "isa-irqs", i, x86ms->gsi[i]);
+ }
pci_realize_and_unref(pci_dev, pci_bus, &error_fatal);
if (xen_enabled()) {
diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c
index 7240c91440..c17547a2c0 100644
--- a/hw/isa/piix3.c
+++ b/hw/isa/piix3.c
@@ -312,6 +312,8 @@ static void pci_piix3_init(Object *obj)
{
PIIX3State *d = PIIX3_PCI_DEVICE(obj);
+ qdev_init_gpio_out_named(DEVICE(obj), d->pic, "isa-irqs", ISA_NUM_IRQS);
+
object_initialize_child(obj, "rtc", &d->rtc, TYPE_MC146818_RTC);
}
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 43/78] hw/i386/pc_piix: Remove redundant "piix3" variable
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (41 preceding siblings ...)
2023-10-19 18:23 ` [PULL v2 42/78] hw/i386/pc_piix: Wire PIIX3's ISA interrupts by new "isa-irqs" property Michael S. Tsirkin
@ 2023-10-19 18:23 ` Michael S. Tsirkin
2023-10-19 18:23 ` [PULL v2 44/78] hw/isa/piix3: Rename "pic" attribute to "isa_irqs_in" Michael S. Tsirkin
` (35 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:23 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Bernhard Beschow, Paolo Bonzini, Richard Henderson,
Eduardo Habkost, Marcel Apfelbaum
From: Bernhard Beschow <shentey@gmail.com>
The variable is never used by its declared type. Eliminate it.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20231007123843.127151-7-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/i386/pc_piix.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 4dc7298c15..cd6c00c0b3 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -261,13 +261,11 @@ static void pc_init1(MachineState *machine,
gsi_state = pc_gsi_create(&x86ms->gsi, pcmc->pci_enabled);
if (pcmc->pci_enabled) {
- PIIX3State *piix3;
PCIDevice *pci_dev;
DeviceState *dev;
size_t i;
pci_dev = pci_new_multifunction(-1, TYPE_PIIX3_DEVICE);
- piix3 = PIIX3_PCI_DEVICE(pci_dev);
dev = DEVICE(pci_dev);
for (i = 0; i < ISA_NUM_IRQS; i++) {
qdev_connect_gpio_out_named(dev, "isa-irqs", i, x86ms->gsi[i]);
@@ -288,8 +286,8 @@ static void pc_init1(MachineState *machine,
XEN_IOAPIC_NUM_PIRQS);
}
- piix3_devfn = piix3->dev.devfn;
- isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0"));
+ piix3_devfn = pci_dev->devfn;
+ isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(pci_dev), "isa.0"));
rtc_state = ISA_DEVICE(object_resolve_path_component(OBJECT(pci_dev),
"rtc"));
} else {
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 44/78] hw/isa/piix3: Rename "pic" attribute to "isa_irqs_in"
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (42 preceding siblings ...)
2023-10-19 18:23 ` [PULL v2 43/78] hw/i386/pc_piix: Remove redundant "piix3" variable Michael S. Tsirkin
@ 2023-10-19 18:23 ` Michael S. Tsirkin
2023-10-19 18:23 ` [PULL v2 45/78] hw/i386/pc_q35: Wire ICH9 LPC function's interrupts before its realize() Michael S. Tsirkin
` (34 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:23 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Bernhard Beschow, Philippe Mathieu-Daudé,
Aurelien Jarno, Marcel Apfelbaum, Hervé Poussineau
From: Bernhard Beschow <shentey@gmail.com>
TYPE_PIIX3_DEVICE doesn't instantiate a PIC since it relies on the board to do
so. The "pic" attribute, however, suggests that there is one. Rename the
attribute to reflect that it represents ISA interrupt lines. Use the same naming
convention as in the VIA south bridges as well as in TYPE_I82378.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20231007123843.127151-8-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
include/hw/southbridge/piix.h | 2 +-
hw/isa/piix3.c | 5 +++--
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
index bb898c6c88..b07ff6bb26 100644
--- a/include/hw/southbridge/piix.h
+++ b/include/hw/southbridge/piix.h
@@ -46,7 +46,7 @@ struct PIIXState {
#endif
uint64_t pic_levels;
- qemu_irq pic[ISA_NUM_IRQS];
+ qemu_irq isa_irqs_in[ISA_NUM_IRQS];
/* This member isn't used. Just for save/load compatibility */
int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c
index c17547a2c0..616f5418fa 100644
--- a/hw/isa/piix3.c
+++ b/hw/isa/piix3.c
@@ -36,7 +36,7 @@
static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
{
- qemu_set_irq(piix3->pic[pic_irq],
+ qemu_set_irq(piix3->isa_irqs_in[pic_irq],
!!(piix3->pic_levels &
(((1ULL << PIIX_NUM_PIRQS) - 1) <<
(pic_irq * PIIX_NUM_PIRQS))));
@@ -312,7 +312,8 @@ static void pci_piix3_init(Object *obj)
{
PIIX3State *d = PIIX3_PCI_DEVICE(obj);
- qdev_init_gpio_out_named(DEVICE(obj), d->pic, "isa-irqs", ISA_NUM_IRQS);
+ qdev_init_gpio_out_named(DEVICE(obj), d->isa_irqs_in, "isa-irqs",
+ ISA_NUM_IRQS);
object_initialize_child(obj, "rtc", &d->rtc, TYPE_MC146818_RTC);
}
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 45/78] hw/i386/pc_q35: Wire ICH9 LPC function's interrupts before its realize()
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (43 preceding siblings ...)
2023-10-19 18:23 ` [PULL v2 44/78] hw/isa/piix3: Rename "pic" attribute to "isa_irqs_in" Michael S. Tsirkin
@ 2023-10-19 18:23 ` Michael S. Tsirkin
2023-10-19 18:23 ` [PULL v2 46/78] hw/isa/piix3: Wire PIC IRQs to ISA bus in host device Michael S. Tsirkin
` (33 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:23 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Bernhard Beschow, Paolo Bonzini, Richard Henderson,
Eduardo Habkost, Marcel Apfelbaum
From: Bernhard Beschow <shentey@gmail.com>
When the board assigns the ISA IRQs after the device's realize(), internal
devices such as the RTC can't be wired in ich9_lpc_realize() since the qemu_irqs
are still NULL. Fix that by assigning the ISA interrupts before realize().
This change is necessary for PIIX consolidation because PIIX4 wires the RTC
interrupts in its realize() method, so PIIX3 needs to do so as well. Since the
PC and Q35 boards share RTC code, and since PIIX3 needs the change, ICH9 needs
to be adapted as well.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20231007123843.127151-9-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/i386/pc_q35.c | 14 +++++++-------
hw/isa/lpc_ich9.c | 6 +++---
2 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index a7386f2ca2..597943ff1b 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -242,11 +242,18 @@ static void pc_q35_init(MachineState *machine)
host_bus = PCI_BUS(qdev_get_child_bus(DEVICE(phb), "pcie.0"));
pcms->bus = host_bus;
+ /* irq lines */
+ gsi_state = pc_gsi_create(&x86ms->gsi, pcmc->pci_enabled);
+
/* create ISA bus */
lpc = pci_new_multifunction(PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC),
TYPE_ICH9_LPC_DEVICE);
qdev_prop_set_bit(DEVICE(lpc), "smm-enabled",
x86_machine_is_smm_enabled(x86ms));
+ lpc_dev = DEVICE(lpc);
+ for (i = 0; i < IOAPIC_NUM_PINS; i++) {
+ qdev_connect_gpio_out_named(lpc_dev, ICH9_GPIO_GSI, i, x86ms->gsi[i]);
+ }
pci_realize_and_unref(lpc, host_bus, &error_fatal);
rtc_state = ISA_DEVICE(object_resolve_path_component(OBJECT(lpc), "rtc"));
@@ -273,13 +280,6 @@ static void pc_q35_init(MachineState *machine)
"true", true);
}
- /* irq lines */
- gsi_state = pc_gsi_create(&x86ms->gsi, pcmc->pci_enabled);
-
- lpc_dev = DEVICE(lpc);
- for (i = 0; i < IOAPIC_NUM_PINS; i++) {
- qdev_connect_gpio_out_named(lpc_dev, ICH9_GPIO_GSI, i, x86ms->gsi[i]);
- }
isa_bus = ISA_BUS(qdev_get_child_bus(lpc_dev, "isa.0"));
if (x86ms->pic == ON_OFF_AUTO_ON || x86ms->pic == ON_OFF_AUTO_AUTO) {
diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c
index 3f59980aa0..3fcefc5a8a 100644
--- a/hw/isa/lpc_ich9.c
+++ b/hw/isa/lpc_ich9.c
@@ -675,6 +675,9 @@ static void ich9_lpc_initfn(Object *obj)
object_initialize_child(obj, "rtc", &lpc->rtc, TYPE_MC146818_RTC);
+ qdev_init_gpio_out_named(DEVICE(lpc), lpc->gsi, ICH9_GPIO_GSI,
+ IOAPIC_NUM_PINS);
+
object_property_add_uint8_ptr(obj, ACPI_PM_PROP_SCI_INT,
&lpc->sci_gsi, OBJ_PROP_FLAG_READ);
object_property_add_uint8_ptr(OBJECT(lpc), ACPI_PM_PROP_ACPI_ENABLE_CMD,
@@ -691,7 +694,6 @@ static void ich9_lpc_initfn(Object *obj)
static void ich9_lpc_realize(PCIDevice *d, Error **errp)
{
ICH9LPCState *lpc = ICH9_LPC_DEVICE(d);
- DeviceState *dev = DEVICE(d);
PCIBus *pci_bus = pci_get_bus(d);
ISABus *isa_bus;
@@ -734,8 +736,6 @@ static void ich9_lpc_realize(PCIDevice *d, Error **errp)
ICH9_RST_CNT_IOPORT, &lpc->rst_cnt_mem,
1);
- qdev_init_gpio_out_named(dev, lpc->gsi, ICH9_GPIO_GSI, IOAPIC_NUM_PINS);
-
isa_bus_register_input_irqs(isa_bus, lpc->gsi);
i8257_dma_init(isa_bus, 0);
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 46/78] hw/isa/piix3: Wire PIC IRQs to ISA bus in host device
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (44 preceding siblings ...)
2023-10-19 18:23 ` [PULL v2 45/78] hw/i386/pc_q35: Wire ICH9 LPC function's interrupts before its realize() Michael S. Tsirkin
@ 2023-10-19 18:23 ` Michael S. Tsirkin
2023-10-19 18:23 ` [PULL v2 47/78] hw/i386/pc: Wire RTC ISA IRQs in south bridges Michael S. Tsirkin
` (32 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:23 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Bernhard Beschow, Paolo Bonzini, Richard Henderson,
Eduardo Habkost, Marcel Apfelbaum
From: Bernhard Beschow <shentey@gmail.com>
Thie PIIX3 south bridge implements both the PIC and the ISA bus, so wiring the
interrupts there makes the device model more self-contained. Furthermore, this
allows the ISA interrupts to be wired to internal child devices in
pci_piix3_realize() which will be performed in subsequent patches.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20231007123843.127151-10-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/i386/pc_piix.c | 2 +-
hw/isa/piix3.c | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index cd6c00c0b3..5988656279 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -293,6 +293,7 @@ static void pc_init1(MachineState *machine,
} else {
isa_bus = isa_bus_new(NULL, system_memory, system_io,
&error_abort);
+ isa_bus_register_input_irqs(isa_bus, x86ms->gsi);
rtc_state = isa_new(TYPE_MC146818_RTC);
qdev_prop_set_int32(DEVICE(rtc_state), "base_year", 2000);
@@ -301,7 +302,6 @@ static void pc_init1(MachineState *machine,
i8257_dma_init(isa_bus, 0);
pcms->hpet_enabled = false;
}
- isa_bus_register_input_irqs(isa_bus, x86ms->gsi);
if (x86ms->pic == ON_OFF_AUTO_ON || x86ms->pic == ON_OFF_AUTO_AUTO) {
pc_i8259_create(isa_bus, gsi_state->i8259_irq);
diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c
index 616f5418fa..3e7c42fa68 100644
--- a/hw/isa/piix3.c
+++ b/hw/isa/piix3.c
@@ -278,6 +278,8 @@ static void pci_piix3_realize(PCIDevice *dev, Error **errp)
memory_region_add_subregion_overlap(pci_address_space_io(dev),
PIIX_RCR_IOPORT, &d->rcr_mem, 1);
+ isa_bus_register_input_irqs(isa_bus, d->isa_irqs_in);
+
i8257_dma_init(isa_bus, 0);
/* RTC */
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 47/78] hw/i386/pc: Wire RTC ISA IRQs in south bridges
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (45 preceding siblings ...)
2023-10-19 18:23 ` [PULL v2 46/78] hw/isa/piix3: Wire PIC IRQs to ISA bus in host device Michael S. Tsirkin
@ 2023-10-19 18:23 ` Michael S. Tsirkin
2023-10-19 18:23 ` [PULL v2 48/78] hw/isa/piix3: Create IDE controller in host device Michael S. Tsirkin
` (31 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:23 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Bernhard Beschow, Marcel Apfelbaum, Paolo Bonzini,
Richard Henderson, Eduardo Habkost
From: Bernhard Beschow <shentey@gmail.com>
Makes the south bridges a bit more self-contained and aligns PIIX3 more with
PIIX4. The latter is needed for consolidating the PIIX south bridges.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20231007123843.127151-11-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/i386/pc.c | 7 ++-----
hw/isa/lpc_ich9.c | 3 +++
hw/isa/piix3.c | 3 +++
3 files changed, 8 insertions(+), 5 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 7e6c4dc526..355e1b7cf6 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1244,12 +1244,9 @@ void pc_basic_device_init(struct PCMachineState *pcms,
pit_isa_irq = -1;
pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
+
+ /* overwrite connection created by south bridge */
qdev_connect_gpio_out(DEVICE(rtc_state), 0, rtc_irq);
- } else {
- uint32_t irq = object_property_get_uint(OBJECT(rtc_state),
- "irq",
- &error_fatal);
- isa_connect_gpio_out(rtc_state, 0, irq);
}
object_property_add_alias(OBJECT(pcms), "rtc-time", OBJECT(rtc_state),
diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c
index 3fcefc5a8a..23eba64f22 100644
--- a/hw/isa/lpc_ich9.c
+++ b/hw/isa/lpc_ich9.c
@@ -696,6 +696,7 @@ static void ich9_lpc_realize(PCIDevice *d, Error **errp)
ICH9LPCState *lpc = ICH9_LPC_DEVICE(d);
PCIBus *pci_bus = pci_get_bus(d);
ISABus *isa_bus;
+ uint32_t irq;
if ((lpc->smi_host_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT)) &&
!(lpc->smi_host_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT))) {
@@ -745,6 +746,8 @@ static void ich9_lpc_realize(PCIDevice *d, Error **errp)
if (!qdev_realize(DEVICE(&lpc->rtc), BUS(isa_bus), errp)) {
return;
}
+ irq = object_property_get_uint(OBJECT(&lpc->rtc), "irq", &error_fatal);
+ isa_connect_gpio_out(ISA_DEVICE(&lpc->rtc), 0, irq);
pci_bus_irqs(pci_bus, ich9_lpc_set_irq, d, ICH9_LPC_NB_PIRQS);
pci_bus_map_irqs(pci_bus, ich9_lpc_map_irq);
diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c
index 3e7c42fa68..11d72ca2bb 100644
--- a/hw/isa/piix3.c
+++ b/hw/isa/piix3.c
@@ -266,6 +266,7 @@ static void pci_piix3_realize(PCIDevice *dev, Error **errp)
{
PIIX3State *d = PIIX3_PCI_DEVICE(dev);
ISABus *isa_bus;
+ uint32_t irq;
isa_bus = isa_bus_new(DEVICE(d), pci_address_space(dev),
pci_address_space_io(dev), errp);
@@ -287,6 +288,8 @@ static void pci_piix3_realize(PCIDevice *dev, Error **errp)
if (!qdev_realize(DEVICE(&d->rtc), BUS(isa_bus), errp)) {
return;
}
+ irq = object_property_get_uint(OBJECT(&d->rtc), "irq", &error_fatal);
+ isa_connect_gpio_out(ISA_DEVICE(&d->rtc), 0, irq);
}
static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *scope)
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 48/78] hw/isa/piix3: Create IDE controller in host device
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (46 preceding siblings ...)
2023-10-19 18:23 ` [PULL v2 47/78] hw/i386/pc: Wire RTC ISA IRQs in south bridges Michael S. Tsirkin
@ 2023-10-19 18:23 ` Michael S. Tsirkin
2023-10-19 18:23 ` [PULL v2 49/78] hw/isa/piix3: Create USB " Michael S. Tsirkin
` (30 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:23 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Bernhard Beschow, Paolo Bonzini, Marcel Apfelbaum,
Richard Henderson, Eduardo Habkost, Hervé Poussineau,
Philippe Mathieu-Daudé, Aurelien Jarno
From: Bernhard Beschow <shentey@gmail.com>
The IDE controller is an integral part of PIIX3 (function 1). So create it as
part of the south bridge.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231007123843.127151-12-shentey@gmail.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
include/hw/southbridge/piix.h | 2 ++
hw/i386/pc_piix.c | 13 ++++++-------
hw/isa/piix3.c | 9 +++++++++
hw/i386/Kconfig | 1 -
hw/isa/Kconfig | 1 +
5 files changed, 18 insertions(+), 8 deletions(-)
diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
index b07ff6bb26..1daeff397c 100644
--- a/include/hw/southbridge/piix.h
+++ b/include/hw/southbridge/piix.h
@@ -13,6 +13,7 @@
#define HW_SOUTHBRIDGE_PIIX_H
#include "hw/pci/pci_device.h"
+#include "hw/ide/pci.h"
#include "hw/rtc/mc146818rtc.h"
/* PIRQRC[A:D]: PIRQx Route Control Registers */
@@ -52,6 +53,7 @@ struct PIIXState {
int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
MC146818RtcState rtc;
+ PCIIDEState ide;
/* Reset Control Register contents */
uint8_t rcr;
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 5988656279..c98a997482 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -43,7 +43,6 @@
#include "net/net.h"
#include "hw/ide/isa.h"
#include "hw/ide/pci.h"
-#include "hw/ide/piix.h"
#include "hw/irq.h"
#include "sysemu/kvm.h"
#include "hw/i386/kvm/clock.h"
@@ -290,6 +289,10 @@ static void pc_init1(MachineState *machine,
isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(pci_dev), "isa.0"));
rtc_state = ISA_DEVICE(object_resolve_path_component(OBJECT(pci_dev),
"rtc"));
+ dev = DEVICE(object_resolve_path_component(OBJECT(pci_dev), "ide"));
+ pci_ide_create_devs(PCI_DEVICE(dev));
+ idebus[0] = qdev_get_child_bus(dev, "ide.0");
+ idebus[1] = qdev_get_child_bus(dev, "ide.1");
} else {
isa_bus = isa_bus_new(NULL, system_memory, system_io,
&error_abort);
@@ -301,6 +304,8 @@ static void pc_init1(MachineState *machine,
i8257_dma_init(isa_bus, 0);
pcms->hpet_enabled = false;
+ idebus[0] = NULL;
+ idebus[1] = NULL;
}
if (x86ms->pic == ON_OFF_AUTO_ON || x86ms->pic == ON_OFF_AUTO_AUTO) {
@@ -329,12 +334,6 @@ static void pc_init1(MachineState *machine,
pc_nic_init(pcmc, isa_bus, pci_bus);
if (pcmc->pci_enabled) {
- PCIDevice *dev;
-
- dev = pci_create_simple(pci_bus, piix3_devfn + 1, TYPE_PIIX3_IDE);
- pci_ide_create_devs(dev);
- idebus[0] = qdev_get_child_bus(&dev->qdev, "ide.0");
- idebus[1] = qdev_get_child_bus(&dev->qdev, "ide.1");
pc_cmos_init(pcms, idebus[0], idebus[1], rtc_state);
}
#ifdef CONFIG_IDE_ISA
diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c
index 11d72ca2bb..3f1dabade0 100644
--- a/hw/isa/piix3.c
+++ b/hw/isa/piix3.c
@@ -29,6 +29,7 @@
#include "hw/southbridge/piix.h"
#include "hw/irq.h"
#include "hw/qdev-properties.h"
+#include "hw/ide/piix.h"
#include "hw/isa/isa.h"
#include "sysemu/runstate.h"
#include "migration/vmstate.h"
@@ -265,6 +266,7 @@ static const MemoryRegionOps rcr_ops = {
static void pci_piix3_realize(PCIDevice *dev, Error **errp)
{
PIIX3State *d = PIIX3_PCI_DEVICE(dev);
+ PCIBus *pci_bus = pci_get_bus(dev);
ISABus *isa_bus;
uint32_t irq;
@@ -290,6 +292,12 @@ static void pci_piix3_realize(PCIDevice *dev, Error **errp)
}
irq = object_property_get_uint(OBJECT(&d->rtc), "irq", &error_fatal);
isa_connect_gpio_out(ISA_DEVICE(&d->rtc), 0, irq);
+
+ /* IDE */
+ qdev_prop_set_int32(DEVICE(&d->ide), "addr", dev->devfn + 1);
+ if (!qdev_realize(DEVICE(&d->ide), BUS(pci_bus), errp)) {
+ return;
+ }
}
static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *scope)
@@ -321,6 +329,7 @@ static void pci_piix3_init(Object *obj)
ISA_NUM_IRQS);
object_initialize_child(obj, "rtc", &d->rtc, TYPE_MC146818_RTC);
+ object_initialize_child(obj, "ide", &d->ide, TYPE_PIIX3_IDE);
}
static void pci_piix3_class_init(ObjectClass *klass, void *data)
diff --git a/hw/i386/Kconfig b/hw/i386/Kconfig
index 9051083c1e..ade817f1b6 100644
--- a/hw/i386/Kconfig
+++ b/hw/i386/Kconfig
@@ -73,7 +73,6 @@ config I440FX
select PC_ACPI
select PCI_I440FX
select PIIX3
- select IDE_PIIX
select DIMM
select SMBIOS
select FW_CFG_DMA
diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig
index c10cbc5fc1..28345edbb3 100644
--- a/hw/isa/Kconfig
+++ b/hw/isa/Kconfig
@@ -34,6 +34,7 @@ config PC87312
config PIIX3
bool
select I8257
+ select IDE_PIIX
select ISA_BUS
select MC146818RTC
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 49/78] hw/isa/piix3: Create USB controller in host device
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (47 preceding siblings ...)
2023-10-19 18:23 ` [PULL v2 48/78] hw/isa/piix3: Create IDE controller in host device Michael S. Tsirkin
@ 2023-10-19 18:23 ` Michael S. Tsirkin
2023-10-19 18:23 ` [PULL v2 50/78] hw/isa/piix3: Create power management " Michael S. Tsirkin
` (29 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:23 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Bernhard Beschow, Marcel Apfelbaum, Paolo Bonzini,
Richard Henderson, Eduardo Habkost, Hervé Poussineau,
Philippe Mathieu-Daudé, Aurelien Jarno
From: Bernhard Beschow <shentey@gmail.com>
The USB controller is an integral part of PIIX3 (function 2). So create
it as part of the south bridge.
Note that the USB function is optional in QEMU. This is why it gets
object_initialize_child()'ed in realize rather than in instance_init.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231007123843.127151-13-shentey@gmail.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
include/hw/southbridge/piix.h | 4 ++++
hw/i386/pc_piix.c | 7 ++-----
hw/isa/piix3.c | 16 ++++++++++++++++
hw/isa/Kconfig | 1 +
4 files changed, 23 insertions(+), 5 deletions(-)
diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
index 1daeff397c..5cd866f1f2 100644
--- a/include/hw/southbridge/piix.h
+++ b/include/hw/southbridge/piix.h
@@ -15,6 +15,7 @@
#include "hw/pci/pci_device.h"
#include "hw/ide/pci.h"
#include "hw/rtc/mc146818rtc.h"
+#include "hw/usb/hcd-uhci.h"
/* PIRQRC[A:D]: PIRQx Route Control Registers */
#define PIIX_PIRQCA 0x60
@@ -54,12 +55,15 @@ struct PIIXState {
MC146818RtcState rtc;
PCIIDEState ide;
+ UHCIState uhci;
/* Reset Control Register contents */
uint8_t rcr;
/* IO memory region for Reset Control Register (PIIX_RCR_IOPORT) */
MemoryRegion rcr_mem;
+
+ bool has_usb;
};
typedef struct PIIXState PIIX3State;
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index c98a997482..8dcd6851d0 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -51,7 +51,6 @@
#include "exec/memory.h"
#include "hw/acpi/acpi.h"
#include "hw/acpi/piix4.h"
-#include "hw/usb/hcd-uhci.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
#include "sysemu/xen.h"
@@ -265,6 +264,8 @@ static void pc_init1(MachineState *machine,
size_t i;
pci_dev = pci_new_multifunction(-1, TYPE_PIIX3_DEVICE);
+ object_property_set_bool(OBJECT(pci_dev), "has-usb",
+ machine_usb(machine), &error_abort);
dev = DEVICE(pci_dev);
for (i = 0; i < ISA_NUM_IRQS; i++) {
qdev_connect_gpio_out_named(dev, "isa-irqs", i, x86ms->gsi[i]);
@@ -359,10 +360,6 @@ static void pc_init1(MachineState *machine,
}
#endif
- if (pcmc->pci_enabled && machine_usb(machine)) {
- pci_create_simple(pci_bus, piix3_devfn + 2, TYPE_PIIX3_USB_UHCI);
- }
-
if (pcmc->pci_enabled && x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) {
PCIDevice *piix4_pm;
diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c
index 3f1dabade0..aebc0da23b 100644
--- a/hw/isa/piix3.c
+++ b/hw/isa/piix3.c
@@ -298,6 +298,16 @@ static void pci_piix3_realize(PCIDevice *dev, Error **errp)
if (!qdev_realize(DEVICE(&d->ide), BUS(pci_bus), errp)) {
return;
}
+
+ /* USB */
+ if (d->has_usb) {
+ object_initialize_child(OBJECT(dev), "uhci", &d->uhci,
+ TYPE_PIIX3_USB_UHCI);
+ qdev_prop_set_int32(DEVICE(&d->uhci), "addr", dev->devfn + 2);
+ if (!qdev_realize(DEVICE(&d->uhci), BUS(pci_bus), errp)) {
+ return;
+ }
+ }
}
static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *scope)
@@ -332,6 +342,11 @@ static void pci_piix3_init(Object *obj)
object_initialize_child(obj, "ide", &d->ide, TYPE_PIIX3_IDE);
}
+static Property pci_piix3_props[] = {
+ DEFINE_PROP_BOOL("has-usb", PIIX3State, has_usb, true),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
static void pci_piix3_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@@ -352,6 +367,7 @@ static void pci_piix3_class_init(ObjectClass *klass, void *data)
* pc_piix.c's pc_init1()
*/
dc->user_creatable = false;
+ device_class_set_props(dc, pci_piix3_props);
adevc->build_dev_aml = build_pci_isa_aml;
}
diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig
index 28345edbb3..1076df69ca 100644
--- a/hw/isa/Kconfig
+++ b/hw/isa/Kconfig
@@ -37,6 +37,7 @@ config PIIX3
select IDE_PIIX
select ISA_BUS
select MC146818RTC
+ select USB_UHCI
config PIIX4
bool
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 50/78] hw/isa/piix3: Create power management controller in host device
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (48 preceding siblings ...)
2023-10-19 18:23 ` [PULL v2 49/78] hw/isa/piix3: Create USB " Michael S. Tsirkin
@ 2023-10-19 18:23 ` Michael S. Tsirkin
2023-10-19 18:23 ` [PULL v2 51/78] hw/isa/piix3: Drop the "3" from PIIX base class name Michael S. Tsirkin
` (28 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:23 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Bernhard Beschow, Paolo Bonzini, Richard Henderson,
Eduardo Habkost, Marcel Apfelbaum, Philippe Mathieu-Daudé,
Aurelien Jarno, Hervé Poussineau
From: Bernhard Beschow <shentey@gmail.com>
The power management controller is an integral part of PIIX3 (function 3). So
create it as part of the south bridge.
Note that the ACPI function is optional in QEMU. This is why it gets
object_initialize_child()'ed in realize rather than in instance_init.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231007123843.127151-14-shentey@gmail.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
include/hw/southbridge/piix.h | 6 ++++++
hw/i386/pc_piix.c | 24 +++++++++++-------------
hw/isa/piix3.c | 15 +++++++++++++++
hw/isa/Kconfig | 1 +
4 files changed, 33 insertions(+), 13 deletions(-)
diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
index 5cd866f1f2..c56ce49fd3 100644
--- a/include/hw/southbridge/piix.h
+++ b/include/hw/southbridge/piix.h
@@ -13,6 +13,7 @@
#define HW_SOUTHBRIDGE_PIIX_H
#include "hw/pci/pci_device.h"
+#include "hw/acpi/piix4.h"
#include "hw/ide/pci.h"
#include "hw/rtc/mc146818rtc.h"
#include "hw/usb/hcd-uhci.h"
@@ -56,6 +57,9 @@ struct PIIXState {
MC146818RtcState rtc;
PCIIDEState ide;
UHCIState uhci;
+ PIIX4PMState pm;
+
+ uint32_t smb_io_base;
/* Reset Control Register contents */
uint8_t rcr;
@@ -63,7 +67,9 @@ struct PIIXState {
/* IO memory region for Reset Control Register (PIIX_RCR_IOPORT) */
MemoryRegion rcr_mem;
+ bool has_acpi;
bool has_usb;
+ bool smm_enabled;
};
typedef struct PIIXState PIIX3State;
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 8dcd6851d0..70cffcfe4f 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -50,7 +50,6 @@
#include "hw/i2c/smbus_eeprom.h"
#include "exec/memory.h"
#include "hw/acpi/acpi.h"
-#include "hw/acpi/piix4.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
#include "sysemu/xen.h"
@@ -115,7 +114,7 @@ static void pc_init1(MachineState *machine,
MemoryRegion *system_io = get_system_io();
PCIBus *pci_bus = NULL;
ISABus *isa_bus;
- int piix3_devfn = -1;
+ Object *piix4_pm = NULL;
qemu_irq smi_irq;
GSIState *gsi_state;
BusState *idebus[MAX_IDE_BUS];
@@ -266,6 +265,13 @@ static void pc_init1(MachineState *machine,
pci_dev = pci_new_multifunction(-1, TYPE_PIIX3_DEVICE);
object_property_set_bool(OBJECT(pci_dev), "has-usb",
machine_usb(machine), &error_abort);
+ object_property_set_bool(OBJECT(pci_dev), "has-acpi",
+ x86_machine_is_acpi_enabled(x86ms),
+ &error_abort);
+ qdev_prop_set_uint32(DEVICE(pci_dev), "smb_io_base", 0xb100);
+ object_property_set_bool(OBJECT(pci_dev), "smm-enabled",
+ x86_machine_is_smm_enabled(x86ms),
+ &error_abort);
dev = DEVICE(pci_dev);
for (i = 0; i < ISA_NUM_IRQS; i++) {
qdev_connect_gpio_out_named(dev, "isa-irqs", i, x86ms->gsi[i]);
@@ -286,10 +292,10 @@ static void pc_init1(MachineState *machine,
XEN_IOAPIC_NUM_PIRQS);
}
- piix3_devfn = pci_dev->devfn;
isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(pci_dev), "isa.0"));
rtc_state = ISA_DEVICE(object_resolve_path_component(OBJECT(pci_dev),
"rtc"));
+ piix4_pm = object_resolve_path_component(OBJECT(pci_dev), "pm");
dev = DEVICE(object_resolve_path_component(OBJECT(pci_dev), "ide"));
pci_ide_create_devs(PCI_DEVICE(dev));
idebus[0] = qdev_get_child_bus(dev, "ide.0");
@@ -360,17 +366,9 @@ static void pc_init1(MachineState *machine,
}
#endif
- if (pcmc->pci_enabled && x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) {
- PCIDevice *piix4_pm;
-
+ if (piix4_pm) {
smi_irq = qemu_allocate_irq(pc_acpi_smi_interrupt, first_cpu, 0);
- piix4_pm = pci_new(piix3_devfn + 3, TYPE_PIIX4_PM);
- qdev_prop_set_uint32(DEVICE(piix4_pm), "smb_io_base", 0xb100);
- qdev_prop_set_bit(DEVICE(piix4_pm), "smm-enabled",
- x86_machine_is_smm_enabled(x86ms));
- pci_realize_and_unref(piix4_pm, pci_bus, &error_fatal);
- qdev_connect_gpio_out(DEVICE(piix4_pm), 0, x86ms->gsi[9]);
qdev_connect_gpio_out_named(DEVICE(piix4_pm), "smi-irq", 0, smi_irq);
pcms->smbus = I2C_BUS(qdev_get_child_bus(DEVICE(piix4_pm), "i2c"));
/* TODO: Populate SPD eeprom data. */
@@ -382,7 +380,7 @@ static void pc_init1(MachineState *machine,
object_property_allow_set_link,
OBJ_PROP_LINK_STRONG);
object_property_set_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP,
- OBJECT(piix4_pm), &error_abort);
+ piix4_pm, &error_abort);
}
if (machine->nvdimms_state->is_enabled) {
diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c
index aebc0da23b..5b867df299 100644
--- a/hw/isa/piix3.c
+++ b/hw/isa/piix3.c
@@ -308,6 +308,18 @@ static void pci_piix3_realize(PCIDevice *dev, Error **errp)
return;
}
}
+
+ /* Power Management */
+ if (d->has_acpi) {
+ object_initialize_child(OBJECT(d), "pm", &d->pm, TYPE_PIIX4_PM);
+ qdev_prop_set_int32(DEVICE(&d->pm), "addr", dev->devfn + 3);
+ qdev_prop_set_uint32(DEVICE(&d->pm), "smb_io_base", d->smb_io_base);
+ qdev_prop_set_bit(DEVICE(&d->pm), "smm-enabled", d->smm_enabled);
+ if (!qdev_realize(DEVICE(&d->pm), BUS(pci_bus), errp)) {
+ return;
+ }
+ qdev_connect_gpio_out(DEVICE(&d->pm), 0, d->isa_irqs_in[9]);
+ }
}
static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *scope)
@@ -343,7 +355,10 @@ static void pci_piix3_init(Object *obj)
}
static Property pci_piix3_props[] = {
+ DEFINE_PROP_UINT32("smb_io_base", PIIX3State, smb_io_base, 0),
+ DEFINE_PROP_BOOL("has-acpi", PIIX3State, has_acpi, true),
DEFINE_PROP_BOOL("has-usb", PIIX3State, has_usb, true),
+ DEFINE_PROP_BOOL("smm-enabled", PIIX3State, smm_enabled, false),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig
index 1076df69ca..17ddb25afc 100644
--- a/hw/isa/Kconfig
+++ b/hw/isa/Kconfig
@@ -33,6 +33,7 @@ config PC87312
config PIIX3
bool
+ select ACPI_PIIX4
select I8257
select IDE_PIIX
select ISA_BUS
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 51/78] hw/isa/piix3: Drop the "3" from PIIX base class name
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (49 preceding siblings ...)
2023-10-19 18:23 ` [PULL v2 50/78] hw/isa/piix3: Create power management " Michael S. Tsirkin
@ 2023-10-19 18:23 ` Michael S. Tsirkin
2023-10-19 18:23 ` [PULL v2 52/78] hw/isa/piix4: Remove unused inbound ISA interrupt lines Michael S. Tsirkin
` (27 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:23 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Bernhard Beschow, Marcel Apfelbaum,
Hervé Poussineau, Philippe Mathieu-Daudé,
Aurelien Jarno
From: Bernhard Beschow <shentey@gmail.com>
TYPE_PIIX3_PCI_DEVICE was the former base class of the Xen and non-Xen variants
of the PIIX3 ISA device models. It will become the base class for the PIIX3 and
PIIX4 device models, so drop the "3" from the type names.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231007123843.127151-15-shentey@gmail.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
include/hw/southbridge/piix.h | 6 ++--
hw/isa/piix3.c | 56 +++++++++++++++++------------------
2 files changed, 30 insertions(+), 32 deletions(-)
diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
index c56ce49fd3..0b257e1582 100644
--- a/include/hw/southbridge/piix.h
+++ b/include/hw/southbridge/piix.h
@@ -71,11 +71,9 @@ struct PIIXState {
bool has_usb;
bool smm_enabled;
};
-typedef struct PIIXState PIIX3State;
-#define TYPE_PIIX3_PCI_DEVICE "pci-piix3"
-DECLARE_INSTANCE_CHECKER(PIIX3State, PIIX3_PCI_DEVICE,
- TYPE_PIIX3_PCI_DEVICE)
+#define TYPE_PIIX_PCI_DEVICE "pci-piix"
+OBJECT_DECLARE_SIMPLE_TYPE(PIIXState, PIIX_PCI_DEVICE)
#define TYPE_PIIX3_DEVICE "PIIX3"
#define TYPE_PIIX4_PCI_DEVICE "piix4-isa"
diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c
index 5b867df299..c7e59249b6 100644
--- a/hw/isa/piix3.c
+++ b/hw/isa/piix3.c
@@ -35,7 +35,7 @@
#include "migration/vmstate.h"
#include "hw/acpi/acpi_aml_interface.h"
-static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
+static void piix3_set_irq_pic(PIIXState *piix3, int pic_irq)
{
qemu_set_irq(piix3->isa_irqs_in[pic_irq],
!!(piix3->pic_levels &
@@ -43,7 +43,7 @@ static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
(pic_irq * PIIX_NUM_PIRQS))));
}
-static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level)
+static void piix3_set_irq_level_internal(PIIXState *piix3, int pirq, int level)
{
int pic_irq;
uint64_t mask;
@@ -58,7 +58,7 @@ static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level)
piix3->pic_levels |= mask * !!level;
}
-static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
+static void piix3_set_irq_level(PIIXState *piix3, int pirq, int level)
{
int pic_irq;
@@ -74,13 +74,13 @@ static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
static void piix3_set_irq(void *opaque, int pirq, int level)
{
- PIIX3State *piix3 = opaque;
+ PIIXState *piix3 = opaque;
piix3_set_irq_level(piix3, pirq, level);
}
static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
{
- PIIX3State *piix3 = opaque;
+ PIIXState *piix3 = opaque;
int irq = piix3->dev.config[PIIX_PIRQCA + pin];
PCIINTxRoute route;
@@ -95,7 +95,7 @@ static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
}
/* irq routing is changed. so rebuild bitmap */
-static void piix3_update_irq_levels(PIIX3State *piix3)
+static void piix3_update_irq_levels(PIIXState *piix3)
{
PCIBus *bus = pci_get_bus(&piix3->dev);
int pirq;
@@ -111,7 +111,7 @@ static void piix3_write_config(PCIDevice *dev,
{
pci_default_write_config(dev, address, val, len);
if (ranges_overlap(address, len, PIIX_PIRQCA, 4)) {
- PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev);
+ PIIXState *piix3 = PIIX_PCI_DEVICE(dev);
int pic_irq;
pci_bus_fire_intx_routing_notifier(pci_get_bus(&piix3->dev));
@@ -124,7 +124,7 @@ static void piix3_write_config(PCIDevice *dev,
static void piix3_reset(DeviceState *dev)
{
- PIIX3State *d = PIIX3_PCI_DEVICE(dev);
+ PIIXState *d = PIIX_PCI_DEVICE(dev);
uint8_t *pci_conf = d->dev.config;
pci_conf[0x04] = 0x07; /* master, memory and I/O */
@@ -165,7 +165,7 @@ static void piix3_reset(DeviceState *dev)
static int piix3_post_load(void *opaque, int version_id)
{
- PIIX3State *piix3 = opaque;
+ PIIXState *piix3 = opaque;
int pirq;
/*
@@ -188,7 +188,7 @@ static int piix3_post_load(void *opaque, int version_id)
static int piix3_pre_save(void *opaque)
{
int i;
- PIIX3State *piix3 = opaque;
+ PIIXState *piix3 = opaque;
for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) {
piix3->pci_irq_levels_vmstate[i] =
@@ -200,7 +200,7 @@ static int piix3_pre_save(void *opaque)
static bool piix3_rcr_needed(void *opaque)
{
- PIIX3State *piix3 = opaque;
+ PIIXState *piix3 = opaque;
return (piix3->rcr != 0);
}
@@ -211,7 +211,7 @@ static const VMStateDescription vmstate_piix3_rcr = {
.minimum_version_id = 1,
.needed = piix3_rcr_needed,
.fields = (VMStateField[]) {
- VMSTATE_UINT8(rcr, PIIX3State),
+ VMSTATE_UINT8(rcr, PIIXState),
VMSTATE_END_OF_LIST()
}
};
@@ -223,8 +223,8 @@ static const VMStateDescription vmstate_piix3 = {
.post_load = piix3_post_load,
.pre_save = piix3_pre_save,
.fields = (VMStateField[]) {
- VMSTATE_PCI_DEVICE(dev, PIIX3State),
- VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State,
+ VMSTATE_PCI_DEVICE(dev, PIIXState),
+ VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIXState,
PIIX_NUM_PIRQS, 3),
VMSTATE_END_OF_LIST()
},
@@ -237,7 +237,7 @@ static const VMStateDescription vmstate_piix3 = {
static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len)
{
- PIIX3State *d = opaque;
+ PIIXState *d = opaque;
if (val & 4) {
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
@@ -248,7 +248,7 @@ static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len)
static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len)
{
- PIIX3State *d = opaque;
+ PIIXState *d = opaque;
return d->rcr;
}
@@ -265,7 +265,7 @@ static const MemoryRegionOps rcr_ops = {
static void pci_piix3_realize(PCIDevice *dev, Error **errp)
{
- PIIX3State *d = PIIX3_PCI_DEVICE(dev);
+ PIIXState *d = PIIX_PCI_DEVICE(dev);
PCIBus *pci_bus = pci_get_bus(dev);
ISABus *isa_bus;
uint32_t irq;
@@ -345,7 +345,7 @@ static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *scope)
static void pci_piix3_init(Object *obj)
{
- PIIX3State *d = PIIX3_PCI_DEVICE(obj);
+ PIIXState *d = PIIX_PCI_DEVICE(obj);
qdev_init_gpio_out_named(DEVICE(obj), d->isa_irqs_in, "isa-irqs",
ISA_NUM_IRQS);
@@ -355,10 +355,10 @@ static void pci_piix3_init(Object *obj)
}
static Property pci_piix3_props[] = {
- DEFINE_PROP_UINT32("smb_io_base", PIIX3State, smb_io_base, 0),
- DEFINE_PROP_BOOL("has-acpi", PIIX3State, has_acpi, true),
- DEFINE_PROP_BOOL("has-usb", PIIX3State, has_usb, true),
- DEFINE_PROP_BOOL("smm-enabled", PIIX3State, smm_enabled, false),
+ DEFINE_PROP_UINT32("smb_io_base", PIIXState, smb_io_base, 0),
+ DEFINE_PROP_BOOL("has-acpi", PIIXState, has_acpi, true),
+ DEFINE_PROP_BOOL("has-usb", PIIXState, has_usb, true),
+ DEFINE_PROP_BOOL("smm-enabled", PIIXState, smm_enabled, false),
DEFINE_PROP_END_OF_LIST(),
};
@@ -386,10 +386,10 @@ static void pci_piix3_class_init(ObjectClass *klass, void *data)
adevc->build_dev_aml = build_pci_isa_aml;
}
-static const TypeInfo piix3_pci_type_info = {
- .name = TYPE_PIIX3_PCI_DEVICE,
+static const TypeInfo piix_pci_type_info = {
+ .name = TYPE_PIIX_PCI_DEVICE,
.parent = TYPE_PCI_DEVICE,
- .instance_size = sizeof(PIIX3State),
+ .instance_size = sizeof(PIIXState),
.instance_init = pci_piix3_init,
.abstract = true,
.class_init = pci_piix3_class_init,
@@ -403,7 +403,7 @@ static const TypeInfo piix3_pci_type_info = {
static void piix3_realize(PCIDevice *dev, Error **errp)
{
ERRP_GUARD();
- PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev);
+ PIIXState *piix3 = PIIX_PCI_DEVICE(dev);
PCIBus *pci_bus = pci_get_bus(dev);
pci_piix3_realize(dev, errp);
@@ -424,13 +424,13 @@ static void piix3_class_init(ObjectClass *klass, void *data)
static const TypeInfo piix3_info = {
.name = TYPE_PIIX3_DEVICE,
- .parent = TYPE_PIIX3_PCI_DEVICE,
+ .parent = TYPE_PIIX_PCI_DEVICE,
.class_init = piix3_class_init,
};
static void piix3_register_types(void)
{
- type_register_static(&piix3_pci_type_info);
+ type_register_static(&piix_pci_type_info);
type_register_static(&piix3_info);
}
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 52/78] hw/isa/piix4: Remove unused inbound ISA interrupt lines
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (50 preceding siblings ...)
2023-10-19 18:23 ` [PULL v2 51/78] hw/isa/piix3: Drop the "3" from PIIX base class name Michael S. Tsirkin
@ 2023-10-19 18:23 ` Michael S. Tsirkin
2023-10-19 18:23 ` [PULL v2 53/78] hw/isa/piix4: Rename "isa" attribute to "isa_irqs_in" Michael S. Tsirkin
` (26 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:23 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Bernhard Beschow, Philippe Mathieu-Daudé,
Richard Henderson
From: Bernhard Beschow <shentey@gmail.com>
The Malta board, which is the only user of PIIX4, doesn't connect to the
exported interrupt lines. PIIX3 doesn't expose such interrupt lines
either, so remove them for PIIX4 for simplicity and consistency.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231007123843.127151-16-shentey@gmail.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/isa/piix4.c | 8 --------
1 file changed, 8 deletions(-)
diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index e0b149f8eb..3c3c7a094c 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@ -148,12 +148,6 @@ static void piix4_request_i8259_irq(void *opaque, int irq, int level)
qemu_set_irq(s->cpu_intr, level);
}
-static void piix4_set_i8259_irq(void *opaque, int irq, int level)
-{
- PIIX4State *s = opaque;
- qemu_set_irq(s->isa[irq], level);
-}
-
static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val,
unsigned int len)
{
@@ -197,8 +191,6 @@ static void piix4_realize(PCIDevice *dev, Error **errp)
return;
}
- qdev_init_gpio_in_named(DEVICE(dev), piix4_set_i8259_irq,
- "isa", ISA_NUM_IRQS);
qdev_init_gpio_out_named(DEVICE(dev), &s->cpu_intr,
"intr", 1);
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 53/78] hw/isa/piix4: Rename "isa" attribute to "isa_irqs_in"
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (51 preceding siblings ...)
2023-10-19 18:23 ` [PULL v2 52/78] hw/isa/piix4: Remove unused inbound ISA interrupt lines Michael S. Tsirkin
@ 2023-10-19 18:23 ` Michael S. Tsirkin
2023-10-19 18:23 ` [PULL v2 54/78] hw/isa/piix4: Rename reset control operations to match PIIX3 Michael S. Tsirkin
` (25 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:23 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Bernhard Beschow, Philippe Mathieu-Daudé,
Richard Henderson
From: Bernhard Beschow <shentey@gmail.com>
Rename the "isa" attribute to align it with PIIX3 for consolidation.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20231007123843.127151-17-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/isa/piix4.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index 3c3c7a094c..9c8b6c98ab 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@ -45,7 +45,7 @@
struct PIIX4State {
PCIDevice dev;
qemu_irq cpu_intr;
- qemu_irq *isa;
+ qemu_irq *isa_irqs_in;
MC146818RtcState rtc;
PCIIDEState ide;
@@ -75,7 +75,7 @@ static void piix4_set_irq(void *opaque, int irq_num, int level)
pic_level |= pci_bus_get_irq_level(bus, i);
}
}
- qemu_set_irq(s->isa[pic_irq], pic_level);
+ qemu_set_irq(s->isa_irqs_in[pic_irq], pic_level);
}
}
@@ -201,10 +201,10 @@ static void piix4_realize(PCIDevice *dev, Error **errp)
/* initialize i8259 pic */
i8259_out_irq = qemu_allocate_irqs(piix4_request_i8259_irq, s, 1);
- s->isa = i8259_init(isa_bus, *i8259_out_irq);
+ s->isa_irqs_in = i8259_init(isa_bus, *i8259_out_irq);
/* initialize ISA irqs */
- isa_bus_register_input_irqs(isa_bus, s->isa);
+ isa_bus_register_input_irqs(isa_bus, s->isa_irqs_in);
/* initialize pit */
i8254_pit_init(isa_bus, 0x40, 0, NULL);
@@ -236,7 +236,7 @@ static void piix4_realize(PCIDevice *dev, Error **errp)
if (!qdev_realize(DEVICE(&s->pm), BUS(pci_bus), errp)) {
return;
}
- qdev_connect_gpio_out(DEVICE(&s->pm), 0, s->isa[9]);
+ qdev_connect_gpio_out(DEVICE(&s->pm), 0, s->isa_irqs_in[9]);
pci_bus_irqs(pci_bus, piix4_set_irq, s, PIIX_NUM_PIRQS);
}
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 54/78] hw/isa/piix4: Rename reset control operations to match PIIX3
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (52 preceding siblings ...)
2023-10-19 18:23 ` [PULL v2 53/78] hw/isa/piix4: Rename "isa" attribute to "isa_irqs_in" Michael S. Tsirkin
@ 2023-10-19 18:23 ` Michael S. Tsirkin
2023-10-19 18:23 ` [PULL v2 55/78] hw/isa/piix4: Reuse struct PIIXState from PIIX3 Michael S. Tsirkin
` (24 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:23 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Bernhard Beschow, Philippe Mathieu-Daudé,
Richard Henderson
From: Bernhard Beschow <shentey@gmail.com>
Both implementations are the same and will be shared upon merging.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231007123843.127151-18-shentey@gmail.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/isa/piix4.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index 9c8b6c98ab..eb456622c5 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@ -148,8 +148,8 @@ static void piix4_request_i8259_irq(void *opaque, int irq, int level)
qemu_set_irq(s->cpu_intr, level);
}
-static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val,
- unsigned int len)
+static void rcr_write(void *opaque, hwaddr addr, uint64_t val,
+ unsigned int len)
{
PIIX4State *s = opaque;
@@ -161,16 +161,16 @@ static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val,
s->rcr = val & 2; /* keep System Reset type only */
}
-static uint64_t piix4_rcr_read(void *opaque, hwaddr addr, unsigned int len)
+static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned int len)
{
PIIX4State *s = opaque;
return s->rcr;
}
-static const MemoryRegionOps piix4_rcr_ops = {
- .read = piix4_rcr_read,
- .write = piix4_rcr_write,
+static const MemoryRegionOps rcr_ops = {
+ .read = rcr_read,
+ .write = rcr_write,
.endianness = DEVICE_LITTLE_ENDIAN,
.impl = {
.min_access_size = 1,
@@ -194,7 +194,7 @@ static void piix4_realize(PCIDevice *dev, Error **errp)
qdev_init_gpio_out_named(DEVICE(dev), &s->cpu_intr,
"intr", 1);
- memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s,
+ memory_region_init_io(&s->rcr_mem, OBJECT(dev), &rcr_ops, s,
"reset-control", 1);
memory_region_add_subregion_overlap(pci_address_space_io(dev),
PIIX_RCR_IOPORT, &s->rcr_mem, 1);
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 55/78] hw/isa/piix4: Reuse struct PIIXState from PIIX3
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (53 preceding siblings ...)
2023-10-19 18:23 ` [PULL v2 54/78] hw/isa/piix4: Rename reset control operations to match PIIX3 Michael S. Tsirkin
@ 2023-10-19 18:23 ` Michael S. Tsirkin
2023-10-19 18:23 ` [PULL v2 56/78] hw/isa/piix3: Merge hw/isa/piix4.c Michael S. Tsirkin
` (23 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:23 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Bernhard Beschow, Marcel Apfelbaum,
Hervé Poussineau, Philippe Mathieu-Daudé,
Aurelien Jarno
From: Bernhard Beschow <shentey@gmail.com>
PIIX4 has its own, private PIIX4State structure. PIIX3 has almost the
same structure, provided in a public header. So reuse it and add a
cpu_intr attribute to it which is only used by PIIX4.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20231007123843.127151-19-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
include/hw/southbridge/piix.h | 1 +
hw/isa/piix4.c | 26 +++++++++++---------------
2 files changed, 12 insertions(+), 15 deletions(-)
diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
index 0b257e1582..dd5f7b31c0 100644
--- a/include/hw/southbridge/piix.h
+++ b/include/hw/southbridge/piix.h
@@ -49,6 +49,7 @@ struct PIIXState {
#endif
uint64_t pic_levels;
+ qemu_irq cpu_intr;
qemu_irq isa_irqs_in[ISA_NUM_IRQS];
/* This member isn't used. Just for save/load compatibility */
diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index eb456622c5..71899aaa69 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@ -42,21 +42,9 @@
#include "sysemu/runstate.h"
#include "qom/object.h"
-struct PIIX4State {
- PCIDevice dev;
- qemu_irq cpu_intr;
- qemu_irq *isa_irqs_in;
+typedef struct PIIXState PIIX4State;
- MC146818RtcState rtc;
- PCIIDEState ide;
- UHCIState uhci;
- PIIX4PMState pm;
- /* Reset Control Register */
- MemoryRegion rcr_mem;
- uint8_t rcr;
-};
-
-OBJECT_DECLARE_SIMPLE_TYPE(PIIX4State, PIIX4_PCI_DEVICE)
+DECLARE_INSTANCE_CHECKER(PIIX4State, PIIX4_PCI_DEVICE, TYPE_PIIX4_PCI_DEVICE)
static void piix4_set_irq(void *opaque, int irq_num, int level)
{
@@ -184,6 +172,8 @@ static void piix4_realize(PCIDevice *dev, Error **errp)
PCIBus *pci_bus = pci_get_bus(dev);
ISABus *isa_bus;
qemu_irq *i8259_out_irq;
+ qemu_irq *i8259;
+ size_t i;
isa_bus = isa_bus_new(DEVICE(dev), pci_address_space(dev),
pci_address_space_io(dev), errp);
@@ -201,7 +191,13 @@ static void piix4_realize(PCIDevice *dev, Error **errp)
/* initialize i8259 pic */
i8259_out_irq = qemu_allocate_irqs(piix4_request_i8259_irq, s, 1);
- s->isa_irqs_in = i8259_init(isa_bus, *i8259_out_irq);
+ i8259 = i8259_init(isa_bus, *i8259_out_irq);
+
+ for (i = 0; i < ISA_NUM_IRQS; i++) {
+ s->isa_irqs_in[i] = i8259[i];
+ }
+
+ g_free(i8259);
/* initialize ISA irqs */
isa_bus_register_input_irqs(isa_bus, s->isa_irqs_in);
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 56/78] hw/isa/piix3: Merge hw/isa/piix4.c
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (54 preceding siblings ...)
2023-10-19 18:23 ` [PULL v2 55/78] hw/isa/piix4: Reuse struct PIIXState from PIIX3 Michael S. Tsirkin
@ 2023-10-19 18:23 ` Michael S. Tsirkin
2023-10-19 18:23 ` [PULL v2 57/78] hw/isa/piix: Allow for optional PIC creation in PIIX3 Michael S. Tsirkin
` (22 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:23 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Bernhard Beschow, Paolo Bonzini, Richard Henderson,
Eduardo Habkost, Marcel Apfelbaum, Philippe Mathieu-Daudé,
Aurelien Jarno, Hervé Poussineau
From: Bernhard Beschow <shentey@gmail.com>
Now that the PIIX3 and PIIX4 device models are sufficiently prepared, their
implementations can be merged into one file for further consolidation.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231007123843.127151-20-shentey@gmail.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/isa/{piix3.c => piix.c} | 190 +++++++++++++++++++++++-
hw/isa/piix4.c | 290 -------------------------------------
MAINTAINERS | 6 +-
hw/i386/Kconfig | 2 +-
hw/isa/Kconfig | 11 +-
hw/isa/meson.build | 3 +-
hw/mips/Kconfig | 2 +-
7 files changed, 195 insertions(+), 309 deletions(-)
rename hw/isa/{piix3.c => piix.c} (71%)
delete mode 100644 hw/isa/piix4.c
diff --git a/hw/isa/piix3.c b/hw/isa/piix.c
similarity index 71%
rename from hw/isa/piix3.c
rename to hw/isa/piix.c
index c7e59249b6..f6da334c6f 100644
--- a/hw/isa/piix3.c
+++ b/hw/isa/piix.c
@@ -2,6 +2,7 @@
* QEMU PIIX PCI ISA Bridge Emulation
*
* Copyright (c) 2006 Fabrice Bellard
+ * Copyright (c) 2018 Hervé Poussineau
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -27,14 +28,20 @@
#include "qapi/error.h"
#include "hw/dma/i8257.h"
#include "hw/southbridge/piix.h"
+#include "hw/timer/i8254.h"
#include "hw/irq.h"
#include "hw/qdev-properties.h"
#include "hw/ide/piix.h"
+#include "hw/intc/i8259.h"
#include "hw/isa/isa.h"
#include "sysemu/runstate.h"
#include "migration/vmstate.h"
#include "hw/acpi/acpi_aml_interface.h"
+typedef struct PIIXState PIIX4State;
+
+DECLARE_INSTANCE_CHECKER(PIIX4State, PIIX4_PCI_DEVICE, TYPE_PIIX4_PCI_DEVICE)
+
static void piix3_set_irq_pic(PIIXState *piix3, int pic_irq)
{
qemu_set_irq(piix3->isa_irqs_in[pic_irq],
@@ -78,6 +85,33 @@ static void piix3_set_irq(void *opaque, int pirq, int level)
piix3_set_irq_level(piix3, pirq, level);
}
+static void piix4_set_irq(void *opaque, int irq_num, int level)
+{
+ int i, pic_irq, pic_level;
+ PIIX4State *s = opaque;
+ PCIBus *bus = pci_get_bus(&s->dev);
+
+ /* now we change the pic irq level according to the piix irq mappings */
+ /* XXX: optimize */
+ pic_irq = s->dev.config[PIIX_PIRQCA + irq_num];
+ if (pic_irq < ISA_NUM_IRQS) {
+ /* The pic level is the logical OR of all the PCI irqs mapped to it. */
+ pic_level = 0;
+ for (i = 0; i < PIIX_NUM_PIRQS; i++) {
+ if (pic_irq == s->dev.config[PIIX_PIRQCA + i]) {
+ pic_level |= pci_bus_get_irq_level(bus, i);
+ }
+ }
+ qemu_set_irq(s->isa_irqs_in[pic_irq], pic_level);
+ }
+}
+
+static void piix4_request_i8259_irq(void *opaque, int irq, int level)
+{
+ PIIX4State *s = opaque;
+ qemu_set_irq(s->cpu_intr, level);
+}
+
static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
{
PIIXState *piix3 = opaque;
@@ -122,9 +156,8 @@ static void piix3_write_config(PCIDevice *dev,
}
}
-static void piix3_reset(DeviceState *dev)
+static void piix_reset(PIIXState *d)
{
- PIIXState *d = PIIX_PCI_DEVICE(dev);
uint8_t *pci_conf = d->dev.config;
pci_conf[0x04] = 0x07; /* master, memory and I/O */
@@ -163,6 +196,13 @@ static void piix3_reset(DeviceState *dev)
d->rcr = 0;
}
+static void piix3_reset(DeviceState *dev)
+{
+ PIIXState *d = PIIX_PCI_DEVICE(dev);
+
+ piix_reset(d);
+}
+
static int piix3_post_load(void *opaque, int version_id)
{
PIIXState *piix3 = opaque;
@@ -185,6 +225,17 @@ static int piix3_post_load(void *opaque, int version_id)
return 0;
}
+static int piix4_post_load(void *opaque, int version_id)
+{
+ PIIX4State *s = opaque;
+
+ if (version_id == 2) {
+ s->rcr = 0;
+ }
+
+ return 0;
+}
+
static int piix3_pre_save(void *opaque)
{
int i;
@@ -234,6 +285,17 @@ static const VMStateDescription vmstate_piix3 = {
}
};
+static const VMStateDescription vmstate_piix4 = {
+ .name = "PIIX4",
+ .version_id = 3,
+ .minimum_version_id = 2,
+ .post_load = piix4_post_load,
+ .fields = (VMStateField[]) {
+ VMSTATE_PCI_DEVICE(dev, PIIX4State),
+ VMSTATE_UINT8_V(rcr, PIIX4State, 3),
+ VMSTATE_END_OF_LIST()
+ }
+};
static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len)
{
@@ -428,10 +490,134 @@ static const TypeInfo piix3_info = {
.class_init = piix3_class_init,
};
+static void piix4_realize(PCIDevice *dev, Error **errp)
+{
+ PIIX4State *s = PIIX4_PCI_DEVICE(dev);
+ PCIBus *pci_bus = pci_get_bus(dev);
+ ISABus *isa_bus;
+ qemu_irq *i8259_out_irq;
+ qemu_irq *i8259;
+ size_t i;
+
+ isa_bus = isa_bus_new(DEVICE(dev), pci_address_space(dev),
+ pci_address_space_io(dev), errp);
+ if (!isa_bus) {
+ return;
+ }
+
+ qdev_init_gpio_out_named(DEVICE(dev), &s->cpu_intr,
+ "intr", 1);
+
+ memory_region_init_io(&s->rcr_mem, OBJECT(dev), &rcr_ops, s,
+ "reset-control", 1);
+ memory_region_add_subregion_overlap(pci_address_space_io(dev),
+ PIIX_RCR_IOPORT, &s->rcr_mem, 1);
+
+ /* initialize i8259 pic */
+ i8259_out_irq = qemu_allocate_irqs(piix4_request_i8259_irq, s, 1);
+ i8259 = i8259_init(isa_bus, *i8259_out_irq);
+
+ for (i = 0; i < ISA_NUM_IRQS; i++) {
+ s->isa_irqs_in[i] = i8259[i];
+ }
+
+ g_free(i8259);
+
+ /* initialize ISA irqs */
+ isa_bus_register_input_irqs(isa_bus, s->isa_irqs_in);
+
+ /* initialize pit */
+ i8254_pit_init(isa_bus, 0x40, 0, NULL);
+
+ /* DMA */
+ i8257_dma_init(isa_bus, 0);
+
+ /* RTC */
+ qdev_prop_set_int32(DEVICE(&s->rtc), "base_year", 2000);
+ if (!qdev_realize(DEVICE(&s->rtc), BUS(isa_bus), errp)) {
+ return;
+ }
+ s->rtc.irq = isa_get_irq(ISA_DEVICE(&s->rtc), s->rtc.isairq);
+
+ /* IDE */
+ qdev_prop_set_int32(DEVICE(&s->ide), "addr", dev->devfn + 1);
+ if (!qdev_realize(DEVICE(&s->ide), BUS(pci_bus), errp)) {
+ return;
+ }
+
+ /* USB */
+ qdev_prop_set_int32(DEVICE(&s->uhci), "addr", dev->devfn + 2);
+ if (!qdev_realize(DEVICE(&s->uhci), BUS(pci_bus), errp)) {
+ return;
+ }
+
+ /* ACPI controller */
+ qdev_prop_set_int32(DEVICE(&s->pm), "addr", dev->devfn + 3);
+ if (!qdev_realize(DEVICE(&s->pm), BUS(pci_bus), errp)) {
+ return;
+ }
+ qdev_connect_gpio_out(DEVICE(&s->pm), 0, s->isa_irqs_in[9]);
+
+ pci_bus_irqs(pci_bus, piix4_set_irq, s, PIIX_NUM_PIRQS);
+}
+
+static void piix4_isa_reset(DeviceState *dev)
+{
+ PIIX4State *s = PIIX4_PCI_DEVICE(dev);
+
+ piix_reset(s);
+}
+
+static void piix4_init(Object *obj)
+{
+ PIIX4State *s = PIIX4_PCI_DEVICE(obj);
+
+ object_initialize_child(obj, "rtc", &s->rtc, TYPE_MC146818_RTC);
+ object_initialize_child(obj, "ide", &s->ide, TYPE_PIIX4_IDE);
+ object_initialize_child(obj, "uhci", &s->uhci, TYPE_PIIX4_USB_UHCI);
+
+ object_initialize_child(obj, "pm", &s->pm, TYPE_PIIX4_PM);
+ qdev_prop_set_uint32(DEVICE(&s->pm), "smb_io_base", 0x1100);
+ qdev_prop_set_bit(DEVICE(&s->pm), "smm-enabled", 0);
+}
+
+static void piix4_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
+
+ k->realize = piix4_realize;
+ k->vendor_id = PCI_VENDOR_ID_INTEL;
+ k->device_id = PCI_DEVICE_ID_INTEL_82371AB_0;
+ k->class_id = PCI_CLASS_BRIDGE_ISA;
+ dc->reset = piix4_isa_reset;
+ dc->desc = "ISA bridge";
+ dc->vmsd = &vmstate_piix4;
+ /*
+ * Reason: part of PIIX4 southbridge, needs to be wired up,
+ * e.g. by mips_malta_init()
+ */
+ dc->user_creatable = false;
+ dc->hotpluggable = false;
+}
+
+static const TypeInfo piix4_info = {
+ .name = TYPE_PIIX4_PCI_DEVICE,
+ .parent = TYPE_PCI_DEVICE,
+ .instance_size = sizeof(PIIX4State),
+ .instance_init = piix4_init,
+ .class_init = piix4_class_init,
+ .interfaces = (InterfaceInfo[]) {
+ { INTERFACE_CONVENTIONAL_PCI_DEVICE },
+ { },
+ },
+};
+
static void piix3_register_types(void)
{
type_register_static(&piix_pci_type_info);
type_register_static(&piix3_info);
+ type_register_static(&piix4_info);
}
type_init(piix3_register_types)
diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
deleted file mode 100644
index 71899aaa69..0000000000
--- a/hw/isa/piix4.c
+++ /dev/null
@@ -1,290 +0,0 @@
-/*
- * QEMU PIIX4 PCI Bridge Emulation
- *
- * Copyright (c) 2006 Fabrice Bellard
- * Copyright (c) 2018 Hervé Poussineau
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#include "qemu/osdep.h"
-#include "qapi/error.h"
-#include "hw/irq.h"
-#include "hw/southbridge/piix.h"
-#include "hw/pci/pci.h"
-#include "hw/ide/piix.h"
-#include "hw/isa/isa.h"
-#include "hw/intc/i8259.h"
-#include "hw/dma/i8257.h"
-#include "hw/timer/i8254.h"
-#include "hw/rtc/mc146818rtc.h"
-#include "hw/ide/pci.h"
-#include "hw/acpi/piix4.h"
-#include "hw/usb/hcd-uhci.h"
-#include "migration/vmstate.h"
-#include "sysemu/reset.h"
-#include "sysemu/runstate.h"
-#include "qom/object.h"
-
-typedef struct PIIXState PIIX4State;
-
-DECLARE_INSTANCE_CHECKER(PIIX4State, PIIX4_PCI_DEVICE, TYPE_PIIX4_PCI_DEVICE)
-
-static void piix4_set_irq(void *opaque, int irq_num, int level)
-{
- int i, pic_irq, pic_level;
- PIIX4State *s = opaque;
- PCIBus *bus = pci_get_bus(&s->dev);
-
- /* now we change the pic irq level according to the piix irq mappings */
- /* XXX: optimize */
- pic_irq = s->dev.config[PIIX_PIRQCA + irq_num];
- if (pic_irq < ISA_NUM_IRQS) {
- /* The pic level is the logical OR of all the PCI irqs mapped to it. */
- pic_level = 0;
- for (i = 0; i < PIIX_NUM_PIRQS; i++) {
- if (pic_irq == s->dev.config[PIIX_PIRQCA + i]) {
- pic_level |= pci_bus_get_irq_level(bus, i);
- }
- }
- qemu_set_irq(s->isa_irqs_in[pic_irq], pic_level);
- }
-}
-
-static void piix4_isa_reset(DeviceState *dev)
-{
- PIIX4State *d = PIIX4_PCI_DEVICE(dev);
- uint8_t *pci_conf = d->dev.config;
-
- pci_conf[0x04] = 0x07; // master, memory and I/O
- pci_conf[0x05] = 0x00;
- pci_conf[0x06] = 0x00;
- pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
- pci_conf[0x4c] = 0x4d;
- pci_conf[0x4e] = 0x03;
- pci_conf[0x4f] = 0x00;
- pci_conf[0x60] = 0x80;
- pci_conf[0x61] = 0x80;
- pci_conf[0x62] = 0x80;
- pci_conf[0x63] = 0x80;
- pci_conf[0x69] = 0x02;
- pci_conf[0x70] = 0x80;
- pci_conf[0x76] = 0x0c;
- pci_conf[0x77] = 0x0c;
- pci_conf[0x78] = 0x02;
- pci_conf[0x79] = 0x00;
- pci_conf[0x80] = 0x00;
- pci_conf[0x82] = 0x00;
- pci_conf[0xa0] = 0x08;
- pci_conf[0xa2] = 0x00;
- pci_conf[0xa3] = 0x00;
- pci_conf[0xa4] = 0x00;
- pci_conf[0xa5] = 0x00;
- pci_conf[0xa6] = 0x00;
- pci_conf[0xa7] = 0x00;
- pci_conf[0xa8] = 0x0f;
- pci_conf[0xaa] = 0x00;
- pci_conf[0xab] = 0x00;
- pci_conf[0xac] = 0x00;
- pci_conf[0xae] = 0x00;
-
- d->rcr = 0;
-}
-
-static int piix4_post_load(void *opaque, int version_id)
-{
- PIIX4State *s = opaque;
-
- if (version_id == 2) {
- s->rcr = 0;
- }
-
- return 0;
-}
-
-static const VMStateDescription vmstate_piix4 = {
- .name = "PIIX4",
- .version_id = 3,
- .minimum_version_id = 2,
- .post_load = piix4_post_load,
- .fields = (VMStateField[]) {
- VMSTATE_PCI_DEVICE(dev, PIIX4State),
- VMSTATE_UINT8_V(rcr, PIIX4State, 3),
- VMSTATE_END_OF_LIST()
- }
-};
-
-static void piix4_request_i8259_irq(void *opaque, int irq, int level)
-{
- PIIX4State *s = opaque;
- qemu_set_irq(s->cpu_intr, level);
-}
-
-static void rcr_write(void *opaque, hwaddr addr, uint64_t val,
- unsigned int len)
-{
- PIIX4State *s = opaque;
-
- if (val & 4) {
- qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
- return;
- }
-
- s->rcr = val & 2; /* keep System Reset type only */
-}
-
-static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned int len)
-{
- PIIX4State *s = opaque;
-
- return s->rcr;
-}
-
-static const MemoryRegionOps rcr_ops = {
- .read = rcr_read,
- .write = rcr_write,
- .endianness = DEVICE_LITTLE_ENDIAN,
- .impl = {
- .min_access_size = 1,
- .max_access_size = 1,
- },
-};
-
-static void piix4_realize(PCIDevice *dev, Error **errp)
-{
- PIIX4State *s = PIIX4_PCI_DEVICE(dev);
- PCIBus *pci_bus = pci_get_bus(dev);
- ISABus *isa_bus;
- qemu_irq *i8259_out_irq;
- qemu_irq *i8259;
- size_t i;
-
- isa_bus = isa_bus_new(DEVICE(dev), pci_address_space(dev),
- pci_address_space_io(dev), errp);
- if (!isa_bus) {
- return;
- }
-
- qdev_init_gpio_out_named(DEVICE(dev), &s->cpu_intr,
- "intr", 1);
-
- memory_region_init_io(&s->rcr_mem, OBJECT(dev), &rcr_ops, s,
- "reset-control", 1);
- memory_region_add_subregion_overlap(pci_address_space_io(dev),
- PIIX_RCR_IOPORT, &s->rcr_mem, 1);
-
- /* initialize i8259 pic */
- i8259_out_irq = qemu_allocate_irqs(piix4_request_i8259_irq, s, 1);
- i8259 = i8259_init(isa_bus, *i8259_out_irq);
-
- for (i = 0; i < ISA_NUM_IRQS; i++) {
- s->isa_irqs_in[i] = i8259[i];
- }
-
- g_free(i8259);
-
- /* initialize ISA irqs */
- isa_bus_register_input_irqs(isa_bus, s->isa_irqs_in);
-
- /* initialize pit */
- i8254_pit_init(isa_bus, 0x40, 0, NULL);
-
- /* DMA */
- i8257_dma_init(isa_bus, 0);
-
- /* RTC */
- qdev_prop_set_int32(DEVICE(&s->rtc), "base_year", 2000);
- if (!qdev_realize(DEVICE(&s->rtc), BUS(isa_bus), errp)) {
- return;
- }
- s->rtc.irq = isa_get_irq(ISA_DEVICE(&s->rtc), s->rtc.isairq);
-
- /* IDE */
- qdev_prop_set_int32(DEVICE(&s->ide), "addr", dev->devfn + 1);
- if (!qdev_realize(DEVICE(&s->ide), BUS(pci_bus), errp)) {
- return;
- }
-
- /* USB */
- qdev_prop_set_int32(DEVICE(&s->uhci), "addr", dev->devfn + 2);
- if (!qdev_realize(DEVICE(&s->uhci), BUS(pci_bus), errp)) {
- return;
- }
-
- /* ACPI controller */
- qdev_prop_set_int32(DEVICE(&s->pm), "addr", dev->devfn + 3);
- if (!qdev_realize(DEVICE(&s->pm), BUS(pci_bus), errp)) {
- return;
- }
- qdev_connect_gpio_out(DEVICE(&s->pm), 0, s->isa_irqs_in[9]);
-
- pci_bus_irqs(pci_bus, piix4_set_irq, s, PIIX_NUM_PIRQS);
-}
-
-static void piix4_init(Object *obj)
-{
- PIIX4State *s = PIIX4_PCI_DEVICE(obj);
-
- object_initialize_child(obj, "rtc", &s->rtc, TYPE_MC146818_RTC);
- object_initialize_child(obj, "ide", &s->ide, TYPE_PIIX4_IDE);
- object_initialize_child(obj, "uhci", &s->uhci, TYPE_PIIX4_USB_UHCI);
-
- object_initialize_child(obj, "pm", &s->pm, TYPE_PIIX4_PM);
- qdev_prop_set_uint32(DEVICE(&s->pm), "smb_io_base", 0x1100);
- qdev_prop_set_bit(DEVICE(&s->pm), "smm-enabled", 0);
-}
-
-static void piix4_class_init(ObjectClass *klass, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(klass);
- PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
-
- k->realize = piix4_realize;
- k->vendor_id = PCI_VENDOR_ID_INTEL;
- k->device_id = PCI_DEVICE_ID_INTEL_82371AB_0;
- k->class_id = PCI_CLASS_BRIDGE_ISA;
- dc->reset = piix4_isa_reset;
- dc->desc = "ISA bridge";
- dc->vmsd = &vmstate_piix4;
- /*
- * Reason: part of PIIX4 southbridge, needs to be wired up,
- * e.g. by mips_malta_init()
- */
- dc->user_creatable = false;
- dc->hotpluggable = false;
-}
-
-static const TypeInfo piix4_info = {
- .name = TYPE_PIIX4_PCI_DEVICE,
- .parent = TYPE_PCI_DEVICE,
- .instance_size = sizeof(PIIX4State),
- .instance_init = piix4_init,
- .class_init = piix4_class_init,
- .interfaces = (InterfaceInfo[]) {
- { INTERFACE_CONVENTIONAL_PCI_DEVICE },
- { },
- },
-};
-
-static void piix4_register_types(void)
-{
- type_register_static(&piix4_info);
-}
-
-type_init(piix4_register_types)
diff --git a/MAINTAINERS b/MAINTAINERS
index 9bd4fe378d..d9fe5aa367 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1302,7 +1302,7 @@ Malta
M: Philippe Mathieu-Daudé <philmd@linaro.org>
R: Aurelien Jarno <aurelien@aurel32.net>
S: Odd Fixes
-F: hw/isa/piix4.c
+F: hw/isa/piix.c
F: hw/acpi/piix4.c
F: hw/mips/malta.c
F: hw/pci-host/gt64120.c
@@ -1724,7 +1724,7 @@ F: hw/pci-host/pam.c
F: include/hw/pci-host/i440fx.h
F: include/hw/pci-host/q35.h
F: include/hw/pci-host/pam.h
-F: hw/isa/piix3.c
+F: hw/isa/piix.c
F: hw/isa/lpc_ich9.c
F: hw/i2c/smbus_ich9.c
F: hw/acpi/piix4.c
@@ -2478,7 +2478,7 @@ PIIX4 South Bridge (i82371AB)
M: Hervé Poussineau <hpoussin@reactos.org>
M: Philippe Mathieu-Daudé <philmd@linaro.org>
S: Maintained
-F: hw/isa/piix4.c
+F: hw/isa/piix.c
F: include/hw/southbridge/piix.h
Firmware configuration (fw_cfg)
diff --git a/hw/i386/Kconfig b/hw/i386/Kconfig
index ade817f1b6..94772c726b 100644
--- a/hw/i386/Kconfig
+++ b/hw/i386/Kconfig
@@ -72,7 +72,7 @@ config I440FX
select PC_PCI
select PC_ACPI
select PCI_I440FX
- select PIIX3
+ select PIIX
select DIMM
select SMBIOS
select FW_CFG_DMA
diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig
index 17ddb25afc..040a18c070 100644
--- a/hw/isa/Kconfig
+++ b/hw/isa/Kconfig
@@ -31,16 +31,7 @@ config PC87312
select FDC_ISA
select IDE_ISA
-config PIIX3
- bool
- select ACPI_PIIX4
- select I8257
- select IDE_PIIX
- select ISA_BUS
- select MC146818RTC
- select USB_UHCI
-
-config PIIX4
+config PIIX
bool
# For historical reasons, SuperIO devices are created in the board
# for PIIX4.
diff --git a/hw/isa/meson.build b/hw/isa/meson.build
index b855e81276..2ab99ce0c6 100644
--- a/hw/isa/meson.build
+++ b/hw/isa/meson.build
@@ -3,8 +3,7 @@ system_ss.add(when: 'CONFIG_I82378', if_true: files('i82378.c'))
system_ss.add(when: 'CONFIG_ISA_BUS', if_true: files('isa-bus.c'))
system_ss.add(when: 'CONFIG_ISA_SUPERIO', if_true: files('isa-superio.c'))
system_ss.add(when: 'CONFIG_PC87312', if_true: files('pc87312.c'))
-system_ss.add(when: 'CONFIG_PIIX3', if_true: files('piix3.c'))
-system_ss.add(when: 'CONFIG_PIIX4', if_true: files('piix4.c'))
+system_ss.add(when: 'CONFIG_PIIX', if_true: files('piix.c'))
system_ss.add(when: 'CONFIG_SMC37C669', if_true: files('smc37c669-superio.c'))
system_ss.add(when: 'CONFIG_VT82C686', if_true: files('vt82c686.c'))
diff --git a/hw/mips/Kconfig b/hw/mips/Kconfig
index da3a37e215..ac1eb06a51 100644
--- a/hw/mips/Kconfig
+++ b/hw/mips/Kconfig
@@ -2,7 +2,7 @@ config MALTA
bool
select GT64120
select ISA_SUPERIO
- select PIIX4
+ select PIIX
config MIPSSIM
bool
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 57/78] hw/isa/piix: Allow for optional PIC creation in PIIX3
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (55 preceding siblings ...)
2023-10-19 18:23 ` [PULL v2 56/78] hw/isa/piix3: Merge hw/isa/piix4.c Michael S. Tsirkin
@ 2023-10-19 18:23 ` Michael S. Tsirkin
2023-10-19 18:23 ` [PULL v2 58/78] hw/isa/piix: Allow for optional PIT " Michael S. Tsirkin
` (21 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:23 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Bernhard Beschow, Marcel Apfelbaum, Paolo Bonzini,
Richard Henderson, Eduardo Habkost, Hervé Poussineau,
Philippe Mathieu-Daudé, Aurelien Jarno
From: Bernhard Beschow <shentey@gmail.com>
In the PC machine, the PIC is created in board code to allow it to be
virtualized with various virtualization techniques. So explicitly disable its
creation in the PC machine via a property which defaults to enabled. Once the
PIIX implementations are consolidated this default will keep Malta working
without further ado.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20231007123843.127151-21-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
include/hw/southbridge/piix.h | 1 +
hw/i386/pc_piix.c | 2 ++
hw/isa/piix.c | 21 +++++++++++++++++++--
3 files changed, 22 insertions(+), 2 deletions(-)
diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
index dd5f7b31c0..08491693b4 100644
--- a/include/hw/southbridge/piix.h
+++ b/include/hw/southbridge/piix.h
@@ -69,6 +69,7 @@ struct PIIXState {
MemoryRegion rcr_mem;
bool has_acpi;
+ bool has_pic;
bool has_usb;
bool smm_enabled;
};
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 70cffcfe4f..fa39afd891 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -268,6 +268,8 @@ static void pc_init1(MachineState *machine,
object_property_set_bool(OBJECT(pci_dev), "has-acpi",
x86_machine_is_acpi_enabled(x86ms),
&error_abort);
+ object_property_set_bool(OBJECT(pci_dev), "has-pic", false,
+ &error_abort);
qdev_prop_set_uint32(DEVICE(pci_dev), "smb_io_base", 0xb100);
object_property_set_bool(OBJECT(pci_dev), "smm-enabled",
x86_machine_is_smm_enabled(x86ms),
diff --git a/hw/isa/piix.c b/hw/isa/piix.c
index f6da334c6f..d6d9ac6473 100644
--- a/hw/isa/piix.c
+++ b/hw/isa/piix.c
@@ -106,7 +106,7 @@ static void piix4_set_irq(void *opaque, int irq_num, int level)
}
}
-static void piix4_request_i8259_irq(void *opaque, int irq, int level)
+static void piix_request_i8259_irq(void *opaque, int irq, int level)
{
PIIX4State *s = opaque;
qemu_set_irq(s->cpu_intr, level);
@@ -343,6 +343,22 @@ static void pci_piix3_realize(PCIDevice *dev, Error **errp)
memory_region_add_subregion_overlap(pci_address_space_io(dev),
PIIX_RCR_IOPORT, &d->rcr_mem, 1);
+ /* PIC */
+ if (d->has_pic) {
+ qemu_irq *i8259_out_irq = qemu_allocate_irqs(piix_request_i8259_irq, d,
+ 1);
+ qemu_irq *i8259 = i8259_init(isa_bus, *i8259_out_irq);
+ size_t i;
+
+ for (i = 0; i < ISA_NUM_IRQS; i++) {
+ d->isa_irqs_in[i] = i8259[i];
+ }
+
+ g_free(i8259);
+
+ qdev_init_gpio_out_named(DEVICE(dev), &d->cpu_intr, "intr", 1);
+ }
+
isa_bus_register_input_irqs(isa_bus, d->isa_irqs_in);
i8257_dma_init(isa_bus, 0);
@@ -419,6 +435,7 @@ static void pci_piix3_init(Object *obj)
static Property pci_piix3_props[] = {
DEFINE_PROP_UINT32("smb_io_base", PIIXState, smb_io_base, 0),
DEFINE_PROP_BOOL("has-acpi", PIIXState, has_acpi, true),
+ DEFINE_PROP_BOOL("has-pic", PIIXState, has_pic, true),
DEFINE_PROP_BOOL("has-usb", PIIXState, has_usb, true),
DEFINE_PROP_BOOL("smm-enabled", PIIXState, smm_enabled, false),
DEFINE_PROP_END_OF_LIST(),
@@ -514,7 +531,7 @@ static void piix4_realize(PCIDevice *dev, Error **errp)
PIIX_RCR_IOPORT, &s->rcr_mem, 1);
/* initialize i8259 pic */
- i8259_out_irq = qemu_allocate_irqs(piix4_request_i8259_irq, s, 1);
+ i8259_out_irq = qemu_allocate_irqs(piix_request_i8259_irq, s, 1);
i8259 = i8259_init(isa_bus, *i8259_out_irq);
for (i = 0; i < ISA_NUM_IRQS; i++) {
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 58/78] hw/isa/piix: Allow for optional PIT creation in PIIX3
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (56 preceding siblings ...)
2023-10-19 18:23 ` [PULL v2 57/78] hw/isa/piix: Allow for optional PIC creation in PIIX3 Michael S. Tsirkin
@ 2023-10-19 18:23 ` Michael S. Tsirkin
2023-10-19 18:23 ` [PULL v2 59/78] hw/isa/piix: Harmonize names of reset control memory regions Michael S. Tsirkin
` (20 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:23 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Bernhard Beschow, Paolo Bonzini, Richard Henderson,
Eduardo Habkost, Marcel Apfelbaum, Hervé Poussineau,
Philippe Mathieu-Daudé, Aurelien Jarno
From: Bernhard Beschow <shentey@gmail.com>
In the PC machine, the PIT is created in board code to allow it to be
virtualized with various virtualization techniques. So explicitly disable its
creation in the PC machine via a property which defaults to enabled. Once the
PIIX implementations are consolidated this default will keep Malta working
without further ado.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20231007123843.127151-22-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
include/hw/southbridge/piix.h | 1 +
hw/i386/pc_piix.c | 2 ++
hw/isa/piix.c | 6 ++++++
3 files changed, 9 insertions(+)
diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
index 08491693b4..86709ba2e4 100644
--- a/include/hw/southbridge/piix.h
+++ b/include/hw/southbridge/piix.h
@@ -70,6 +70,7 @@ struct PIIXState {
bool has_acpi;
bool has_pic;
+ bool has_pit;
bool has_usb;
bool smm_enabled;
};
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index fa39afd891..e38942a3c3 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -270,6 +270,8 @@ static void pc_init1(MachineState *machine,
&error_abort);
object_property_set_bool(OBJECT(pci_dev), "has-pic", false,
&error_abort);
+ object_property_set_bool(OBJECT(pci_dev), "has-pit", false,
+ &error_abort);
qdev_prop_set_uint32(DEVICE(pci_dev), "smb_io_base", 0xb100);
object_property_set_bool(OBJECT(pci_dev), "smm-enabled",
x86_machine_is_smm_enabled(x86ms),
diff --git a/hw/isa/piix.c b/hw/isa/piix.c
index d6d9ac6473..270b8eb1f7 100644
--- a/hw/isa/piix.c
+++ b/hw/isa/piix.c
@@ -361,6 +361,11 @@ static void pci_piix3_realize(PCIDevice *dev, Error **errp)
isa_bus_register_input_irqs(isa_bus, d->isa_irqs_in);
+ /* PIT */
+ if (d->has_pit) {
+ i8254_pit_init(isa_bus, 0x40, 0, NULL);
+ }
+
i8257_dma_init(isa_bus, 0);
/* RTC */
@@ -436,6 +441,7 @@ static Property pci_piix3_props[] = {
DEFINE_PROP_UINT32("smb_io_base", PIIXState, smb_io_base, 0),
DEFINE_PROP_BOOL("has-acpi", PIIXState, has_acpi, true),
DEFINE_PROP_BOOL("has-pic", PIIXState, has_pic, true),
+ DEFINE_PROP_BOOL("has-pit", PIIXState, has_pit, true),
DEFINE_PROP_BOOL("has-usb", PIIXState, has_usb, true),
DEFINE_PROP_BOOL("smm-enabled", PIIXState, smm_enabled, false),
DEFINE_PROP_END_OF_LIST(),
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 59/78] hw/isa/piix: Harmonize names of reset control memory regions
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (57 preceding siblings ...)
2023-10-19 18:23 ` [PULL v2 58/78] hw/isa/piix: Allow for optional PIT " Michael S. Tsirkin
@ 2023-10-19 18:23 ` Michael S. Tsirkin
2023-10-19 18:23 ` [PULL v2 60/78] hw/isa/piix: Share PIIX3's base class with PIIX4 Michael S. Tsirkin
` (19 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:23 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Bernhard Beschow, Philippe Mathieu-Daudé,
Aurelien Jarno, Marcel Apfelbaum, Hervé Poussineau
From: Bernhard Beschow <shentey@gmail.com>
There is no need for having different names here. Having the same name
further allows code to be shared between PIIX3 and PIIX4.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231007123843.127151-23-shentey@gmail.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/isa/piix.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/isa/piix.c b/hw/isa/piix.c
index 270b8eb1f7..bd66fb7475 100644
--- a/hw/isa/piix.c
+++ b/hw/isa/piix.c
@@ -339,7 +339,7 @@ static void pci_piix3_realize(PCIDevice *dev, Error **errp)
}
memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d,
- "piix3-reset-control", 1);
+ "piix-reset-control", 1);
memory_region_add_subregion_overlap(pci_address_space_io(dev),
PIIX_RCR_IOPORT, &d->rcr_mem, 1);
@@ -532,7 +532,7 @@ static void piix4_realize(PCIDevice *dev, Error **errp)
"intr", 1);
memory_region_init_io(&s->rcr_mem, OBJECT(dev), &rcr_ops, s,
- "reset-control", 1);
+ "piix-reset-control", 1);
memory_region_add_subregion_overlap(pci_address_space_io(dev),
PIIX_RCR_IOPORT, &s->rcr_mem, 1);
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 60/78] hw/isa/piix: Share PIIX3's base class with PIIX4
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (58 preceding siblings ...)
2023-10-19 18:23 ` [PULL v2 59/78] hw/isa/piix: Harmonize names of reset control memory regions Michael S. Tsirkin
@ 2023-10-19 18:23 ` Michael S. Tsirkin
2023-10-19 18:23 ` [PULL v2 61/78] hw/isa/piix: Reuse PIIX3 base class' realize method in PIIX4 Michael S. Tsirkin
` (18 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:23 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Bernhard Beschow, Hervé Poussineau,
Philippe Mathieu-Daudé, Aurelien Jarno, Marcel Apfelbaum
From: Bernhard Beschow <shentey@gmail.com>
Having a common base class will allow for futher code sharing between PIIX3 and
PIIX4. Moreover, it makes PIIX4 implement the acpi-dev-aml-interface.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231007123843.127151-24-shentey@gmail.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/isa/piix.c | 85 ++++++++++++++++++---------------------------------
1 file changed, 30 insertions(+), 55 deletions(-)
diff --git a/hw/isa/piix.c b/hw/isa/piix.c
index bd66fb7475..8f7d6c56a8 100644
--- a/hw/isa/piix.c
+++ b/hw/isa/piix.c
@@ -38,10 +38,6 @@
#include "migration/vmstate.h"
#include "hw/acpi/acpi_aml_interface.h"
-typedef struct PIIXState PIIX4State;
-
-DECLARE_INSTANCE_CHECKER(PIIX4State, PIIX4_PCI_DEVICE, TYPE_PIIX4_PCI_DEVICE)
-
static void piix3_set_irq_pic(PIIXState *piix3, int pic_irq)
{
qemu_set_irq(piix3->isa_irqs_in[pic_irq],
@@ -88,7 +84,7 @@ static void piix3_set_irq(void *opaque, int pirq, int level)
static void piix4_set_irq(void *opaque, int irq_num, int level)
{
int i, pic_irq, pic_level;
- PIIX4State *s = opaque;
+ PIIXState *s = opaque;
PCIBus *bus = pci_get_bus(&s->dev);
/* now we change the pic irq level according to the piix irq mappings */
@@ -108,7 +104,7 @@ static void piix4_set_irq(void *opaque, int irq_num, int level)
static void piix_request_i8259_irq(void *opaque, int irq, int level)
{
- PIIX4State *s = opaque;
+ PIIXState *s = opaque;
qemu_set_irq(s->cpu_intr, level);
}
@@ -156,8 +152,9 @@ static void piix3_write_config(PCIDevice *dev,
}
}
-static void piix_reset(PIIXState *d)
+static void piix_reset(DeviceState *dev)
{
+ PIIXState *d = PIIX_PCI_DEVICE(dev);
uint8_t *pci_conf = d->dev.config;
pci_conf[0x04] = 0x07; /* master, memory and I/O */
@@ -196,13 +193,6 @@ static void piix_reset(PIIXState *d)
d->rcr = 0;
}
-static void piix3_reset(DeviceState *dev)
-{
- PIIXState *d = PIIX_PCI_DEVICE(dev);
-
- piix_reset(d);
-}
-
static int piix3_post_load(void *opaque, int version_id)
{
PIIXState *piix3 = opaque;
@@ -227,7 +217,7 @@ static int piix3_post_load(void *opaque, int version_id)
static int piix4_post_load(void *opaque, int version_id)
{
- PIIX4State *s = opaque;
+ PIIXState *s = opaque;
if (version_id == 2) {
s->rcr = 0;
@@ -291,8 +281,8 @@ static const VMStateDescription vmstate_piix4 = {
.minimum_version_id = 2,
.post_load = piix4_post_load,
.fields = (VMStateField[]) {
- VMSTATE_PCI_DEVICE(dev, PIIX4State),
- VMSTATE_UINT8_V(rcr, PIIX4State, 3),
+ VMSTATE_PCI_DEVICE(dev, PIIXState),
+ VMSTATE_UINT8_V(rcr, PIIXState, 3),
VMSTATE_END_OF_LIST()
}
};
@@ -426,7 +416,7 @@ static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *scope)
qbus_build_aml(bus, scope);
}
-static void pci_piix3_init(Object *obj)
+static void pci_piix_init(Object *obj)
{
PIIXState *d = PIIX_PCI_DEVICE(obj);
@@ -434,7 +424,6 @@ static void pci_piix3_init(Object *obj)
ISA_NUM_IRQS);
object_initialize_child(obj, "rtc", &d->rtc, TYPE_MC146818_RTC);
- object_initialize_child(obj, "ide", &d->ide, TYPE_PIIX3_IDE);
}
static Property pci_piix3_props[] = {
@@ -447,27 +436,22 @@ static Property pci_piix3_props[] = {
DEFINE_PROP_END_OF_LIST(),
};
-static void pci_piix3_class_init(ObjectClass *klass, void *data)
+static void pci_piix_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
AcpiDevAmlIfClass *adevc = ACPI_DEV_AML_IF_CLASS(klass);
- k->config_write = piix3_write_config;
- dc->reset = piix3_reset;
+ dc->reset = piix_reset;
dc->desc = "ISA bridge";
- dc->vmsd = &vmstate_piix3;
dc->hotpluggable = false;
k->vendor_id = PCI_VENDOR_ID_INTEL;
- /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
- k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0;
k->class_id = PCI_CLASS_BRIDGE_ISA;
/*
- * Reason: part of PIIX3 southbridge, needs to be wired up by
+ * Reason: part of PIIX southbridge, needs to be wired up by e.g.
* pc_piix.c's pc_init1()
*/
dc->user_creatable = false;
- device_class_set_props(dc, pci_piix3_props);
adevc->build_dev_aml = build_pci_isa_aml;
}
@@ -475,9 +459,9 @@ static const TypeInfo piix_pci_type_info = {
.name = TYPE_PIIX_PCI_DEVICE,
.parent = TYPE_PCI_DEVICE,
.instance_size = sizeof(PIIXState),
- .instance_init = pci_piix3_init,
+ .instance_init = pci_piix_init,
.abstract = true,
- .class_init = pci_piix3_class_init,
+ .class_init = pci_piix_class_init,
.interfaces = (InterfaceInfo[]) {
{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
{ TYPE_ACPI_DEV_AML_IF },
@@ -500,22 +484,36 @@ static void piix3_realize(PCIDevice *dev, Error **errp)
pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq);
}
+static void piix3_init(Object *obj)
+{
+ PIIXState *d = PIIX_PCI_DEVICE(obj);
+
+ object_initialize_child(obj, "ide", &d->ide, TYPE_PIIX3_IDE);
+}
+
static void piix3_class_init(ObjectClass *klass, void *data)
{
+ DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
+ k->config_write = piix3_write_config;
k->realize = piix3_realize;
+ /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
+ k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0;
+ dc->vmsd = &vmstate_piix3;
+ device_class_set_props(dc, pci_piix3_props);
}
static const TypeInfo piix3_info = {
.name = TYPE_PIIX3_DEVICE,
.parent = TYPE_PIIX_PCI_DEVICE,
+ .instance_init = piix3_init,
.class_init = piix3_class_init,
};
static void piix4_realize(PCIDevice *dev, Error **errp)
{
- PIIX4State *s = PIIX4_PCI_DEVICE(dev);
+ PIIXState *s = PIIX_PCI_DEVICE(dev);
PCIBus *pci_bus = pci_get_bus(dev);
ISABus *isa_bus;
qemu_irq *i8259_out_irq;
@@ -584,18 +582,10 @@ static void piix4_realize(PCIDevice *dev, Error **errp)
pci_bus_irqs(pci_bus, piix4_set_irq, s, PIIX_NUM_PIRQS);
}
-static void piix4_isa_reset(DeviceState *dev)
-{
- PIIX4State *s = PIIX4_PCI_DEVICE(dev);
-
- piix_reset(s);
-}
-
static void piix4_init(Object *obj)
{
- PIIX4State *s = PIIX4_PCI_DEVICE(obj);
+ PIIXState *s = PIIX_PCI_DEVICE(obj);
- object_initialize_child(obj, "rtc", &s->rtc, TYPE_MC146818_RTC);
object_initialize_child(obj, "ide", &s->ide, TYPE_PIIX4_IDE);
object_initialize_child(obj, "uhci", &s->uhci, TYPE_PIIX4_USB_UHCI);
@@ -610,30 +600,15 @@ static void piix4_class_init(ObjectClass *klass, void *data)
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
k->realize = piix4_realize;
- k->vendor_id = PCI_VENDOR_ID_INTEL;
k->device_id = PCI_DEVICE_ID_INTEL_82371AB_0;
- k->class_id = PCI_CLASS_BRIDGE_ISA;
- dc->reset = piix4_isa_reset;
- dc->desc = "ISA bridge";
dc->vmsd = &vmstate_piix4;
- /*
- * Reason: part of PIIX4 southbridge, needs to be wired up,
- * e.g. by mips_malta_init()
- */
- dc->user_creatable = false;
- dc->hotpluggable = false;
}
static const TypeInfo piix4_info = {
.name = TYPE_PIIX4_PCI_DEVICE,
- .parent = TYPE_PCI_DEVICE,
- .instance_size = sizeof(PIIX4State),
+ .parent = TYPE_PIIX_PCI_DEVICE,
.instance_init = piix4_init,
.class_init = piix4_class_init,
- .interfaces = (InterfaceInfo[]) {
- { INTERFACE_CONVENTIONAL_PCI_DEVICE },
- { },
- },
};
static void piix3_register_types(void)
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 61/78] hw/isa/piix: Reuse PIIX3 base class' realize method in PIIX4
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (59 preceding siblings ...)
2023-10-19 18:23 ` [PULL v2 60/78] hw/isa/piix: Share PIIX3's base class with PIIX4 Michael S. Tsirkin
@ 2023-10-19 18:23 ` Michael S. Tsirkin
2023-10-19 18:23 ` [PULL v2 62/78] hw/isa/piix: Rename functions to be shared for PCI interrupt triggering Michael S. Tsirkin
` (17 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:23 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Bernhard Beschow, Hervé Poussineau,
Philippe Mathieu-Daudé, Marcel Apfelbaum, Aurelien Jarno
From: Bernhard Beschow <shentey@gmail.com>
Resolves duplicate code. Also makes PIIX4 respect the PIIX3 properties which get
added, too. This allows for using PIIX4 in the PC machine.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20231007123843.127151-25-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/isa/piix.c | 80 ++++++-------------------------------------------
hw/mips/malta.c | 5 ++--
2 files changed, 12 insertions(+), 73 deletions(-)
diff --git a/hw/isa/piix.c b/hw/isa/piix.c
index 8f7d6c56a8..2ab799b95e 100644
--- a/hw/isa/piix.c
+++ b/hw/isa/piix.c
@@ -315,7 +315,8 @@ static const MemoryRegionOps rcr_ops = {
},
};
-static void pci_piix3_realize(PCIDevice *dev, Error **errp)
+static void pci_piix_realize(PCIDevice *dev, const char *uhci_type,
+ Error **errp)
{
PIIXState *d = PIIX_PCI_DEVICE(dev);
PCIBus *pci_bus = pci_get_bus(dev);
@@ -374,8 +375,7 @@ static void pci_piix3_realize(PCIDevice *dev, Error **errp)
/* USB */
if (d->has_usb) {
- object_initialize_child(OBJECT(dev), "uhci", &d->uhci,
- TYPE_PIIX3_USB_UHCI);
+ object_initialize_child(OBJECT(dev), "uhci", &d->uhci, uhci_type);
qdev_prop_set_int32(DEVICE(&d->uhci), "addr", dev->devfn + 2);
if (!qdev_realize(DEVICE(&d->uhci), BUS(pci_bus), errp)) {
return;
@@ -426,7 +426,7 @@ static void pci_piix_init(Object *obj)
object_initialize_child(obj, "rtc", &d->rtc, TYPE_MC146818_RTC);
}
-static Property pci_piix3_props[] = {
+static Property pci_piix_props[] = {
DEFINE_PROP_UINT32("smb_io_base", PIIXState, smb_io_base, 0),
DEFINE_PROP_BOOL("has-acpi", PIIXState, has_acpi, true),
DEFINE_PROP_BOOL("has-pic", PIIXState, has_pic, true),
@@ -452,6 +452,7 @@ static void pci_piix_class_init(ObjectClass *klass, void *data)
* pc_piix.c's pc_init1()
*/
dc->user_creatable = false;
+ device_class_set_props(dc, pci_piix_props);
adevc->build_dev_aml = build_pci_isa_aml;
}
@@ -475,7 +476,7 @@ static void piix3_realize(PCIDevice *dev, Error **errp)
PIIXState *piix3 = PIIX_PCI_DEVICE(dev);
PCIBus *pci_bus = pci_get_bus(dev);
- pci_piix3_realize(dev, errp);
+ pci_piix_realize(dev, TYPE_PIIX3_USB_UHCI, errp);
if (*errp) {
return;
}
@@ -501,7 +502,6 @@ static void piix3_class_init(ObjectClass *klass, void *data)
/* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0;
dc->vmsd = &vmstate_piix3;
- device_class_set_props(dc, pci_piix3_props);
}
static const TypeInfo piix3_info = {
@@ -513,72 +513,15 @@ static const TypeInfo piix3_info = {
static void piix4_realize(PCIDevice *dev, Error **errp)
{
+ ERRP_GUARD();
PIIXState *s = PIIX_PCI_DEVICE(dev);
PCIBus *pci_bus = pci_get_bus(dev);
- ISABus *isa_bus;
- qemu_irq *i8259_out_irq;
- qemu_irq *i8259;
- size_t i;
- isa_bus = isa_bus_new(DEVICE(dev), pci_address_space(dev),
- pci_address_space_io(dev), errp);
- if (!isa_bus) {
+ pci_piix_realize(dev, TYPE_PIIX4_USB_UHCI, errp);
+ if (*errp) {
return;
}
- qdev_init_gpio_out_named(DEVICE(dev), &s->cpu_intr,
- "intr", 1);
-
- memory_region_init_io(&s->rcr_mem, OBJECT(dev), &rcr_ops, s,
- "piix-reset-control", 1);
- memory_region_add_subregion_overlap(pci_address_space_io(dev),
- PIIX_RCR_IOPORT, &s->rcr_mem, 1);
-
- /* initialize i8259 pic */
- i8259_out_irq = qemu_allocate_irqs(piix_request_i8259_irq, s, 1);
- i8259 = i8259_init(isa_bus, *i8259_out_irq);
-
- for (i = 0; i < ISA_NUM_IRQS; i++) {
- s->isa_irqs_in[i] = i8259[i];
- }
-
- g_free(i8259);
-
- /* initialize ISA irqs */
- isa_bus_register_input_irqs(isa_bus, s->isa_irqs_in);
-
- /* initialize pit */
- i8254_pit_init(isa_bus, 0x40, 0, NULL);
-
- /* DMA */
- i8257_dma_init(isa_bus, 0);
-
- /* RTC */
- qdev_prop_set_int32(DEVICE(&s->rtc), "base_year", 2000);
- if (!qdev_realize(DEVICE(&s->rtc), BUS(isa_bus), errp)) {
- return;
- }
- s->rtc.irq = isa_get_irq(ISA_DEVICE(&s->rtc), s->rtc.isairq);
-
- /* IDE */
- qdev_prop_set_int32(DEVICE(&s->ide), "addr", dev->devfn + 1);
- if (!qdev_realize(DEVICE(&s->ide), BUS(pci_bus), errp)) {
- return;
- }
-
- /* USB */
- qdev_prop_set_int32(DEVICE(&s->uhci), "addr", dev->devfn + 2);
- if (!qdev_realize(DEVICE(&s->uhci), BUS(pci_bus), errp)) {
- return;
- }
-
- /* ACPI controller */
- qdev_prop_set_int32(DEVICE(&s->pm), "addr", dev->devfn + 3);
- if (!qdev_realize(DEVICE(&s->pm), BUS(pci_bus), errp)) {
- return;
- }
- qdev_connect_gpio_out(DEVICE(&s->pm), 0, s->isa_irqs_in[9]);
-
pci_bus_irqs(pci_bus, piix4_set_irq, s, PIIX_NUM_PIRQS);
}
@@ -587,11 +530,6 @@ static void piix4_init(Object *obj)
PIIXState *s = PIIX_PCI_DEVICE(obj);
object_initialize_child(obj, "ide", &s->ide, TYPE_PIIX4_IDE);
- object_initialize_child(obj, "uhci", &s->uhci, TYPE_PIIX4_USB_UHCI);
-
- object_initialize_child(obj, "pm", &s->pm, TYPE_PIIX4_PM);
- qdev_prop_set_uint32(DEVICE(&s->pm), "smb_io_base", 0x1100);
- qdev_prop_set_bit(DEVICE(&s->pm), "smm-enabled", 0);
}
static void piix4_class_init(ObjectClass *klass, void *data)
diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index dac27fad9d..155f3c1cc8 100644
--- a/hw/mips/malta.c
+++ b/hw/mips/malta.c
@@ -1238,8 +1238,9 @@ void mips_malta_init(MachineState *machine)
pci_bus_map_irqs(pci_bus, malta_pci_slot_get_pirq);
/* Southbridge */
- piix4 = pci_create_simple_multifunction(pci_bus, PIIX4_PCI_DEVFN,
- TYPE_PIIX4_PCI_DEVICE);
+ piix4 = pci_new_multifunction(PIIX4_PCI_DEVFN, TYPE_PIIX4_PCI_DEVICE);
+ qdev_prop_set_uint32(DEVICE(piix4), "smb_io_base", 0x1100);
+ pci_realize_and_unref(piix4, pci_bus, &error_fatal);
isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix4), "isa.0"));
dev = DEVICE(object_resolve_path_component(OBJECT(piix4), "ide"));
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 62/78] hw/isa/piix: Rename functions to be shared for PCI interrupt triggering
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (60 preceding siblings ...)
2023-10-19 18:23 ` [PULL v2 61/78] hw/isa/piix: Reuse PIIX3 base class' realize method in PIIX4 Michael S. Tsirkin
@ 2023-10-19 18:23 ` Michael S. Tsirkin
2023-10-19 18:23 ` [PULL v2 63/78] hw/isa/piix: Reuse PIIX3's PCI interrupt triggering in PIIX4 Michael S. Tsirkin
` (16 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:23 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Bernhard Beschow, Philippe Mathieu-Daudé,
Aurelien Jarno, Marcel Apfelbaum, Hervé Poussineau
From: Bernhard Beschow <shentey@gmail.com>
PIIX4 will get the same optimizations which are already implemented for
PIIX3.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231007123843.127151-26-shentey@gmail.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/isa/piix.c | 72 +++++++++++++++++++++++++--------------------------
1 file changed, 36 insertions(+), 36 deletions(-)
diff --git a/hw/isa/piix.c b/hw/isa/piix.c
index 2ab799b95e..449c1baaab 100644
--- a/hw/isa/piix.c
+++ b/hw/isa/piix.c
@@ -38,47 +38,47 @@
#include "migration/vmstate.h"
#include "hw/acpi/acpi_aml_interface.h"
-static void piix3_set_irq_pic(PIIXState *piix3, int pic_irq)
+static void piix_set_irq_pic(PIIXState *s, int pic_irq)
{
- qemu_set_irq(piix3->isa_irqs_in[pic_irq],
- !!(piix3->pic_levels &
+ qemu_set_irq(s->isa_irqs_in[pic_irq],
+ !!(s->pic_levels &
(((1ULL << PIIX_NUM_PIRQS) - 1) <<
(pic_irq * PIIX_NUM_PIRQS))));
}
-static void piix3_set_irq_level_internal(PIIXState *piix3, int pirq, int level)
+static void piix_set_pci_irq_level_internal(PIIXState *s, int pirq, int level)
{
int pic_irq;
uint64_t mask;
- pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
+ pic_irq = s->dev.config[PIIX_PIRQCA + pirq];
if (pic_irq >= ISA_NUM_IRQS) {
return;
}
mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq);
- piix3->pic_levels &= ~mask;
- piix3->pic_levels |= mask * !!level;
+ s->pic_levels &= ~mask;
+ s->pic_levels |= mask * !!level;
}
-static void piix3_set_irq_level(PIIXState *piix3, int pirq, int level)
+static void piix_set_pci_irq_level(PIIXState *s, int pirq, int level)
{
int pic_irq;
- pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
+ pic_irq = s->dev.config[PIIX_PIRQCA + pirq];
if (pic_irq >= ISA_NUM_IRQS) {
return;
}
- piix3_set_irq_level_internal(piix3, pirq, level);
+ piix_set_pci_irq_level_internal(s, pirq, level);
- piix3_set_irq_pic(piix3, pic_irq);
+ piix_set_irq_pic(s, pic_irq);
}
-static void piix3_set_irq(void *opaque, int pirq, int level)
+static void piix_set_pci_irq(void *opaque, int pirq, int level)
{
- PIIXState *piix3 = opaque;
- piix3_set_irq_level(piix3, pirq, level);
+ PIIXState *s = opaque;
+ piix_set_pci_irq_level(s, pirq, level);
}
static void piix4_set_irq(void *opaque, int irq_num, int level)
@@ -108,10 +108,10 @@ static void piix_request_i8259_irq(void *opaque, int irq, int level)
qemu_set_irq(s->cpu_intr, level);
}
-static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
+static PCIINTxRoute piix_route_intx_pin_to_irq(void *opaque, int pin)
{
- PIIXState *piix3 = opaque;
- int irq = piix3->dev.config[PIIX_PIRQCA + pin];
+ PCIDevice *pci_dev = opaque;
+ int irq = pci_dev->config[PIIX_PIRQCA + pin];
PCIINTxRoute route;
if (irq < ISA_NUM_IRQS) {
@@ -125,29 +125,29 @@ static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
}
/* irq routing is changed. so rebuild bitmap */
-static void piix3_update_irq_levels(PIIXState *piix3)
+static void piix_update_pci_irq_levels(PIIXState *s)
{
- PCIBus *bus = pci_get_bus(&piix3->dev);
+ PCIBus *bus = pci_get_bus(&s->dev);
int pirq;
- piix3->pic_levels = 0;
+ s->pic_levels = 0;
for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
- piix3_set_irq_level(piix3, pirq, pci_bus_get_irq_level(bus, pirq));
+ piix_set_pci_irq_level(s, pirq, pci_bus_get_irq_level(bus, pirq));
}
}
-static void piix3_write_config(PCIDevice *dev,
- uint32_t address, uint32_t val, int len)
+static void piix_write_config(PCIDevice *dev, uint32_t address, uint32_t val,
+ int len)
{
pci_default_write_config(dev, address, val, len);
if (ranges_overlap(address, len, PIIX_PIRQCA, 4)) {
- PIIXState *piix3 = PIIX_PCI_DEVICE(dev);
+ PIIXState *s = PIIX_PCI_DEVICE(dev);
int pic_irq;
- pci_bus_fire_intx_routing_notifier(pci_get_bus(&piix3->dev));
- piix3_update_irq_levels(piix3);
+ pci_bus_fire_intx_routing_notifier(pci_get_bus(&s->dev));
+ piix_update_pci_irq_levels(s);
for (pic_irq = 0; pic_irq < ISA_NUM_IRQS; pic_irq++) {
- piix3_set_irq_pic(piix3, pic_irq);
+ piix_set_irq_pic(s, pic_irq);
}
}
}
@@ -193,9 +193,9 @@ static void piix_reset(DeviceState *dev)
d->rcr = 0;
}
-static int piix3_post_load(void *opaque, int version_id)
+static int piix_post_load(void *opaque, int version_id)
{
- PIIXState *piix3 = opaque;
+ PIIXState *s = opaque;
int pirq;
/*
@@ -207,10 +207,10 @@ static int piix3_post_load(void *opaque, int version_id)
* Here, we update irq levels without raising the interrupt.
* Interrupt state will be deserialized separately through the i8259.
*/
- piix3->pic_levels = 0;
+ s->pic_levels = 0;
for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
- piix3_set_irq_level_internal(piix3, pirq,
- pci_bus_get_irq_level(pci_get_bus(&piix3->dev), pirq));
+ piix_set_pci_irq_level_internal(s, pirq,
+ pci_bus_get_irq_level(pci_get_bus(&s->dev), pirq));
}
return 0;
}
@@ -261,7 +261,7 @@ static const VMStateDescription vmstate_piix3 = {
.name = "PIIX3",
.version_id = 3,
.minimum_version_id = 2,
- .post_load = piix3_post_load,
+ .post_load = piix_post_load,
.pre_save = piix3_pre_save,
.fields = (VMStateField[]) {
VMSTATE_PCI_DEVICE(dev, PIIXState),
@@ -481,8 +481,8 @@ static void piix3_realize(PCIDevice *dev, Error **errp)
return;
}
- pci_bus_irqs(pci_bus, piix3_set_irq, piix3, PIIX_NUM_PIRQS);
- pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq);
+ pci_bus_irqs(pci_bus, piix_set_pci_irq, piix3, PIIX_NUM_PIRQS);
+ pci_bus_set_route_irq_fn(pci_bus, piix_route_intx_pin_to_irq);
}
static void piix3_init(Object *obj)
@@ -497,7 +497,7 @@ static void piix3_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
- k->config_write = piix3_write_config;
+ k->config_write = piix_write_config;
k->realize = piix3_realize;
/* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0;
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 63/78] hw/isa/piix: Reuse PIIX3's PCI interrupt triggering in PIIX4
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (61 preceding siblings ...)
2023-10-19 18:23 ` [PULL v2 62/78] hw/isa/piix: Rename functions to be shared for PCI interrupt triggering Michael S. Tsirkin
@ 2023-10-19 18:23 ` Michael S. Tsirkin
2023-10-19 18:24 ` [PULL v2 64/78] hw/isa/piix: Resolve duplicate code regarding PCI interrupt wiring Michael S. Tsirkin
` (15 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:23 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Bernhard Beschow, Marcel Apfelbaum,
Hervé Poussineau, Philippe Mathieu-Daudé,
Aurelien Jarno
From: Bernhard Beschow <shentey@gmail.com>
Speeds up PIIX4 which resolves an old TODO. Also makes PIIX4 compatible with Xen
which relies on pci_bus_fire_intx_routing_notifier() to be fired.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231007123843.127151-27-shentey@gmail.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/isa/piix.c | 27 +++------------------------
1 file changed, 3 insertions(+), 24 deletions(-)
diff --git a/hw/isa/piix.c b/hw/isa/piix.c
index 449c1baaab..17677c2126 100644
--- a/hw/isa/piix.c
+++ b/hw/isa/piix.c
@@ -81,27 +81,6 @@ static void piix_set_pci_irq(void *opaque, int pirq, int level)
piix_set_pci_irq_level(s, pirq, level);
}
-static void piix4_set_irq(void *opaque, int irq_num, int level)
-{
- int i, pic_irq, pic_level;
- PIIXState *s = opaque;
- PCIBus *bus = pci_get_bus(&s->dev);
-
- /* now we change the pic irq level according to the piix irq mappings */
- /* XXX: optimize */
- pic_irq = s->dev.config[PIIX_PIRQCA + irq_num];
- if (pic_irq < ISA_NUM_IRQS) {
- /* The pic level is the logical OR of all the PCI irqs mapped to it. */
- pic_level = 0;
- for (i = 0; i < PIIX_NUM_PIRQS; i++) {
- if (pic_irq == s->dev.config[PIIX_PIRQCA + i]) {
- pic_level |= pci_bus_get_irq_level(bus, i);
- }
- }
- qemu_set_irq(s->isa_irqs_in[pic_irq], pic_level);
- }
-}
-
static void piix_request_i8259_irq(void *opaque, int irq, int level)
{
PIIXState *s = opaque;
@@ -223,7 +202,7 @@ static int piix4_post_load(void *opaque, int version_id)
s->rcr = 0;
}
- return 0;
+ return piix_post_load(opaque, version_id);
}
static int piix3_pre_save(void *opaque)
@@ -442,6 +421,7 @@ static void pci_piix_class_init(ObjectClass *klass, void *data)
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
AcpiDevAmlIfClass *adevc = ACPI_DEV_AML_IF_CLASS(klass);
+ k->config_write = piix_write_config;
dc->reset = piix_reset;
dc->desc = "ISA bridge";
dc->hotpluggable = false;
@@ -497,7 +477,6 @@ static void piix3_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
- k->config_write = piix_write_config;
k->realize = piix3_realize;
/* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0;
@@ -522,7 +501,7 @@ static void piix4_realize(PCIDevice *dev, Error **errp)
return;
}
- pci_bus_irqs(pci_bus, piix4_set_irq, s, PIIX_NUM_PIRQS);
+ pci_bus_irqs(pci_bus, piix_set_pci_irq, s, PIIX_NUM_PIRQS);
}
static void piix4_init(Object *obj)
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 64/78] hw/isa/piix: Resolve duplicate code regarding PCI interrupt wiring
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (62 preceding siblings ...)
2023-10-19 18:23 ` [PULL v2 63/78] hw/isa/piix: Reuse PIIX3's PCI interrupt triggering in PIIX4 Michael S. Tsirkin
@ 2023-10-19 18:24 ` Michael S. Tsirkin
2023-10-19 18:24 ` [PULL v2 65/78] hw/isa/piix: Implement multi-process QEMU support also for PIIX4 Michael S. Tsirkin
` (14 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:24 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Bernhard Beschow, Philippe Mathieu-Daudé,
Aurelien Jarno, Marcel Apfelbaum, Hervé Poussineau
From: Bernhard Beschow <shentey@gmail.com>
Now that both PIIX3 and PIIX4 use piix_set_irq() to trigger PCI IRQs the wiring
in the respective realize methods can be shared, too.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231007123843.127151-28-shentey@gmail.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/isa/piix.c | 13 ++-----------
1 file changed, 2 insertions(+), 11 deletions(-)
diff --git a/hw/isa/piix.c b/hw/isa/piix.c
index 17677c2126..cba2098ca2 100644
--- a/hw/isa/piix.c
+++ b/hw/isa/piix.c
@@ -372,6 +372,8 @@ static void pci_piix_realize(PCIDevice *dev, const char *uhci_type,
}
qdev_connect_gpio_out(DEVICE(&d->pm), 0, d->isa_irqs_in[9]);
}
+
+ pci_bus_irqs(pci_bus, piix_set_pci_irq, d, PIIX_NUM_PIRQS);
}
static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *scope)
@@ -453,7 +455,6 @@ static const TypeInfo piix_pci_type_info = {
static void piix3_realize(PCIDevice *dev, Error **errp)
{
ERRP_GUARD();
- PIIXState *piix3 = PIIX_PCI_DEVICE(dev);
PCIBus *pci_bus = pci_get_bus(dev);
pci_piix_realize(dev, TYPE_PIIX3_USB_UHCI, errp);
@@ -461,7 +462,6 @@ static void piix3_realize(PCIDevice *dev, Error **errp)
return;
}
- pci_bus_irqs(pci_bus, piix_set_pci_irq, piix3, PIIX_NUM_PIRQS);
pci_bus_set_route_irq_fn(pci_bus, piix_route_intx_pin_to_irq);
}
@@ -492,16 +492,7 @@ static const TypeInfo piix3_info = {
static void piix4_realize(PCIDevice *dev, Error **errp)
{
- ERRP_GUARD();
- PIIXState *s = PIIX_PCI_DEVICE(dev);
- PCIBus *pci_bus = pci_get_bus(dev);
-
pci_piix_realize(dev, TYPE_PIIX4_USB_UHCI, errp);
- if (*errp) {
- return;
- }
-
- pci_bus_irqs(pci_bus, piix_set_pci_irq, s, PIIX_NUM_PIRQS);
}
static void piix4_init(Object *obj)
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 65/78] hw/isa/piix: Implement multi-process QEMU support also for PIIX4
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (63 preceding siblings ...)
2023-10-19 18:24 ` [PULL v2 64/78] hw/isa/piix: Resolve duplicate code regarding PCI interrupt wiring Michael S. Tsirkin
@ 2023-10-19 18:24 ` Michael S. Tsirkin
2023-10-19 18:24 ` [PULL v2 66/78] hw/i386/pc_piix: Make PIIX4 south bridge usable in PC machine Michael S. Tsirkin
` (13 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:24 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Bernhard Beschow, Hervé Poussineau,
Philippe Mathieu-Daudé, Aurelien Jarno, Marcel Apfelbaum
From: Bernhard Beschow <shentey@gmail.com>
So far multi-process QEMU was only implemented for PIIX3. Move the support into
the base class to achieve feature parity between both device models.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20231007123843.127151-29-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/isa/piix.c | 9 +--------
1 file changed, 1 insertion(+), 8 deletions(-)
diff --git a/hw/isa/piix.c b/hw/isa/piix.c
index cba2098ca2..04ebed5b52 100644
--- a/hw/isa/piix.c
+++ b/hw/isa/piix.c
@@ -374,6 +374,7 @@ static void pci_piix_realize(PCIDevice *dev, const char *uhci_type,
}
pci_bus_irqs(pci_bus, piix_set_pci_irq, d, PIIX_NUM_PIRQS);
+ pci_bus_set_route_irq_fn(pci_bus, piix_route_intx_pin_to_irq);
}
static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *scope)
@@ -454,15 +455,7 @@ static const TypeInfo piix_pci_type_info = {
static void piix3_realize(PCIDevice *dev, Error **errp)
{
- ERRP_GUARD();
- PCIBus *pci_bus = pci_get_bus(dev);
-
pci_piix_realize(dev, TYPE_PIIX3_USB_UHCI, errp);
- if (*errp) {
- return;
- }
-
- pci_bus_set_route_irq_fn(pci_bus, piix_route_intx_pin_to_irq);
}
static void piix3_init(Object *obj)
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 66/78] hw/i386/pc_piix: Make PIIX4 south bridge usable in PC machine
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (64 preceding siblings ...)
2023-10-19 18:24 ` [PULL v2 65/78] hw/isa/piix: Implement multi-process QEMU support also for PIIX4 Michael S. Tsirkin
@ 2023-10-19 18:24 ` Michael S. Tsirkin
2023-10-19 18:24 ` [PULL v2 67/78] vhost-user-common: send get_inflight_fd once Michael S. Tsirkin
` (12 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:24 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Bernhard Beschow, Paolo Bonzini, Richard Henderson,
Eduardo Habkost, Marcel Apfelbaum
From: Bernhard Beschow <shentey@gmail.com>
QEMU's PIIX3 implementation actually models the real PIIX4, but with different
PCI IDs. Usually, guests deal just fine with it. Still, in order to provide a
more consistent illusion to guests, allow QEMU's PIIX4 implementation to be used
in the PC machine.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20231007123843.127151-30-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
include/hw/i386/pc.h | 2 +
hw/i386/pc.c | 1 +
hw/i386/pc_piix.c | 61 +++++++++++++++++++++++++++-
docs/system/target-i386-desc.rst.inc | 8 ++++
4 files changed, 71 insertions(+), 1 deletion(-)
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index bec38cb92c..29a9724524 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -42,6 +42,7 @@ typedef struct PCMachineState {
uint64_t max_ram_below_4g;
OnOffAuto vmport;
SmbiosEntryPointType smbios_entry_point_type;
+ const char *south_bridge;
bool acpi_build_enabled;
bool smbus_enabled;
@@ -92,6 +93,7 @@ struct PCMachineClass {
/* Device configuration: */
bool pci_enabled;
bool kvmclock_enabled;
+ const char *default_south_bridge;
/* Compat options: */
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 355e1b7cf6..6293f57a0c 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1706,6 +1706,7 @@ static void pc_machine_initfn(Object *obj)
#endif /* CONFIG_VMPORT */
pcms->max_ram_below_4g = 0; /* use default */
pcms->smbios_entry_point_type = pcmc->default_smbios_ep_type;
+ pcms->south_bridge = pcmc->default_south_bridge;
/* acpi build is enabled by default if machine supports it */
pcms->acpi_build_enabled = pcmc->has_acpi_build;
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index e38942a3c3..334d9a0299 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -262,7 +262,7 @@ static void pc_init1(MachineState *machine,
DeviceState *dev;
size_t i;
- pci_dev = pci_new_multifunction(-1, TYPE_PIIX3_DEVICE);
+ pci_dev = pci_new_multifunction(-1, pcms->south_bridge);
object_property_set_bool(OBJECT(pci_dev), "has-usb",
machine_usb(machine), &error_abort);
object_property_set_bool(OBJECT(pci_dev), "has-acpi",
@@ -394,6 +394,56 @@ static void pc_init1(MachineState *machine,
}
}
+typedef enum PCSouthBridgeOption {
+ PC_SOUTH_BRIDGE_OPTION_PIIX3,
+ PC_SOUTH_BRIDGE_OPTION_PIIX4,
+ PC_SOUTH_BRIDGE_OPTION_MAX,
+} PCSouthBridgeOption;
+
+static const QEnumLookup PCSouthBridgeOption_lookup = {
+ .array = (const char *const[]) {
+ [PC_SOUTH_BRIDGE_OPTION_PIIX3] = TYPE_PIIX3_DEVICE,
+ [PC_SOUTH_BRIDGE_OPTION_PIIX4] = TYPE_PIIX4_PCI_DEVICE,
+ },
+ .size = PC_SOUTH_BRIDGE_OPTION_MAX
+};
+
+#define NotifyVmexitOption_str(val) \
+ qapi_enum_lookup(&NotifyVmexitOption_lookup, (val))
+
+static int pc_get_south_bridge(Object *obj, Error **errp)
+{
+ PCMachineState *pcms = PC_MACHINE(obj);
+ int i;
+
+ for (i = 0; i < PCSouthBridgeOption_lookup.size; i++) {
+ if (g_strcmp0(PCSouthBridgeOption_lookup.array[i],
+ pcms->south_bridge) == 0) {
+ return i;
+ }
+ }
+
+ error_setg(errp, "Invalid south bridge value set");
+ return 0;
+}
+
+static void pc_set_south_bridge(Object *obj, int value, Error **errp)
+{
+ PCMachineState *pcms = PC_MACHINE(obj);
+
+ if (value < 0) {
+ error_setg(errp, "Value can't be negative");
+ return;
+ }
+
+ if (value >= PCSouthBridgeOption_lookup.size) {
+ error_setg(errp, "Value too big");
+ return;
+ }
+
+ pcms->south_bridge = PCSouthBridgeOption_lookup.array[value];
+}
+
/* Looking for a pc_compat_2_4() function? It doesn't exist.
* pc_compat_*() functions that run on machine-init time and
* change global QEMU state are deprecated. Please don't create
@@ -473,6 +523,8 @@ static void pc_xen_hvm_init(MachineState *machine)
static void pc_i440fx_machine_options(MachineClass *m)
{
PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
+ ObjectClass *oc = OBJECT_CLASS(m);
+ pcmc->default_south_bridge = TYPE_PIIX3_DEVICE;
pcmc->pci_root_uid = 0;
pcmc->default_cpu_version = 1;
@@ -484,6 +536,13 @@ static void pc_i440fx_machine_options(MachineClass *m)
m->no_parallel = !module_object_class_by_name(TYPE_ISA_PARALLEL);
machine_class_allow_dynamic_sysbus_dev(m, TYPE_RAMFB_DEVICE);
machine_class_allow_dynamic_sysbus_dev(m, TYPE_VMBUS_BRIDGE);
+
+ object_class_property_add_enum(oc, "x-south-bridge", "PCSouthBridgeOption",
+ &PCSouthBridgeOption_lookup,
+ pc_get_south_bridge,
+ pc_set_south_bridge);
+ object_class_property_set_description(oc, "x-south-bridge",
+ "Use a different south bridge than PIIX3");
}
static void pc_i440fx_8_2_machine_options(MachineClass *m)
diff --git a/docs/system/target-i386-desc.rst.inc b/docs/system/target-i386-desc.rst.inc
index 7d1fffacbe..5ebbcda9db 100644
--- a/docs/system/target-i386-desc.rst.inc
+++ b/docs/system/target-i386-desc.rst.inc
@@ -71,3 +71,11 @@ machine property, i.e.
|qemu_system_x86| some.img \
-audiodev <backend>,id=<name> \
-machine pcspk-audiodev=<name>
+
+Machine-specific options
+~~~~~~~~~~~~~~~~~~~~~~~~
+
+It supports the following machine-specific options:
+
+- ``x-south-bridge=PIIX3|piix4-isa`` (Experimental option to select a particular
+ south bridge. Default: ``PIIX3``)
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 67/78] vhost-user-common: send get_inflight_fd once
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (65 preceding siblings ...)
2023-10-19 18:24 ` [PULL v2 66/78] hw/i386/pc_piix: Make PIIX4 south bridge usable in PC machine Michael S. Tsirkin
@ 2023-10-19 18:24 ` Michael S. Tsirkin
2023-10-19 18:24 ` [PULL v2 68/78] vhost: move and rename the conn retry times Michael S. Tsirkin
` (11 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:24 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Li Feng, Raphael Norwitz, Paolo Bonzini, Fam Zheng
From: Li Feng <fengli@smartx.com>
Currently the get_inflight_fd will be sent every time the device is started, and
the backend will allocate shared memory to save the inflight state. If the
backend finds that it receives the second get_inflight_fd, it will release the
previous shared memory, which breaks inflight working logic.
This patch is a preparation for the following patches.
Signed-off-by: Li Feng <fengli@smartx.com>
Reviewed-by: Raphael Norwitz <raphael.norwitz@nutanix.com>
Message-Id: <20231009044735.941655-2-fengli@smartx.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/scsi/vhost-scsi-common.c | 37 ++++++++++++++++++-------------------
1 file changed, 18 insertions(+), 19 deletions(-)
diff --git a/hw/scsi/vhost-scsi-common.c b/hw/scsi/vhost-scsi-common.c
index a06f01af26..a61cd0e907 100644
--- a/hw/scsi/vhost-scsi-common.c
+++ b/hw/scsi/vhost-scsi-common.c
@@ -52,20 +52,28 @@ int vhost_scsi_common_start(VHostSCSICommon *vsc)
vsc->dev.acked_features = vdev->guest_features;
- assert(vsc->inflight == NULL);
- vsc->inflight = g_new0(struct vhost_inflight, 1);
- ret = vhost_dev_get_inflight(&vsc->dev,
- vs->conf.virtqueue_size,
- vsc->inflight);
+ ret = vhost_dev_prepare_inflight(&vsc->dev, vdev);
if (ret < 0) {
- error_report("Error get inflight: %d", -ret);
+ error_report("Error setting inflight format: %d", -ret);
goto err_guest_notifiers;
}
- ret = vhost_dev_set_inflight(&vsc->dev, vsc->inflight);
- if (ret < 0) {
- error_report("Error set inflight: %d", -ret);
- goto err_guest_notifiers;
+ if (vsc->inflight) {
+ if (!vsc->inflight->addr) {
+ ret = vhost_dev_get_inflight(&vsc->dev,
+ vs->conf.virtqueue_size,
+ vsc->inflight);
+ if (ret < 0) {
+ error_report("Error getting inflight: %d", -ret);
+ goto err_guest_notifiers;
+ }
+ }
+
+ ret = vhost_dev_set_inflight(&vsc->dev, vsc->inflight);
+ if (ret < 0) {
+ error_report("Error setting inflight: %d", -ret);
+ goto err_guest_notifiers;
+ }
}
ret = vhost_dev_start(&vsc->dev, vdev, true);
@@ -85,9 +93,6 @@ int vhost_scsi_common_start(VHostSCSICommon *vsc)
return ret;
err_guest_notifiers:
- g_free(vsc->inflight);
- vsc->inflight = NULL;
-
k->set_guest_notifiers(qbus->parent, vsc->dev.nvqs, false);
err_host_notifiers:
vhost_dev_disable_notifiers(&vsc->dev, vdev);
@@ -111,12 +116,6 @@ void vhost_scsi_common_stop(VHostSCSICommon *vsc)
}
assert(ret >= 0);
- if (vsc->inflight) {
- vhost_dev_free_inflight(vsc->inflight);
- g_free(vsc->inflight);
- vsc->inflight = NULL;
- }
-
vhost_dev_disable_notifiers(&vsc->dev, vdev);
}
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 68/78] vhost: move and rename the conn retry times
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (66 preceding siblings ...)
2023-10-19 18:24 ` [PULL v2 67/78] vhost-user-common: send get_inflight_fd once Michael S. Tsirkin
@ 2023-10-19 18:24 ` Michael S. Tsirkin
2023-10-19 18:24 ` [PULL v2 69/78] vhost-user-scsi: support reconnect to backend Michael S. Tsirkin
` (10 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:24 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Li Feng, Raphael Norwitz, Kevin Wolf, Hanna Reitz,
Alex Bennée, Viresh Kumar, qemu-block
From: Li Feng <fengli@smartx.com>
Multiple devices need this macro, move it to a common header.
Signed-off-by: Li Feng <fengli@smartx.com>
Reviewed-by: Raphael Norwitz <raphael.norwitz@nutanix.com>
Message-Id: <20231009044735.941655-3-fengli@smartx.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
include/hw/virtio/vhost.h | 2 ++
hw/block/vhost-user-blk.c | 4 +---
hw/virtio/vhost-user-gpio.c | 3 +--
3 files changed, 4 insertions(+), 5 deletions(-)
diff --git a/include/hw/virtio/vhost.h b/include/hw/virtio/vhost.h
index 00e0a669b8..5e8183f64a 100644
--- a/include/hw/virtio/vhost.h
+++ b/include/hw/virtio/vhost.h
@@ -8,6 +8,8 @@
#define VHOST_F_DEVICE_IOTLB 63
#define VHOST_USER_F_PROTOCOL_FEATURES 30
+#define VU_REALIZE_CONN_RETRIES 3
+
/* Generic structures common for any vhost based device. */
struct vhost_inflight {
diff --git a/hw/block/vhost-user-blk.c b/hw/block/vhost-user-blk.c
index eecf3f7a81..3c69fa47d5 100644
--- a/hw/block/vhost-user-blk.c
+++ b/hw/block/vhost-user-blk.c
@@ -32,8 +32,6 @@
#include "sysemu/sysemu.h"
#include "sysemu/runstate.h"
-#define REALIZE_CONNECTION_RETRIES 3
-
static const int user_feature_bits[] = {
VIRTIO_BLK_F_SIZE_MAX,
VIRTIO_BLK_F_SEG_MAX,
@@ -482,7 +480,7 @@ static void vhost_user_blk_device_realize(DeviceState *dev, Error **errp)
s->inflight = g_new0(struct vhost_inflight, 1);
s->vhost_vqs = g_new0(struct vhost_virtqueue, s->num_queues);
- retries = REALIZE_CONNECTION_RETRIES;
+ retries = VU_REALIZE_CONN_RETRIES;
assert(!*errp);
do {
if (*errp) {
diff --git a/hw/virtio/vhost-user-gpio.c b/hw/virtio/vhost-user-gpio.c
index 3d7fae3984..fc784e4213 100644
--- a/hw/virtio/vhost-user-gpio.c
+++ b/hw/virtio/vhost-user-gpio.c
@@ -15,7 +15,6 @@
#include "standard-headers/linux/virtio_ids.h"
#include "trace.h"
-#define REALIZE_CONNECTION_RETRIES 3
#define VHOST_NVQS 2
/* Features required from VirtIO */
@@ -365,7 +364,7 @@ static void vu_gpio_device_realize(DeviceState *dev, Error **errp)
qemu_chr_fe_set_handlers(&gpio->chardev, NULL, NULL, vu_gpio_event, NULL,
dev, NULL, true);
- retries = REALIZE_CONNECTION_RETRIES;
+ retries = VU_REALIZE_CONN_RETRIES;
g_assert(!*errp);
do {
if (*errp) {
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 69/78] vhost-user-scsi: support reconnect to backend
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (67 preceding siblings ...)
2023-10-19 18:24 ` [PULL v2 68/78] vhost: move and rename the conn retry times Michael S. Tsirkin
@ 2023-10-19 18:24 ` Michael S. Tsirkin
2023-10-19 18:24 ` [PULL v2 70/78] vhost-user-scsi: start vhost when guest kicks Michael S. Tsirkin
` (9 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:24 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Li Feng, Manos Pitsidianakis, Paolo Bonzini,
Fam Zheng, Raphael Norwitz
From: Li Feng <fengli@smartx.com>
If the backend crashes and restarts, the device is broken.
This patch adds reconnect for vhost-user-scsi.
This patch also improves the error messages, and reports some silent errors.
Tested with spdk backend.
Signed-off-by: Li Feng <fengli@smartx.com>
Message-Id: <20231009044735.941655-4-fengli@smartx.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
---
include/hw/virtio/vhost-scsi-common.h | 2 +-
include/hw/virtio/vhost-user-scsi.h | 6 +
hw/scsi/vhost-scsi-common.c | 16 +-
hw/scsi/vhost-scsi.c | 6 +-
hw/scsi/vhost-user-scsi.c | 201 +++++++++++++++++++++++---
5 files changed, 201 insertions(+), 30 deletions(-)
diff --git a/include/hw/virtio/vhost-scsi-common.h b/include/hw/virtio/vhost-scsi-common.h
index 18f115527c..c5d2c09455 100644
--- a/include/hw/virtio/vhost-scsi-common.h
+++ b/include/hw/virtio/vhost-scsi-common.h
@@ -39,7 +39,7 @@ struct VHostSCSICommon {
struct vhost_inflight *inflight;
};
-int vhost_scsi_common_start(VHostSCSICommon *vsc);
+int vhost_scsi_common_start(VHostSCSICommon *vsc, Error **errp);
void vhost_scsi_common_stop(VHostSCSICommon *vsc);
char *vhost_scsi_common_get_fw_dev_path(FWPathProvider *p, BusState *bus,
DeviceState *dev);
diff --git a/include/hw/virtio/vhost-user-scsi.h b/include/hw/virtio/vhost-user-scsi.h
index 521b08e559..78fe616ccb 100644
--- a/include/hw/virtio/vhost-user-scsi.h
+++ b/include/hw/virtio/vhost-user-scsi.h
@@ -28,7 +28,13 @@ OBJECT_DECLARE_SIMPLE_TYPE(VHostUserSCSI, VHOST_USER_SCSI)
struct VHostUserSCSI {
VHostSCSICommon parent_obj;
+
+ /* Properties */
+ bool connected;
+ bool started_vu;
+
VhostUserState vhost_user;
+ struct vhost_virtqueue *vhost_vqs;
};
#endif /* VHOST_USER_SCSI_H */
diff --git a/hw/scsi/vhost-scsi-common.c b/hw/scsi/vhost-scsi-common.c
index a61cd0e907..4c8637045d 100644
--- a/hw/scsi/vhost-scsi-common.c
+++ b/hw/scsi/vhost-scsi-common.c
@@ -16,6 +16,7 @@
*/
#include "qemu/osdep.h"
+#include "qapi/error.h"
#include "qemu/error-report.h"
#include "qemu/module.h"
#include "hw/virtio/vhost.h"
@@ -25,7 +26,7 @@
#include "hw/virtio/virtio-access.h"
#include "hw/fw-path-provider.h"
-int vhost_scsi_common_start(VHostSCSICommon *vsc)
+int vhost_scsi_common_start(VHostSCSICommon *vsc, Error **errp)
{
int ret, i;
VirtIODevice *vdev = VIRTIO_DEVICE(vsc);
@@ -35,18 +36,19 @@ int vhost_scsi_common_start(VHostSCSICommon *vsc)
VirtIOSCSICommon *vs = (VirtIOSCSICommon *)vsc;
if (!k->set_guest_notifiers) {
- error_report("binding does not support guest notifiers");
+ error_setg(errp, "binding does not support guest notifiers");
return -ENOSYS;
}
ret = vhost_dev_enable_notifiers(&vsc->dev, vdev);
if (ret < 0) {
+ error_setg_errno(errp, -ret, "Error enabling host notifiers");
return ret;
}
ret = k->set_guest_notifiers(qbus->parent, vsc->dev.nvqs, true);
if (ret < 0) {
- error_report("Error binding guest notifier");
+ error_setg_errno(errp, -ret, "Error binding guest notifier");
goto err_host_notifiers;
}
@@ -54,7 +56,7 @@ int vhost_scsi_common_start(VHostSCSICommon *vsc)
ret = vhost_dev_prepare_inflight(&vsc->dev, vdev);
if (ret < 0) {
- error_report("Error setting inflight format: %d", -ret);
+ error_setg_errno(errp, -ret, "Error setting inflight format");
goto err_guest_notifiers;
}
@@ -64,21 +66,21 @@ int vhost_scsi_common_start(VHostSCSICommon *vsc)
vs->conf.virtqueue_size,
vsc->inflight);
if (ret < 0) {
- error_report("Error getting inflight: %d", -ret);
+ error_setg_errno(errp, -ret, "Error getting inflight");
goto err_guest_notifiers;
}
}
ret = vhost_dev_set_inflight(&vsc->dev, vsc->inflight);
if (ret < 0) {
- error_report("Error setting inflight: %d", -ret);
+ error_setg_errno(errp, -ret, "Error setting inflight");
goto err_guest_notifiers;
}
}
ret = vhost_dev_start(&vsc->dev, vdev, true);
if (ret < 0) {
- error_report("Error start vhost dev");
+ error_setg_errno(errp, -ret, "Error starting vhost dev");
goto err_guest_notifiers;
}
diff --git a/hw/scsi/vhost-scsi.c b/hw/scsi/vhost-scsi.c
index 443f67daa4..95cadb93e7 100644
--- a/hw/scsi/vhost-scsi.c
+++ b/hw/scsi/vhost-scsi.c
@@ -75,6 +75,7 @@ static int vhost_scsi_start(VHostSCSI *s)
int ret, abi_version;
VHostSCSICommon *vsc = VHOST_SCSI_COMMON(s);
const VhostOps *vhost_ops = vsc->dev.vhost_ops;
+ Error *local_err = NULL;
ret = vhost_ops->vhost_scsi_get_abi_version(&vsc->dev, &abi_version);
if (ret < 0) {
@@ -88,14 +89,15 @@ static int vhost_scsi_start(VHostSCSI *s)
return -ENOSYS;
}
- ret = vhost_scsi_common_start(vsc);
+ ret = vhost_scsi_common_start(vsc, &local_err);
if (ret < 0) {
+ error_reportf_err(local_err, "Error starting vhost-scsi");
return ret;
}
ret = vhost_scsi_set_endpoint(s);
if (ret < 0) {
- error_report("Error setting vhost-scsi endpoint");
+ error_reportf_err(local_err, "Error setting vhost-scsi endpoint");
vhost_scsi_common_stop(vsc);
}
diff --git a/hw/scsi/vhost-user-scsi.c b/hw/scsi/vhost-user-scsi.c
index b7c6100f3e..24c250d3f8 100644
--- a/hw/scsi/vhost-user-scsi.c
+++ b/hw/scsi/vhost-user-scsi.c
@@ -39,26 +39,56 @@ static const int user_feature_bits[] = {
VHOST_INVALID_FEATURE_BIT
};
+static int vhost_user_scsi_start(VHostUserSCSI *s, Error **errp)
+{
+ VHostSCSICommon *vsc = VHOST_SCSI_COMMON(s);
+ int ret;
+
+ ret = vhost_scsi_common_start(vsc, errp);
+ s->started_vu = !(ret < 0);
+
+ return ret;
+}
+
+static void vhost_user_scsi_stop(VHostUserSCSI *s)
+{
+ VHostSCSICommon *vsc = VHOST_SCSI_COMMON(s);
+
+ if (!s->started_vu) {
+ return;
+ }
+ s->started_vu = false;
+
+ vhost_scsi_common_stop(vsc);
+}
+
static void vhost_user_scsi_set_status(VirtIODevice *vdev, uint8_t status)
{
VHostUserSCSI *s = (VHostUserSCSI *)vdev;
+ DeviceState *dev = DEVICE(vdev);
VHostSCSICommon *vsc = VHOST_SCSI_COMMON(s);
- bool start = (status & VIRTIO_CONFIG_S_DRIVER_OK) && vdev->vm_running;
+ VirtIOSCSICommon *vs = VIRTIO_SCSI_COMMON(dev);
+ bool should_start = virtio_device_should_start(vdev, status);
+ Error *local_err = NULL;
+ int ret;
- if (vhost_dev_is_started(&vsc->dev) == start) {
+ if (!s->connected) {
return;
}
- if (start) {
- int ret;
+ if (vhost_dev_is_started(&vsc->dev) == should_start) {
+ return;
+ }
- ret = vhost_scsi_common_start(vsc);
+ if (should_start) {
+ ret = vhost_user_scsi_start(s, &local_err);
if (ret < 0) {
- error_report("unable to start vhost-user-scsi: %s", strerror(-ret));
- exit(1);
+ error_reportf_err(local_err, "unable to start vhost-user-scsi: %s",
+ strerror(-ret));
+ qemu_chr_fe_disconnect(&vs->conf.chardev);
}
} else {
- vhost_scsi_common_stop(vsc);
+ vhost_user_scsi_stop(s);
}
}
@@ -66,14 +96,124 @@ static void vhost_dummy_handle_output(VirtIODevice *vdev, VirtQueue *vq)
{
}
+static int vhost_user_scsi_connect(DeviceState *dev, Error **errp)
+{
+ VirtIODevice *vdev = VIRTIO_DEVICE(dev);
+ VHostUserSCSI *s = VHOST_USER_SCSI(vdev);
+ VHostSCSICommon *vsc = VHOST_SCSI_COMMON(s);
+ VirtIOSCSICommon *vs = VIRTIO_SCSI_COMMON(dev);
+ int ret = 0;
+
+ if (s->connected) {
+ return 0;
+ }
+ s->connected = true;
+
+ vsc->dev.num_queues = vs->conf.num_queues;
+ vsc->dev.nvqs = VIRTIO_SCSI_VQ_NUM_FIXED + vs->conf.num_queues;
+ vsc->dev.vqs = s->vhost_vqs;
+ vsc->dev.vq_index = 0;
+ vsc->dev.backend_features = 0;
+
+ ret = vhost_dev_init(&vsc->dev, &s->vhost_user, VHOST_BACKEND_TYPE_USER, 0,
+ errp);
+ if (ret < 0) {
+ return ret;
+ }
+
+ /* restore vhost state */
+ if (virtio_device_started(vdev, vdev->status)) {
+ ret = vhost_user_scsi_start(s, errp);
+ }
+
+ return ret;
+}
+
+static void vhost_user_scsi_event(void *opaque, QEMUChrEvent event);
+
+static void vhost_user_scsi_disconnect(DeviceState *dev)
+{
+ VirtIODevice *vdev = VIRTIO_DEVICE(dev);
+ VHostUserSCSI *s = VHOST_USER_SCSI(vdev);
+ VHostSCSICommon *vsc = VHOST_SCSI_COMMON(s);
+ VirtIOSCSICommon *vs = VIRTIO_SCSI_COMMON(dev);
+
+ if (!s->connected) {
+ return;
+ }
+ s->connected = false;
+
+ vhost_user_scsi_stop(s);
+
+ vhost_dev_cleanup(&vsc->dev);
+
+ /* Re-instate the event handler for new connections */
+ qemu_chr_fe_set_handlers(&vs->conf.chardev, NULL, NULL,
+ vhost_user_scsi_event, NULL, dev, NULL, true);
+}
+
+static void vhost_user_scsi_event(void *opaque, QEMUChrEvent event)
+{
+ DeviceState *dev = opaque;
+ VirtIODevice *vdev = VIRTIO_DEVICE(dev);
+ VHostUserSCSI *s = VHOST_USER_SCSI(vdev);
+ VHostSCSICommon *vsc = VHOST_SCSI_COMMON(s);
+ VirtIOSCSICommon *vs = VIRTIO_SCSI_COMMON(dev);
+ Error *local_err = NULL;
+
+ switch (event) {
+ case CHR_EVENT_OPENED:
+ if (vhost_user_scsi_connect(dev, &local_err) < 0) {
+ error_report_err(local_err);
+ qemu_chr_fe_disconnect(&vs->conf.chardev);
+ return;
+ }
+ break;
+ case CHR_EVENT_CLOSED:
+ /* defer close until later to avoid circular close */
+ vhost_user_async_close(dev, &vs->conf.chardev, &vsc->dev,
+ vhost_user_scsi_disconnect);
+ break;
+ case CHR_EVENT_BREAK:
+ case CHR_EVENT_MUX_IN:
+ case CHR_EVENT_MUX_OUT:
+ /* Ignore */
+ break;
+ }
+}
+
+static int vhost_user_scsi_realize_connect(VHostUserSCSI *s, Error **errp)
+{
+ DeviceState *dev = DEVICE(s);
+ VirtIOSCSICommon *vs = VIRTIO_SCSI_COMMON(dev);
+ int ret;
+
+ s->connected = false;
+
+ ret = qemu_chr_fe_wait_connected(&vs->conf.chardev, errp);
+ if (ret < 0) {
+ return ret;
+ }
+
+ ret = vhost_user_scsi_connect(dev, errp);
+ if (ret < 0) {
+ qemu_chr_fe_disconnect(&vs->conf.chardev);
+ return ret;
+ }
+ assert(s->connected);
+
+ return 0;
+}
+
static void vhost_user_scsi_realize(DeviceState *dev, Error **errp)
{
+ ERRP_GUARD();
VirtIOSCSICommon *vs = VIRTIO_SCSI_COMMON(dev);
VHostUserSCSI *s = VHOST_USER_SCSI(dev);
VHostSCSICommon *vsc = VHOST_SCSI_COMMON(s);
- struct vhost_virtqueue *vqs = NULL;
Error *err = NULL;
int ret;
+ int retries = VU_REALIZE_CONN_RETRIES;
if (!vs->conf.chardev.chr) {
error_setg(errp, "vhost-user-scsi: missing chardev");
@@ -92,18 +232,28 @@ static void vhost_user_scsi_realize(DeviceState *dev, Error **errp)
goto free_virtio;
}
- vsc->dev.nvqs = VIRTIO_SCSI_VQ_NUM_FIXED + vs->conf.num_queues;
- vsc->dev.vqs = g_new0(struct vhost_virtqueue, vsc->dev.nvqs);
- vsc->dev.vq_index = 0;
- vsc->dev.backend_features = 0;
- vqs = vsc->dev.vqs;
+ vsc->inflight = g_new0(struct vhost_inflight, 1);
+ s->vhost_vqs = g_new0(struct vhost_virtqueue,
+ VIRTIO_SCSI_VQ_NUM_FIXED + vs->conf.num_queues);
+
+ assert(!*errp);
+ do {
+ if (*errp) {
+ error_prepend(errp, "Reconnecting after error: ");
+ error_report_err(*errp);
+ *errp = NULL;
+ }
+ ret = vhost_user_scsi_realize_connect(s, errp);
+ } while (ret < 0 && retries--);
- ret = vhost_dev_init(&vsc->dev, &s->vhost_user,
- VHOST_BACKEND_TYPE_USER, 0, errp);
if (ret < 0) {
goto free_vhost;
}
+ /* we're fully initialized, now we can operate, so add the handler */
+ qemu_chr_fe_set_handlers(&vs->conf.chardev, NULL, NULL,
+ vhost_user_scsi_event, NULL, (void *)dev,
+ NULL, true);
/* Channel and lun both are 0 for bootable vhost-user-scsi disk */
vsc->channel = 0;
vsc->lun = 0;
@@ -112,8 +262,12 @@ static void vhost_user_scsi_realize(DeviceState *dev, Error **errp)
return;
free_vhost:
+ g_free(s->vhost_vqs);
+ s->vhost_vqs = NULL;
+ g_free(vsc->inflight);
+ vsc->inflight = NULL;
vhost_user_cleanup(&s->vhost_user);
- g_free(vqs);
+
free_virtio:
virtio_scsi_common_unrealize(dev);
}
@@ -123,16 +277,23 @@ static void vhost_user_scsi_unrealize(DeviceState *dev)
VirtIODevice *vdev = VIRTIO_DEVICE(dev);
VHostUserSCSI *s = VHOST_USER_SCSI(dev);
VHostSCSICommon *vsc = VHOST_SCSI_COMMON(s);
- struct vhost_virtqueue *vqs = vsc->dev.vqs;
+ VirtIOSCSICommon *vs = VIRTIO_SCSI_COMMON(dev);
/* This will stop the vhost backend. */
vhost_user_scsi_set_status(vdev, 0);
+ qemu_chr_fe_set_handlers(&vs->conf.chardev, NULL, NULL, NULL, NULL, NULL,
+ NULL, false);
vhost_dev_cleanup(&vsc->dev);
- g_free(vqs);
+ g_free(s->vhost_vqs);
+ s->vhost_vqs = NULL;
+
+ vhost_dev_free_inflight(vsc->inflight);
+ g_free(vsc->inflight);
+ vsc->inflight = NULL;
- virtio_scsi_common_unrealize(dev);
vhost_user_cleanup(&s->vhost_user);
+ virtio_scsi_common_unrealize(dev);
}
static Property vhost_user_scsi_properties[] = {
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 70/78] vhost-user-scsi: start vhost when guest kicks
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (68 preceding siblings ...)
2023-10-19 18:24 ` [PULL v2 69/78] vhost-user-scsi: support reconnect to backend Michael S. Tsirkin
@ 2023-10-19 18:24 ` Michael S. Tsirkin
2023-10-19 18:24 ` [PULL v2 71/78] vhost-user: fix lost reconnect Michael S. Tsirkin
` (8 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:24 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Li Feng, Raphael Norwitz, Paolo Bonzini, Fam Zheng
From: Li Feng <fengli@smartx.com>
Let's keep the same behavior as vhost-user-blk.
Some old guests kick virtqueue before setting VIRTIO_CONFIG_S_DRIVER_OK.
Signed-off-by: Li Feng <fengli@smartx.com>
Reviewed-by: Raphael Norwitz <raphael.norwitz@nutanix.com>
Message-Id: <20231009044735.941655-5-fengli@smartx.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/scsi/vhost-user-scsi.c | 48 +++++++++++++++++++++++++++++++++++----
1 file changed, 44 insertions(+), 4 deletions(-)
diff --git a/hw/scsi/vhost-user-scsi.c b/hw/scsi/vhost-user-scsi.c
index 24c250d3f8..258fba5c69 100644
--- a/hw/scsi/vhost-user-scsi.c
+++ b/hw/scsi/vhost-user-scsi.c
@@ -92,8 +92,48 @@ static void vhost_user_scsi_set_status(VirtIODevice *vdev, uint8_t status)
}
}
-static void vhost_dummy_handle_output(VirtIODevice *vdev, VirtQueue *vq)
+static void vhost_user_scsi_handle_output(VirtIODevice *vdev, VirtQueue *vq)
{
+ VHostUserSCSI *s = (VHostUserSCSI *)vdev;
+ DeviceState *dev = DEVICE(vdev);
+ VHostSCSICommon *vsc = VHOST_SCSI_COMMON(s);
+ VirtIOSCSICommon *vs = VIRTIO_SCSI_COMMON(dev);
+
+ Error *local_err = NULL;
+ int i, ret;
+
+ if (!vdev->start_on_kick) {
+ return;
+ }
+
+ if (!s->connected) {
+ return;
+ }
+
+ if (vhost_dev_is_started(&vsc->dev)) {
+ return;
+ }
+
+ /*
+ * Some guests kick before setting VIRTIO_CONFIG_S_DRIVER_OK so start
+ * vhost here instead of waiting for .set_status().
+ */
+ ret = vhost_user_scsi_start(s, &local_err);
+ if (ret < 0) {
+ error_reportf_err(local_err, "vhost-user-scsi: vhost start failed: ");
+ qemu_chr_fe_disconnect(&vs->conf.chardev);
+ return;
+ }
+
+ /* Kick right away to begin processing requests already in vring */
+ for (i = 0; i < vsc->dev.nvqs; i++) {
+ VirtQueue *kick_vq = virtio_get_queue(vdev, i);
+
+ if (!virtio_queue_get_desc_addr(vdev, i)) {
+ continue;
+ }
+ event_notifier_set(virtio_queue_get_host_notifier(kick_vq));
+ }
}
static int vhost_user_scsi_connect(DeviceState *dev, Error **errp)
@@ -220,9 +260,9 @@ static void vhost_user_scsi_realize(DeviceState *dev, Error **errp)
return;
}
- virtio_scsi_common_realize(dev, vhost_dummy_handle_output,
- vhost_dummy_handle_output,
- vhost_dummy_handle_output, &err);
+ virtio_scsi_common_realize(dev, vhost_user_scsi_handle_output,
+ vhost_user_scsi_handle_output,
+ vhost_user_scsi_handle_output, &err);
if (err != NULL) {
error_propagate(errp, err);
return;
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 71/78] vhost-user: fix lost reconnect
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (69 preceding siblings ...)
2023-10-19 18:24 ` [PULL v2 70/78] vhost-user-scsi: start vhost when guest kicks Michael S. Tsirkin
@ 2023-10-19 18:24 ` Michael S. Tsirkin
2023-10-19 18:24 ` [PULL v2 72/78] hw/i386/cxl: ensure maxram is greater than ram size for calculating cxl range Michael S. Tsirkin
` (7 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:24 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Li Feng, Raphael Norwitz, Kevin Wolf, Hanna Reitz,
Paolo Bonzini, Fam Zheng, Alex Bennée, Viresh Kumar,
qemu-block
From: Li Feng <fengli@smartx.com>
When the vhost-user is reconnecting to the backend, and if the vhost-user fails
at the get_features in vhost_dev_init(), then the reconnect will fail
and it will not be retriggered forever.
The reason is:
When the vhost-user fails at get_features, the vhost_dev_cleanup will be called
immediately.
vhost_dev_cleanup calls 'memset(hdev, 0, sizeof(struct vhost_dev))'.
The reconnect path is:
vhost_user_blk_event
vhost_user_async_close(.. vhost_user_blk_disconnect ..)
qemu_chr_fe_set_handlers <----- clear the notifier callback
schedule vhost_user_async_close_bh
The vhost->vdev is null, so the vhost_user_blk_disconnect will not be
called, then the event fd callback will not be reinstalled.
All vhost-user devices have this issue, including vhost-user-blk/scsi.
With this patch, if the vdev->vdev is null, the fd callback will still
be reinstalled.
Fixes: 71e076a07d ("hw/virtio: generalise CHR_EVENT_CLOSED handling")
Signed-off-by: Li Feng <fengli@smartx.com>
Reviewed-by: Raphael Norwitz <raphael.norwitz@nutanix.com>
Message-Id: <20231009044735.941655-6-fengli@smartx.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
include/hw/virtio/vhost-user.h | 3 ++-
hw/block/vhost-user-blk.c | 2 +-
hw/scsi/vhost-user-scsi.c | 3 ++-
hw/virtio/vhost-user-gpio.c | 2 +-
hw/virtio/vhost-user.c | 10 ++++++++--
5 files changed, 14 insertions(+), 6 deletions(-)
diff --git a/include/hw/virtio/vhost-user.h b/include/hw/virtio/vhost-user.h
index 9f9ddf878d..6b06ecb1bd 100644
--- a/include/hw/virtio/vhost-user.h
+++ b/include/hw/virtio/vhost-user.h
@@ -106,6 +106,7 @@ typedef void (*vu_async_close_fn)(DeviceState *cb);
void vhost_user_async_close(DeviceState *d,
CharBackend *chardev, struct vhost_dev *vhost,
- vu_async_close_fn cb);
+ vu_async_close_fn cb,
+ IOEventHandler *event_cb);
#endif
diff --git a/hw/block/vhost-user-blk.c b/hw/block/vhost-user-blk.c
index 3c69fa47d5..95c758200d 100644
--- a/hw/block/vhost-user-blk.c
+++ b/hw/block/vhost-user-blk.c
@@ -391,7 +391,7 @@ static void vhost_user_blk_event(void *opaque, QEMUChrEvent event)
case CHR_EVENT_CLOSED:
/* defer close until later to avoid circular close */
vhost_user_async_close(dev, &s->chardev, &s->dev,
- vhost_user_blk_disconnect);
+ vhost_user_blk_disconnect, vhost_user_blk_event);
break;
case CHR_EVENT_BREAK:
case CHR_EVENT_MUX_IN:
diff --git a/hw/scsi/vhost-user-scsi.c b/hw/scsi/vhost-user-scsi.c
index 258fba5c69..4486500cac 100644
--- a/hw/scsi/vhost-user-scsi.c
+++ b/hw/scsi/vhost-user-scsi.c
@@ -212,7 +212,8 @@ static void vhost_user_scsi_event(void *opaque, QEMUChrEvent event)
case CHR_EVENT_CLOSED:
/* defer close until later to avoid circular close */
vhost_user_async_close(dev, &vs->conf.chardev, &vsc->dev,
- vhost_user_scsi_disconnect);
+ vhost_user_scsi_disconnect,
+ vhost_user_scsi_event);
break;
case CHR_EVENT_BREAK:
case CHR_EVENT_MUX_IN:
diff --git a/hw/virtio/vhost-user-gpio.c b/hw/virtio/vhost-user-gpio.c
index fc784e4213..aff2d7eff6 100644
--- a/hw/virtio/vhost-user-gpio.c
+++ b/hw/virtio/vhost-user-gpio.c
@@ -289,7 +289,7 @@ static void vu_gpio_event(void *opaque, QEMUChrEvent event)
case CHR_EVENT_CLOSED:
/* defer close until later to avoid circular close */
vhost_user_async_close(dev, &gpio->chardev, &gpio->vhost_dev,
- vu_gpio_disconnect);
+ vu_gpio_disconnect, vu_gpio_event);
break;
case CHR_EVENT_BREAK:
case CHR_EVENT_MUX_IN:
diff --git a/hw/virtio/vhost-user.c b/hw/virtio/vhost-user.c
index f9414f03de..b8a7b5542d 100644
--- a/hw/virtio/vhost-user.c
+++ b/hw/virtio/vhost-user.c
@@ -2756,6 +2756,7 @@ typedef struct {
DeviceState *dev;
CharBackend *cd;
struct vhost_dev *vhost;
+ IOEventHandler *event_cb;
} VhostAsyncCallback;
static void vhost_user_async_close_bh(void *opaque)
@@ -2770,7 +2771,10 @@ static void vhost_user_async_close_bh(void *opaque)
*/
if (vhost->vdev) {
data->cb(data->dev);
- }
+ } else if (data->event_cb) {
+ qemu_chr_fe_set_handlers(data->cd, NULL, NULL, data->event_cb,
+ NULL, data->dev, NULL, true);
+ }
g_free(data);
}
@@ -2782,7 +2786,8 @@ static void vhost_user_async_close_bh(void *opaque)
*/
void vhost_user_async_close(DeviceState *d,
CharBackend *chardev, struct vhost_dev *vhost,
- vu_async_close_fn cb)
+ vu_async_close_fn cb,
+ IOEventHandler *event_cb)
{
if (!runstate_check(RUN_STATE_SHUTDOWN)) {
/*
@@ -2798,6 +2803,7 @@ void vhost_user_async_close(DeviceState *d,
data->dev = d;
data->cd = chardev;
data->vhost = vhost;
+ data->event_cb = event_cb;
/* Disable any further notifications on the chardev */
qemu_chr_fe_set_handlers(chardev,
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 72/78] hw/i386/cxl: ensure maxram is greater than ram size for calculating cxl range
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (70 preceding siblings ...)
2023-10-19 18:24 ` [PULL v2 71/78] vhost-user: fix lost reconnect Michael S. Tsirkin
@ 2023-10-19 18:24 ` Michael S. Tsirkin
2023-10-19 18:24 ` [PULL v2 73/78] tests/acpi: Allow update of DSDT.cxl Michael S. Tsirkin
` (6 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:24 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Ani Sinha, Jonathan Cameron, Paolo Bonzini,
Richard Henderson, Eduardo Habkost, Marcel Apfelbaum
From: Ani Sinha <anisinha@redhat.com>
pc_get_device_memory_range() finds the device memory size by calculating the
difference between maxram and ram sizes. This calculation makes sense only when
maxram is greater than the ram size. Make sure we check for that before calling
pc_get_device_memory_range().
Signed-off-by: Ani Sinha <anisinha@redhat.com>
Message-Id: <20231011105335.42296-1-anisinha@redhat.com>
Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/i386/pc.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 6293f57a0c..dbaefa7617 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -781,10 +781,12 @@ static void pc_get_device_memory_range(PCMachineState *pcms,
static uint64_t pc_get_cxl_range_start(PCMachineState *pcms)
{
PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
+ MachineState *ms = MACHINE(pcms);
hwaddr cxl_base;
ram_addr_t size;
- if (pcmc->has_reserved_memory) {
+ if (pcmc->has_reserved_memory &&
+ (ms->ram_size < ms->maxram_size)) {
pc_get_device_memory_range(pcms, &cxl_base, &size);
cxl_base += size;
} else {
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 73/78] tests/acpi: Allow update of DSDT.cxl
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (71 preceding siblings ...)
2023-10-19 18:24 ` [PULL v2 72/78] hw/i386/cxl: ensure maxram is greater than ram size for calculating cxl range Michael S. Tsirkin
@ 2023-10-19 18:24 ` Michael S. Tsirkin
2023-10-19 18:24 ` [PULL v2 74/78] hw/cxl: Add QTG _DSM support for ACPI0017 device Michael S. Tsirkin
` (5 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:24 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Jonathan Cameron, Fan Ni, Dave Jiang,
Igor Mammedov, Ani Sinha
From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Addition of QTG in following patch requires an update to the test
data.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Fan Ni <fan.ni@samsung.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Message-Id: <20231012125623.21101-2-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..9ce0f596cc 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1 +1,2 @@
/* List of comma-separated changed AML files to ignore */
+"tests/data/acpi/q35/DSDT.cxl",
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 74/78] hw/cxl: Add QTG _DSM support for ACPI0017 device
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (72 preceding siblings ...)
2023-10-19 18:24 ` [PULL v2 73/78] tests/acpi: Allow update of DSDT.cxl Michael S. Tsirkin
@ 2023-10-19 18:24 ` Michael S. Tsirkin
2023-10-19 18:24 ` [PULL v2 75/78] tests/acpi: Update DSDT.cxl with QTG DSM Michael S. Tsirkin
` (4 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:24 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Dave Jiang, Jonathan Cameron, Igor Mammedov,
Ani Sinha, Paolo Bonzini, Richard Henderson, Eduardo Habkost,
Marcel Apfelbaum
From: Dave Jiang <dave.jiang@intel.com>
Add a simple _DSM call support for the ACPI0017 device to return fake QTG
ID values of 0 and 1 in all cases. This for _DSM plumbing testing from the OS.
Following edited for readability
Device (CXLM)
{
Name (_HID, "ACPI0017") // _HID: Hardware ID
...
Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method
{
If ((Arg0 == ToUUID ("f365f9a6-a7de-4071-a66a-b40c0b4f8e52")))
{
If ((Arg2 == Zero))
{
Return (Buffer (One) { 0x01 })
}
If ((Arg2 == One))
{
Return (Package (0x02)
{
One,
Package (0x02)
{
Zero,
One
}
})
}
}
}
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20231012125623.21101-3-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
include/hw/acpi/cxl.h | 1 +
hw/acpi/cxl.c | 69 +++++++++++++++++++++++++++++++++++++++++++
hw/i386/acpi-build.c | 1 +
3 files changed, 71 insertions(+)
diff --git a/include/hw/acpi/cxl.h b/include/hw/acpi/cxl.h
index acf4418886..8f22c71530 100644
--- a/include/hw/acpi/cxl.h
+++ b/include/hw/acpi/cxl.h
@@ -25,5 +25,6 @@ void cxl_build_cedt(GArray *table_offsets, GArray *table_data,
BIOSLinker *linker, const char *oem_id,
const char *oem_table_id, CXLState *cxl_state);
void build_cxl_osc_method(Aml *dev);
+void build_cxl_dsm_method(Aml *dev);
#endif
diff --git a/hw/acpi/cxl.c b/hw/acpi/cxl.c
index 92b46bc932..9cd7905ea2 100644
--- a/hw/acpi/cxl.c
+++ b/hw/acpi/cxl.c
@@ -30,6 +30,75 @@
#include "qapi/error.h"
#include "qemu/uuid.h"
+void build_cxl_dsm_method(Aml *dev)
+{
+ Aml *method, *ifctx, *ifctx2;
+
+ method = aml_method("_DSM", 4, AML_SERIALIZED);
+ {
+ Aml *function, *uuid;
+
+ uuid = aml_arg(0);
+ function = aml_arg(2);
+ /* CXL spec v3.0 9.17.3.1 _DSM Function for Retrieving QTG ID */
+ ifctx = aml_if(aml_equal(
+ uuid, aml_touuid("F365F9A6-A7DE-4071-A66A-B40C0B4F8E52")));
+
+ /* Function 0, standard DSM query function */
+ ifctx2 = aml_if(aml_equal(function, aml_int(0)));
+ {
+ uint8_t byte_list[1] = { 0x01 }; /* function 1 only */
+
+ aml_append(ifctx2,
+ aml_return(aml_buffer(sizeof(byte_list), byte_list)));
+ }
+ aml_append(ifctx, ifctx2);
+
+ /*
+ * Function 1
+ * Creating a package with static values. The max supported QTG ID will
+ * be 1 and recommended QTG IDs are 0 and then 1.
+ * The values here are statically created to simplify emulation. Values
+ * from a real BIOS would be determined by the performance of all the
+ * present CXL memory and then assigned.
+ */
+ ifctx2 = aml_if(aml_equal(function, aml_int(1)));
+ {
+ Aml *pak, *pak1;
+
+ /*
+ * Return: A package containing two elements - a WORD that returns
+ * the maximum throttling group that the platform supports, and a
+ * package containing the QTG ID(s) that the platform recommends.
+ * Package {
+ * Max Supported QTG ID
+ * Package {QTG Recommendations}
+ * }
+ *
+ * While the SPEC specified WORD that hints at the value being
+ * 16bit, the ACPI dump of BIOS DSDT table showed that the values
+ * are integers with no specific size specification. aml_int() will
+ * be used for the values.
+ */
+ pak1 = aml_package(2);
+ /* Set QTG ID of 0 */
+ aml_append(pak1, aml_int(0));
+ /* Set QTG ID of 1 */
+ aml_append(pak1, aml_int(1));
+
+ pak = aml_package(2);
+ /* Set Max QTG 1 */
+ aml_append(pak, aml_int(1));
+ aml_append(pak, pak1);
+
+ aml_append(ifctx2, aml_return(pak));
+ }
+ aml_append(ifctx, ifctx2);
+ }
+ aml_append(method, ifctx);
+ aml_append(dev, method);
+}
+
static void cedt_build_chbs(GArray *table_data, PXBCXLDev *cxl)
{
PXBDev *pxb = PXB_DEV(cxl);
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index b0e1f074f1..80db183b78 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -1417,6 +1417,7 @@ static void build_acpi0017(Aml *table)
method = aml_method("_STA", 0, AML_NOTSERIALIZED);
aml_append(method, aml_return(aml_int(0x01)));
aml_append(dev, method);
+ build_cxl_dsm_method(dev);
aml_append(scope, dev);
aml_append(table, scope);
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 75/78] tests/acpi: Update DSDT.cxl with QTG DSM
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (73 preceding siblings ...)
2023-10-19 18:24 ` [PULL v2 74/78] hw/cxl: Add QTG _DSM support for ACPI0017 device Michael S. Tsirkin
@ 2023-10-19 18:24 ` Michael S. Tsirkin
2023-10-19 18:24 ` [PULL v2 76/78] vhost-user: Fix protocol feature bit conflict Michael S. Tsirkin
` (3 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:24 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Jonathan Cameron, Fan Ni, Dave Jiang,
Igor Mammedov, Ani Sinha
From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Description of change in previous patch.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Fan Ni <fan.ni@samsung.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Message-Id: <20231012125623.21101-4-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 -
tests/data/acpi/q35/DSDT.cxl | Bin 9655 -> 9713 bytes
2 files changed, 1 deletion(-)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index 9ce0f596cc..dfb8523c8b 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1,2 +1 @@
/* List of comma-separated changed AML files to ignore */
-"tests/data/acpi/q35/DSDT.cxl",
diff --git a/tests/data/acpi/q35/DSDT.cxl b/tests/data/acpi/q35/DSDT.cxl
index ee16a861c2de7b7caaf11d91c50fcdf308815233..145301c52af9a17242bb306c210f8a7e0f01b827 100644
GIT binary patch
delta 118
zcmV-+0Ez#%OYutzL{mgm@g)EN0r#;Aks)191z%G_Ut5Ak1w&X&O$c8|Nkk1nLr_UD
zFflg(6bN5aR6ziw0Tef1L{m)+pfHnY5fcg!ruk*_-luUurfRed3r~(xpb3*|0HhHE
Y0Rf;6lWGB^5(okT5(EMOv%Vqu1A4<F)c^nh
delta 60
zcmez9z1^G3CD<ioyD9?%qu)lZiHgc9@xe~<(M__>5k9^g@gANoypGNRo(2Yn<_sbn
Q@xdXE3`;iuQ2faZ03i7h)c^nh
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 76/78] vhost-user: Fix protocol feature bit conflict
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (74 preceding siblings ...)
2023-10-19 18:24 ` [PULL v2 75/78] tests/acpi: Update DSDT.cxl with QTG DSM Michael S. Tsirkin
@ 2023-10-19 18:24 ` Michael S. Tsirkin
2023-10-19 18:24 ` [PULL v2 77/78] MAINTAINERS: Add include/hw/intc/i8259.h to the PC chip section Michael S. Tsirkin
` (2 subsequent siblings)
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:24 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Hanna Czenczek, Emmanouil Pitsidianakis,
Stefano Garzarella, Viresh Kumar, Stefan Hajnoczi
From: Hanna Czenczek <hreitz@redhat.com>
The VHOST_USER_PROTOCOL_F_XEN_MMAP feature bit was defined in
f21e95ee97d, which has been part of qemu's 8.1.0 release. However, it
seems it was never added to qemu's code, but it is well possible that it
is already used by different front-ends outside of qemu (i.e., Xen).
VHOST_USER_PROTOCOL_F_SHARED_OBJECT in contrast was added to qemu's code
in 16094766627, but never defined in the vhost-user specification. As a
consequence, both bits were defined to be 17, which cannot work.
Regardless of whether actual code or the specification should take
precedence, F_XEN_MMAP is already part of a qemu release, while
F_SHARED_OBJECT is not. Therefore, bump the latter to take number 18
instead of 17, and add this to the specification.
Take the opportunity to add at least a little note on the
VhostUserShared structure to the specification. This structure is
referenced by the new commands introduced in 16094766627, but was not
defined.
Fixes: 160947666276c5b7f6bca4d746bcac2966635d79
("vhost-user: add shared_object msg")
Signed-off-by: Hanna Czenczek <hreitz@redhat.com>
Message-Id: <20231016083201.23736-1-hreitz@redhat.com>
Reviewed-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
Reviewed-by: Stefano Garzarella <sgarzare@redhat.com>
Reviewed-by: Viresh Kumar <viresh.kumar@linaro.org>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
include/hw/virtio/vhost-user.h | 3 ++-
subprojects/libvhost-user/libvhost-user.h | 3 ++-
docs/interop/vhost-user.rst | 11 +++++++++++
3 files changed, 15 insertions(+), 2 deletions(-)
diff --git a/include/hw/virtio/vhost-user.h b/include/hw/virtio/vhost-user.h
index 6b06ecb1bd..20b69d8e85 100644
--- a/include/hw/virtio/vhost-user.h
+++ b/include/hw/virtio/vhost-user.h
@@ -29,7 +29,8 @@ enum VhostUserProtocolFeature {
VHOST_USER_PROTOCOL_F_INBAND_NOTIFICATIONS = 14,
VHOST_USER_PROTOCOL_F_CONFIGURE_MEM_SLOTS = 15,
VHOST_USER_PROTOCOL_F_STATUS = 16,
- VHOST_USER_PROTOCOL_F_SHARED_OBJECT = 17,
+ /* Feature 17 reserved for VHOST_USER_PROTOCOL_F_XEN_MMAP. */
+ VHOST_USER_PROTOCOL_F_SHARED_OBJECT = 18,
VHOST_USER_PROTOCOL_F_MAX
};
diff --git a/subprojects/libvhost-user/libvhost-user.h b/subprojects/libvhost-user/libvhost-user.h
index b36a42a7ca..c2352904f0 100644
--- a/subprojects/libvhost-user/libvhost-user.h
+++ b/subprojects/libvhost-user/libvhost-user.h
@@ -65,7 +65,8 @@ enum VhostUserProtocolFeature {
VHOST_USER_PROTOCOL_F_INBAND_NOTIFICATIONS = 14,
VHOST_USER_PROTOCOL_F_CONFIGURE_MEM_SLOTS = 15,
/* Feature 16 is reserved for VHOST_USER_PROTOCOL_F_STATUS. */
- VHOST_USER_PROTOCOL_F_SHARED_OBJECT = 17,
+ /* Feature 17 reserved for VHOST_USER_PROTOCOL_F_XEN_MMAP. */
+ VHOST_USER_PROTOCOL_F_SHARED_OBJECT = 18,
VHOST_USER_PROTOCOL_F_MAX
};
diff --git a/docs/interop/vhost-user.rst b/docs/interop/vhost-user.rst
index 415bb47a19..768fb5c28c 100644
--- a/docs/interop/vhost-user.rst
+++ b/docs/interop/vhost-user.rst
@@ -275,6 +275,16 @@ Inflight description
:queue size: a 16-bit size of virtqueues
+VhostUserShared
+^^^^^^^^^^^^^^^
+
++------+
+| UUID |
++------+
+
+:UUID: 16 bytes UUID, whose first three components (a 32-bit value, then
+ two 16-bit values) are stored in big endian.
+
C structure
-----------
@@ -885,6 +895,7 @@ Protocol features
#define VHOST_USER_PROTOCOL_F_CONFIGURE_MEM_SLOTS 15
#define VHOST_USER_PROTOCOL_F_STATUS 16
#define VHOST_USER_PROTOCOL_F_XEN_MMAP 17
+ #define VHOST_USER_PROTOCOL_F_SHARED_OBJECT 18
Front-end message types
-----------------------
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 77/78] MAINTAINERS: Add include/hw/intc/i8259.h to the PC chip section
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (75 preceding siblings ...)
2023-10-19 18:24 ` [PULL v2 76/78] vhost-user: Fix protocol feature bit conflict Michael S. Tsirkin
@ 2023-10-19 18:24 ` Michael S. Tsirkin
2023-10-19 18:24 ` [PULL v2 78/78] intel-iommu: Report interrupt remapping faults, fix return value Michael S. Tsirkin
2023-10-20 16:00 ` [PULL v2 00/78] virtio,pc,pci: features, cleanups Stefan Hajnoczi
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:24 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Thomas Huth, Philippe Mathieu-Daudé,
Richard Henderson, Alex Bennée
From: Thomas Huth <thuth@redhat.com>
i8259.c is already listed here, so the corresponding header should
be mentioned in this section, too.
Signed-off-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20231017152625.229022-1-thuth@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index d9fe5aa367..2f435102ec 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1764,6 +1764,7 @@ F: include/hw/dma/i8257.h
F: include/hw/i2c/pm_smbus.h
F: include/hw/input/i8042.h
F: include/hw/intc/ioapic*
+F: include/hw/intc/i8259.h
F: include/hw/isa/i8259_internal.h
F: include/hw/isa/superio.h
F: include/hw/timer/hpet.h
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PULL v2 78/78] intel-iommu: Report interrupt remapping faults, fix return value
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (76 preceding siblings ...)
2023-10-19 18:24 ` [PULL v2 77/78] MAINTAINERS: Add include/hw/intc/i8259.h to the PC chip section Michael S. Tsirkin
@ 2023-10-19 18:24 ` Michael S. Tsirkin
2023-10-20 16:00 ` [PULL v2 00/78] virtio,pc,pci: features, cleanups Stefan Hajnoczi
78 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-19 18:24 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, David Woodhouse, Peter Xu, Jason Wang,
Marcel Apfelbaum, Paolo Bonzini, Richard Henderson,
Eduardo Habkost
From: David Woodhouse <dwmw@amazon.co.uk>
A generic X86IOMMUClass->int_remap function should not return VT-d
specific values; fix it to return 0 if the interrupt was successfully
translated or -EINVAL if not.
The VTD_FR_IR_xxx values are supposed to be used to actually raise
faults through the fault reporting mechanism, so do that instead for
the case where the IRQ is actually being injected.
There is more work to be done here, as pretranslations for the KVM IRQ
routing table can't fault; an untranslatable IRQ should be handled in
userspace and the fault raised only when the IRQ actually happens (if
indeed the IRTE is still not valid at that time). But we can work on
that later; we can at least raise faults for the direct case.
Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Message-Id: <31bbfc9041690449d3ac891f4431ec82174ee1b4.camel@infradead.org>
Acked-by: Peter Xu <peterx@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/i386/intel_iommu_internal.h | 1 +
hw/i386/intel_iommu.c | 150 ++++++++++++++++++++++-----------
2 files changed, 103 insertions(+), 48 deletions(-)
diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
index e1450c5cfe..f8cf99bddf 100644
--- a/hw/i386/intel_iommu_internal.h
+++ b/hw/i386/intel_iommu_internal.h
@@ -268,6 +268,7 @@
#define VTD_FRCD_FI(val) ((val) & ~0xfffULL)
#define VTD_FRCD_PV(val) (((val) & 0xffffULL) << 40)
#define VTD_FRCD_PP(val) (((val) & 0x1) << 31)
+#define VTD_FRCD_IR_IDX(val) (((val) & 0xffffULL) << 48)
/* DMA Remapping Fault Conditions */
typedef enum VTDFaultReason {
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 2c832ab68b..30a108a42b 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -469,21 +469,12 @@ static void vtd_set_frcd_and_update_ppf(IntelIOMMUState *s, uint16_t index)
/* Must not update F field now, should be done later */
static void vtd_record_frcd(IntelIOMMUState *s, uint16_t index,
- uint16_t source_id, hwaddr addr,
- VTDFaultReason fault, bool is_write,
- bool is_pasid, uint32_t pasid)
+ uint64_t hi, uint64_t lo)
{
- uint64_t hi = 0, lo;
hwaddr frcd_reg_addr = DMAR_FRCD_REG_OFFSET + (((uint64_t)index) << 4);
assert(index < DMAR_FRCD_REG_NR);
- lo = VTD_FRCD_FI(addr);
- hi = VTD_FRCD_SID(source_id) | VTD_FRCD_FR(fault) |
- VTD_FRCD_PV(pasid) | VTD_FRCD_PP(is_pasid);
- if (!is_write) {
- hi |= VTD_FRCD_T;
- }
vtd_set_quad_raw(s, frcd_reg_addr, lo);
vtd_set_quad_raw(s, frcd_reg_addr + 8, hi);
@@ -509,17 +500,11 @@ static bool vtd_try_collapse_fault(IntelIOMMUState *s, uint16_t source_id)
}
/* Log and report an DMAR (address translation) fault to software */
-static void vtd_report_dmar_fault(IntelIOMMUState *s, uint16_t source_id,
- hwaddr addr, VTDFaultReason fault,
- bool is_write, bool is_pasid,
- uint32_t pasid)
+static void vtd_report_frcd_fault(IntelIOMMUState *s, uint64_t source_id,
+ uint64_t hi, uint64_t lo)
{
uint32_t fsts_reg = vtd_get_long_raw(s, DMAR_FSTS_REG);
- assert(fault < VTD_FR_MAX);
-
- trace_vtd_dmar_fault(source_id, fault, addr, is_write);
-
if (fsts_reg & VTD_FSTS_PFO) {
error_report_once("New fault is not recorded due to "
"Primary Fault Overflow");
@@ -539,8 +524,7 @@ static void vtd_report_dmar_fault(IntelIOMMUState *s, uint16_t source_id,
return;
}
- vtd_record_frcd(s, s->next_frcd_reg, source_id, addr, fault,
- is_write, is_pasid, pasid);
+ vtd_record_frcd(s, s->next_frcd_reg, hi, lo);
if (fsts_reg & VTD_FSTS_PPF) {
error_report_once("There are pending faults already, "
@@ -565,6 +549,40 @@ static void vtd_report_dmar_fault(IntelIOMMUState *s, uint16_t source_id,
}
}
+/* Log and report an DMAR (address translation) fault to software */
+static void vtd_report_dmar_fault(IntelIOMMUState *s, uint16_t source_id,
+ hwaddr addr, VTDFaultReason fault,
+ bool is_write, bool is_pasid,
+ uint32_t pasid)
+{
+ uint64_t hi, lo;
+
+ assert(fault < VTD_FR_MAX);
+
+ trace_vtd_dmar_fault(source_id, fault, addr, is_write);
+
+ lo = VTD_FRCD_FI(addr);
+ hi = VTD_FRCD_SID(source_id) | VTD_FRCD_FR(fault) |
+ VTD_FRCD_PV(pasid) | VTD_FRCD_PP(is_pasid);
+ if (!is_write) {
+ hi |= VTD_FRCD_T;
+ }
+
+ vtd_report_frcd_fault(s, source_id, hi, lo);
+}
+
+
+static void vtd_report_ir_fault(IntelIOMMUState *s, uint64_t source_id,
+ VTDFaultReason fault, uint16_t index)
+{
+ uint64_t hi, lo;
+
+ lo = VTD_FRCD_IR_IDX(index);
+ hi = VTD_FRCD_SID(source_id) | VTD_FRCD_FR(fault);
+
+ vtd_report_frcd_fault(s, source_id, hi, lo);
+}
+
/* Handle Invalidation Queue Errors of queued invalidation interface error
* conditions.
*/
@@ -3305,8 +3323,9 @@ static Property vtd_properties[] = {
};
/* Read IRTE entry with specific index */
-static int vtd_irte_get(IntelIOMMUState *iommu, uint16_t index,
- VTD_IR_TableEntry *entry, uint16_t sid)
+static bool vtd_irte_get(IntelIOMMUState *iommu, uint16_t index,
+ VTD_IR_TableEntry *entry, uint16_t sid,
+ bool do_fault)
{
static const uint16_t vtd_svt_mask[VTD_SQ_MAX] = \
{0xffff, 0xfffb, 0xfff9, 0xfff8};
@@ -3317,7 +3336,10 @@ static int vtd_irte_get(IntelIOMMUState *iommu, uint16_t index,
if (index >= iommu->intr_size) {
error_report_once("%s: index too large: ind=0x%x",
__func__, index);
- return -VTD_FR_IR_INDEX_OVER;
+ if (do_fault) {
+ vtd_report_ir_fault(iommu, sid, VTD_FR_IR_INDEX_OVER, index);
+ }
+ return false;
}
addr = iommu->intr_root + index * sizeof(*entry);
@@ -3325,7 +3347,10 @@ static int vtd_irte_get(IntelIOMMUState *iommu, uint16_t index,
entry, sizeof(*entry), MEMTXATTRS_UNSPECIFIED)) {
error_report_once("%s: read failed: ind=0x%x addr=0x%" PRIx64,
__func__, index, addr);
- return -VTD_FR_IR_ROOT_INVAL;
+ if (do_fault) {
+ vtd_report_ir_fault(iommu, sid, VTD_FR_IR_ROOT_INVAL, index);
+ }
+ return false;
}
entry->data[0] = le64_to_cpu(entry->data[0]);
@@ -3333,11 +3358,24 @@ static int vtd_irte_get(IntelIOMMUState *iommu, uint16_t index,
trace_vtd_ir_irte_get(index, entry->data[1], entry->data[0]);
+ /*
+ * The remaining potential fault conditions are "qualified" by the
+ * Fault Processing Disable bit in the IRTE. Even "not present".
+ * So just clear the do_fault flag if PFD is set, which will
+ * prevent faults being raised.
+ */
+ if (entry->irte.fault_disable) {
+ do_fault = false;
+ }
+
if (!entry->irte.present) {
error_report_once("%s: detected non-present IRTE "
"(index=%u, high=0x%" PRIx64 ", low=0x%" PRIx64 ")",
__func__, index, entry->data[1], entry->data[0]);
- return -VTD_FR_IR_ENTRY_P;
+ if (do_fault) {
+ vtd_report_ir_fault(iommu, sid, VTD_FR_IR_ENTRY_P, index);
+ }
+ return false;
}
if (entry->irte.__reserved_0 || entry->irte.__reserved_1 ||
@@ -3345,7 +3383,10 @@ static int vtd_irte_get(IntelIOMMUState *iommu, uint16_t index,
error_report_once("%s: detected non-zero reserved IRTE "
"(index=%u, high=0x%" PRIx64 ", low=0x%" PRIx64 ")",
__func__, index, entry->data[1], entry->data[0]);
- return -VTD_FR_IR_IRTE_RSVD;
+ if (do_fault) {
+ vtd_report_ir_fault(iommu, sid, VTD_FR_IR_IRTE_RSVD, index);
+ }
+ return false;
}
if (sid != X86_IOMMU_SID_INVALID) {
@@ -3361,7 +3402,10 @@ static int vtd_irte_get(IntelIOMMUState *iommu, uint16_t index,
error_report_once("%s: invalid IRTE SID "
"(index=%u, sid=%u, source_id=%u)",
__func__, index, sid, source_id);
- return -VTD_FR_IR_SID_ERR;
+ if (do_fault) {
+ vtd_report_ir_fault(iommu, sid, VTD_FR_IR_SID_ERR, index);
+ }
+ return false;
}
break;
@@ -3373,7 +3417,10 @@ static int vtd_irte_get(IntelIOMMUState *iommu, uint16_t index,
error_report_once("%s: invalid SVT_BUS "
"(index=%u, bus=%u, min=%u, max=%u)",
__func__, index, bus, bus_min, bus_max);
- return -VTD_FR_IR_SID_ERR;
+ if (do_fault) {
+ vtd_report_ir_fault(iommu, sid, VTD_FR_IR_SID_ERR, index);
+ }
+ return false;
}
break;
@@ -3382,23 +3429,24 @@ static int vtd_irte_get(IntelIOMMUState *iommu, uint16_t index,
"(index=%u, type=%d)", __func__,
index, entry->irte.sid_vtype);
/* Take this as verification failure. */
- return -VTD_FR_IR_SID_ERR;
+ if (do_fault) {
+ vtd_report_ir_fault(iommu, sid, VTD_FR_IR_SID_ERR, index);
+ }
+ return false;
}
}
- return 0;
+ return true;
}
/* Fetch IRQ information of specific IR index */
-static int vtd_remap_irq_get(IntelIOMMUState *iommu, uint16_t index,
- X86IOMMUIrq *irq, uint16_t sid)
+static bool vtd_remap_irq_get(IntelIOMMUState *iommu, uint16_t index,
+ X86IOMMUIrq *irq, uint16_t sid, bool do_fault)
{
VTD_IR_TableEntry irte = {};
- int ret = 0;
- ret = vtd_irte_get(iommu, index, &irte, sid);
- if (ret) {
- return ret;
+ if (!vtd_irte_get(iommu, index, &irte, sid, do_fault)) {
+ return false;
}
irq->trigger_mode = irte.irte.trigger_mode;
@@ -3417,16 +3465,15 @@ static int vtd_remap_irq_get(IntelIOMMUState *iommu, uint16_t index,
trace_vtd_ir_remap(index, irq->trigger_mode, irq->vector,
irq->delivery_mode, irq->dest, irq->dest_mode);
- return 0;
+ return true;
}
/* Interrupt remapping for MSI/MSI-X entry */
static int vtd_interrupt_remap_msi(IntelIOMMUState *iommu,
MSIMessage *origin,
MSIMessage *translated,
- uint16_t sid)
+ uint16_t sid, bool do_fault)
{
- int ret = 0;
VTD_IR_MSIAddress addr;
uint16_t index;
X86IOMMUIrq irq = {};
@@ -3443,14 +3490,20 @@ static int vtd_interrupt_remap_msi(IntelIOMMUState *iommu,
if (origin->address & VTD_MSI_ADDR_HI_MASK) {
error_report_once("%s: MSI address high 32 bits non-zero detected: "
"address=0x%" PRIx64, __func__, origin->address);
- return -VTD_FR_IR_REQ_RSVD;
+ if (do_fault) {
+ vtd_report_ir_fault(iommu, sid, VTD_FR_IR_REQ_RSVD, 0);
+ }
+ return -EINVAL;
}
addr.data = origin->address & VTD_MSI_ADDR_LO_MASK;
if (addr.addr.__head != 0xfee) {
error_report_once("%s: MSI address low 32 bit invalid: 0x%" PRIx32,
__func__, addr.data);
- return -VTD_FR_IR_REQ_RSVD;
+ if (do_fault) {
+ vtd_report_ir_fault(iommu, sid, VTD_FR_IR_REQ_RSVD, 0);
+ }
+ return -EINVAL;
}
/* This is compatible mode. */
@@ -3469,9 +3522,8 @@ static int vtd_interrupt_remap_msi(IntelIOMMUState *iommu,
index += origin->data & VTD_IR_MSI_DATA_SUBHANDLE;
}
- ret = vtd_remap_irq_get(iommu, index, &irq, sid);
- if (ret) {
- return ret;
+ if (!vtd_remap_irq_get(iommu, index, &irq, sid, do_fault)) {
+ return -EINVAL;
}
if (addr.addr.sub_valid) {
@@ -3481,7 +3533,10 @@ static int vtd_interrupt_remap_msi(IntelIOMMUState *iommu,
"(sid=%u, address=0x%" PRIx64
", data=0x%" PRIx32 ")",
__func__, sid, origin->address, origin->data);
- return -VTD_FR_IR_REQ_RSVD;
+ if (do_fault) {
+ vtd_report_ir_fault(iommu, sid, VTD_FR_IR_REQ_RSVD, 0);
+ }
+ return -EINVAL;
}
} else {
uint8_t vector = origin->data & 0xff;
@@ -3521,7 +3576,7 @@ static int vtd_int_remap(X86IOMMUState *iommu, MSIMessage *src,
MSIMessage *dst, uint16_t sid)
{
return vtd_interrupt_remap_msi(INTEL_IOMMU_DEVICE(iommu),
- src, dst, sid);
+ src, dst, sid, false);
}
static MemTxResult vtd_mem_ir_read(void *opaque, hwaddr addr,
@@ -3547,9 +3602,8 @@ static MemTxResult vtd_mem_ir_write(void *opaque, hwaddr addr,
sid = attrs.requester_id;
}
- ret = vtd_interrupt_remap_msi(opaque, &from, &to, sid);
+ ret = vtd_interrupt_remap_msi(opaque, &from, &to, sid, true);
if (ret) {
- /* TODO: report error */
/* Drop this interrupt */
return MEMTX_ERROR;
}
--
MST
^ permalink raw reply related [flat|nested] 81+ messages in thread* Re: [PULL v2 00/78] virtio,pc,pci: features, cleanups
2023-10-19 18:24 [PULL v2 00/78] virtio,pc,pci: features, cleanups Michael S. Tsirkin
` (77 preceding siblings ...)
2023-10-19 18:24 ` [PULL v2 78/78] intel-iommu: Report interrupt remapping faults, fix return value Michael S. Tsirkin
@ 2023-10-20 16:00 ` Stefan Hajnoczi
2023-10-23 11:38 ` Michael S. Tsirkin
78 siblings, 1 reply; 81+ messages in thread
From: Stefan Hajnoczi @ 2023-10-20 16:00 UTC (permalink / raw)
To: Michael S. Tsirkin; +Cc: qemu-devel, Peter Maydell
On Thu, 19 Oct 2023 at 11:30, Michael S. Tsirkin <mst@redhat.com> wrote:
>
> Changes from v1:
> dropped shadow vq patches
>
> The following changes since commit ec6f9f135d5e5596ab0258da2ddd048f1fd8c359:
>
> Merge tag 'migration-20231017-pull-request' of https://gitlab.com/juan.quintela/qemu into staging (2023-10-17 10:06:21 -0400)
>
> are available in the Git repository at:
>
> https://git.kernel.org/pub/scm/virt/kvm/mst/qemu.git tags/for_upstream
>
> for you to fetch changes up to 16ef005ba922d5af498e9f0f2ee6b29a318821a8:
>
> intel-iommu: Report interrupt remapping faults, fix return value (2023-10-19 14:11:17 -0400)
>
> ----------------------------------------------------------------
> virtio,pc,pci: features, cleanups
>
> infrastructure for vhost-vdpa shadow work
> piix south bridge rework
> reconnect for vhost-user-scsi
> dummy ACPI QTG DSM for cxl
>
> tests, cleanups, fixes all over the place
>
> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
>
Hi Michael,
I think the following bios-tables-test failure is caused by this pull request:
>>> MALLOC_PERTURB_=158 QTEST_QEMU_IMG=./qemu-img QTEST_QEMU_BINARY=./qemu-system-x86_64 G_TEST_DBUS_DAEMON=/builds/qemu-project/qemu/tests/dbus-vmstate-daemon.sh QTEST_QEMU_STORAGE_DAEMON_BINARY=./storage-daemon/qemu-storage-daemon PYTHON=/builds/qemu-project/qemu/build/pyvenv/bin/python3.8 /builds/qemu-project/qemu/build/tests/qtest/bios-tables-test --tap -k
――――――――――――――――――――――――――――――――――――― ✀ ―――――――――――――――――――――――――――――――――――――
stderr:
qemu-system-x86_64: -accel kvm: warning: Number of SMP cpus requested
(260) exceeds the recommended cpus supported by KVM (240)
qemu-system-x86_64: -accel kvm: warning: Number of hotpluggable cpus
requested (260) exceeds the recommended cpus supported by KVM (240)
qemu-system-x86_64: -accel kvm: warning: Number of hotpluggable cpus
requested (520) exceeds the recommended cpus supported by KVM (240)
Number of hotpluggable cpus requested (520) exceeds the maximum cpus
supported by KVM (288)
socket_accept failed: Resource temporarily unavailable
**
ERROR:../tests/qtest/libqtest.c:496:qtest_init_internal: assertion
failed: (s->fd >= 0 && s->qmp_fd >= 0)
../tests/qtest/libqtest.c:195: kill_qemu() tried to terminate QEMU
process but encountered exit status 1 (expected 0)
(test program exited with status code -6)
https://gitlab.com/qemu-project/qemu/-/jobs/5338513625
Please take a look. Thanks!
Stefan
> ----------------------------------------------------------------
> Ani Sinha (1):
> hw/i386/cxl: ensure maxram is greater than ram size for calculating cxl range
>
> Bernhard Beschow (30):
> hw/i386/acpi-build: Remove build-time assertion on PIIX/ICH9 reset registers being identical
> hw/i386/pc: Merge two if statements into one
> hw/i386/pc_piix: Allow for setting properties before realizing PIIX3 south bridge
> hw/i386/pc_piix: Assign PIIX3's ISA interrupts before its realize()
> hw/isa/piix3: Resolve redundant PIIX_NUM_PIC_IRQS
> hw/i386/pc_piix: Wire PIIX3's ISA interrupts by new "isa-irqs" property
> hw/i386/pc_piix: Remove redundant "piix3" variable
> hw/isa/piix3: Rename "pic" attribute to "isa_irqs_in"
> hw/i386/pc_q35: Wire ICH9 LPC function's interrupts before its realize()
> hw/isa/piix3: Wire PIC IRQs to ISA bus in host device
> hw/i386/pc: Wire RTC ISA IRQs in south bridges
> hw/isa/piix3: Create IDE controller in host device
> hw/isa/piix3: Create USB controller in host device
> hw/isa/piix3: Create power management controller in host device
> hw/isa/piix3: Drop the "3" from PIIX base class name
> hw/isa/piix4: Remove unused inbound ISA interrupt lines
> hw/isa/piix4: Rename "isa" attribute to "isa_irqs_in"
> hw/isa/piix4: Rename reset control operations to match PIIX3
> hw/isa/piix4: Reuse struct PIIXState from PIIX3
> hw/isa/piix3: Merge hw/isa/piix4.c
> hw/isa/piix: Allow for optional PIC creation in PIIX3
> hw/isa/piix: Allow for optional PIT creation in PIIX3
> hw/isa/piix: Harmonize names of reset control memory regions
> hw/isa/piix: Share PIIX3's base class with PIIX4
> hw/isa/piix: Reuse PIIX3 base class' realize method in PIIX4
> hw/isa/piix: Rename functions to be shared for PCI interrupt triggering
> hw/isa/piix: Reuse PIIX3's PCI interrupt triggering in PIIX4
> hw/isa/piix: Resolve duplicate code regarding PCI interrupt wiring
> hw/isa/piix: Implement multi-process QEMU support also for PIIX4
> hw/i386/pc_piix: Make PIIX4 south bridge usable in PC machine
>
> Damien Zammit (1):
> timer/i8254: Fix one shot PIT mode
>
> Dave Jiang (1):
> hw/cxl: Add QTG _DSM support for ACPI0017 device
>
> David Woodhouse (1):
> intel-iommu: Report interrupt remapping faults, fix return value
>
> Hanna Czenczek (1):
> vhost-user: Fix protocol feature bit conflict
>
> Hawkins Jiawei (7):
> vdpa: Use iovec for vhost_vdpa_net_cvq_add()
> vdpa: Avoid using vhost_vdpa_net_load_*() outside vhost_vdpa_net_load()
> vdpa: Check device ack in vhost_vdpa_net_load_rx_mode()
> vdpa: Move vhost_svq_poll() to the caller of vhost_vdpa_net_cvq_add()
> vdpa: Introduce cursors to vhost_vdpa_net_loadx()
> vhost: Expose vhost_svq_available_slots()
> vdpa: Send cvq state load commands in parallel
>
> Ilya Maximets (1):
> memory: initialize 'fv' in MemoryRegionCache to make Coverity happy
>
> Jonathan Cameron (2):
> tests/acpi: Allow update of DSDT.cxl
> tests/acpi: Update DSDT.cxl with QTG DSM
>
> Laszlo Ersek (7):
> vhost-user: strip superfluous whitespace
> vhost-user: tighten "reply_supported" scope in "set_vring_addr"
> vhost-user: factor out "vhost_user_write_sync"
> vhost-user: flatten "enforce_reply" into "vhost_user_write_sync"
> vhost-user: hoist "write_sync", "get_features", "get_u64"
> vhost-user: allow "vhost_set_vring" to wait for a reply
> vhost-user: call VHOST_USER_SET_VRING_ENABLE synchronously
>
> Li Feng (5):
> vhost-user-common: send get_inflight_fd once
> vhost: move and rename the conn retry times
> vhost-user-scsi: support reconnect to backend
> vhost-user-scsi: start vhost when guest kicks
> vhost-user: fix lost reconnect
>
> Matheus Tavares Bernardino (1):
> hw/display: fix memleak from virtio_add_resource
>
> Stefan Hajnoczi (3):
> vhost-user: do not send RESET_OWNER on device reset
> vhost-backend: remove vhost_kernel_reset_device()
> virtio: call ->vhost_reset_device() during reset
>
> Thomas Huth (1):
> MAINTAINERS: Add include/hw/intc/i8259.h to the PC chip section
>
> Zhao Liu (16):
> tests: test-smp-parse: Add the test for cores/threads per socket helpers
> tests: bios-tables-test: Prepare the ACPI table change for smbios type4 count test
> tests: bios-tables-test: Add test for smbios type4 count
> tests: bios-tables-test: Add ACPI table binaries for smbios type4 count test
> tests: bios-tables-test: Prepare the ACPI table change for smbios type4 core count test
> tests: bios-tables-test: Add test for smbios type4 core count
> tests: bios-tables-test: Add ACPI table binaries for smbios type4 core count test
> tests: bios-tables-test: Prepare the ACPI table change for smbios type4 core count2 test
> tests: bios-tables-test: Extend smbios core count2 test to cover general topology
> tests: bios-tables-test: Update ACPI table binaries for smbios core count2 test
> tests: bios-tables-test: Prepare the ACPI table change for smbios type4 thread count test
> tests: bios-tables-test: Add test for smbios type4 thread count
> tests: bios-tables-test: Add ACPI table binaries for smbios type4 thread count test
> tests: bios-tables-test: Prepare the ACPI table change for smbios type4 thread count2 test
> tests: bios-tables-test: Add test for smbios type4 thread count2
> tests: bios-tables-test: Add ACPI table binaries for smbios type4 thread count2 test
>
> hw/i386/intel_iommu_internal.h | 1 +
> hw/virtio/vhost-shadow-virtqueue.h | 1 +
> include/exec/memory.h | 2 +
> include/hw/acpi/cxl.h | 1 +
> include/hw/i386/pc.h | 2 +
> include/hw/southbridge/piix.h | 30 ++-
> include/hw/virtio/vhost-scsi-common.h | 2 +-
> include/hw/virtio/vhost-user-scsi.h | 6 +
> include/hw/virtio/vhost-user.h | 6 +-
> include/hw/virtio/vhost.h | 12 +
> subprojects/libvhost-user/libvhost-user.h | 3 +-
> hw/acpi/cxl.c | 69 ++++++
> hw/block/vhost-user-blk.c | 6 +-
> hw/display/virtio-dmabuf.c | 12 +-
> hw/i386/acpi-build.c | 6 +-
> hw/i386/intel_iommu.c | 150 ++++++++----
> hw/i386/pc.c | 19 +-
> hw/i386/pc_piix.c | 123 +++++++---
> hw/i386/pc_q35.c | 14 +-
> hw/isa/lpc_ich9.c | 9 +-
> hw/isa/{piix3.c => piix.c} | 281 ++++++++++++++++------
> hw/isa/piix4.c | 302 ------------------------
> hw/mips/malta.c | 5 +-
> hw/scsi/vhost-scsi-common.c | 47 ++--
> hw/scsi/vhost-scsi.c | 6 +-
> hw/scsi/vhost-user-scsi.c | 254 +++++++++++++++++---
> hw/timer/i8254_common.c | 4 +-
> hw/virtio/vhost-backend.c | 6 -
> hw/virtio/vhost-shadow-virtqueue.c | 2 +-
> hw/virtio/vhost-user-gpio.c | 5 +-
> hw/virtio/vhost-user.c | 239 ++++++++++---------
> hw/virtio/vhost.c | 9 +
> hw/virtio/virtio.c | 4 +
> net/vhost-vdpa.c | 374 +++++++++++++++++++-----------
> tests/qtest/bios-tables-test.c | 116 ++++++++-
> tests/unit/test-smp-parse.c | 67 ++++--
> MAINTAINERS | 7 +-
> docs/interop/vhost-user.rst | 11 +
> docs/system/target-i386-desc.rst.inc | 8 +
> hw/i386/Kconfig | 3 +-
> hw/isa/Kconfig | 8 +-
> hw/isa/meson.build | 3 +-
> hw/mips/Kconfig | 2 +-
> meson.build | 1 +
> tests/data/acpi/q35/APIC.core-count | Bin 0 -> 544 bytes
> tests/data/acpi/q35/APIC.core-count2 | Bin 2478 -> 3238 bytes
> tests/data/acpi/q35/APIC.thread-count | Bin 0 -> 544 bytes
> tests/data/acpi/q35/APIC.thread-count2 | Bin 0 -> 7398 bytes
> tests/data/acpi/q35/APIC.type4-count | Bin 0 -> 1072 bytes
> tests/data/acpi/q35/DSDT.core-count | Bin 0 -> 12913 bytes
> tests/data/acpi/q35/DSDT.core-count2 | Bin 32495 -> 33770 bytes
> tests/data/acpi/q35/DSDT.cxl | Bin 9655 -> 9713 bytes
> tests/data/acpi/q35/DSDT.thread-count | Bin 0 -> 12913 bytes
> tests/data/acpi/q35/DSDT.thread-count2 | Bin 0 -> 63671 bytes
> tests/data/acpi/q35/DSDT.type4-count | Bin 0 -> 18589 bytes
> tests/data/acpi/q35/FACP.core-count | Bin 0 -> 244 bytes
> tests/data/acpi/q35/FACP.thread-count | Bin 0 -> 244 bytes
> tests/data/acpi/q35/FACP.thread-count2 | Bin 0 -> 244 bytes
> tests/data/acpi/q35/FACP.type4-count | Bin 0 -> 244 bytes
> 59 files changed, 1386 insertions(+), 852 deletions(-)
> rename hw/isa/{piix3.c => piix.c} (52%)
> delete mode 100644 hw/isa/piix4.c
> create mode 100644 tests/data/acpi/q35/APIC.core-count
> create mode 100644 tests/data/acpi/q35/APIC.thread-count
> create mode 100644 tests/data/acpi/q35/APIC.thread-count2
> create mode 100644 tests/data/acpi/q35/APIC.type4-count
> create mode 100644 tests/data/acpi/q35/DSDT.core-count
> create mode 100644 tests/data/acpi/q35/DSDT.thread-count
> create mode 100644 tests/data/acpi/q35/DSDT.thread-count2
> create mode 100644 tests/data/acpi/q35/DSDT.type4-count
> create mode 100644 tests/data/acpi/q35/FACP.core-count
> create mode 100644 tests/data/acpi/q35/FACP.thread-count
> create mode 100644 tests/data/acpi/q35/FACP.thread-count2
> create mode 100644 tests/data/acpi/q35/FACP.type4-count
>
>
^ permalink raw reply [flat|nested] 81+ messages in thread* Re: [PULL v2 00/78] virtio,pc,pci: features, cleanups
2023-10-20 16:00 ` [PULL v2 00/78] virtio,pc,pci: features, cleanups Stefan Hajnoczi
@ 2023-10-23 11:38 ` Michael S. Tsirkin
0 siblings, 0 replies; 81+ messages in thread
From: Michael S. Tsirkin @ 2023-10-23 11:38 UTC (permalink / raw)
To: Stefan Hajnoczi; +Cc: qemu-devel, Peter Maydell
On Fri, Oct 20, 2023 at 09:00:33AM -0700, Stefan Hajnoczi wrote:
> On Thu, 19 Oct 2023 at 11:30, Michael S. Tsirkin <mst@redhat.com> wrote:
> >
> > Changes from v1:
> > dropped shadow vq patches
> >
> > The following changes since commit ec6f9f135d5e5596ab0258da2ddd048f1fd8c359:
> >
> > Merge tag 'migration-20231017-pull-request' of https://gitlab.com/juan.quintela/qemu into staging (2023-10-17 10:06:21 -0400)
> >
> > are available in the Git repository at:
> >
> > https://git.kernel.org/pub/scm/virt/kvm/mst/qemu.git tags/for_upstream
> >
> > for you to fetch changes up to 16ef005ba922d5af498e9f0f2ee6b29a318821a8:
> >
> > intel-iommu: Report interrupt remapping faults, fix return value (2023-10-19 14:11:17 -0400)
> >
> > ----------------------------------------------------------------
> > virtio,pc,pci: features, cleanups
> >
> > infrastructure for vhost-vdpa shadow work
> > piix south bridge rework
> > reconnect for vhost-user-scsi
> > dummy ACPI QTG DSM for cxl
> >
> > tests, cleanups, fixes all over the place
> >
> > Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
> >
>
> Hi Michael,
> I think the following bios-tables-test failure is caused by this pull request:
>
> >>> MALLOC_PERTURB_=158 QTEST_QEMU_IMG=./qemu-img QTEST_QEMU_BINARY=./qemu-system-x86_64 G_TEST_DBUS_DAEMON=/builds/qemu-project/qemu/tests/dbus-vmstate-daemon.sh QTEST_QEMU_STORAGE_DAEMON_BINARY=./storage-daemon/qemu-storage-daemon PYTHON=/builds/qemu-project/qemu/build/pyvenv/bin/python3.8 /builds/qemu-project/qemu/build/tests/qtest/bios-tables-test --tap -k
> ――――――――――――――――――――――――――――――――――――― ✀ ―――――――――――――――――――――――――――――――――――――
> stderr:
> qemu-system-x86_64: -accel kvm: warning: Number of SMP cpus requested
> (260) exceeds the recommended cpus supported by KVM (240)
> qemu-system-x86_64: -accel kvm: warning: Number of hotpluggable cpus
> requested (260) exceeds the recommended cpus supported by KVM (240)
> qemu-system-x86_64: -accel kvm: warning: Number of hotpluggable cpus
> requested (520) exceeds the recommended cpus supported by KVM (240)
> Number of hotpluggable cpus requested (520) exceeds the maximum cpus
> supported by KVM (288)
> socket_accept failed: Resource temporarily unavailable
> **
> ERROR:../tests/qtest/libqtest.c:496:qtest_init_internal: assertion
> failed: (s->fd >= 0 && s->qmp_fd >= 0)
> ../tests/qtest/libqtest.c:195: kill_qemu() tried to terminate QEMU
> process but encountered exit status 1 (expected 0)
> (test program exited with status code -6)
>
> https://gitlab.com/qemu-project/qemu/-/jobs/5338513625
>
> Please take a look. Thanks!
>
> Stefan
I dropped the offending patches. Thanks!
> > ----------------------------------------------------------------
> > Ani Sinha (1):
> > hw/i386/cxl: ensure maxram is greater than ram size for calculating cxl range
> >
> > Bernhard Beschow (30):
> > hw/i386/acpi-build: Remove build-time assertion on PIIX/ICH9 reset registers being identical
> > hw/i386/pc: Merge two if statements into one
> > hw/i386/pc_piix: Allow for setting properties before realizing PIIX3 south bridge
> > hw/i386/pc_piix: Assign PIIX3's ISA interrupts before its realize()
> > hw/isa/piix3: Resolve redundant PIIX_NUM_PIC_IRQS
> > hw/i386/pc_piix: Wire PIIX3's ISA interrupts by new "isa-irqs" property
> > hw/i386/pc_piix: Remove redundant "piix3" variable
> > hw/isa/piix3: Rename "pic" attribute to "isa_irqs_in"
> > hw/i386/pc_q35: Wire ICH9 LPC function's interrupts before its realize()
> > hw/isa/piix3: Wire PIC IRQs to ISA bus in host device
> > hw/i386/pc: Wire RTC ISA IRQs in south bridges
> > hw/isa/piix3: Create IDE controller in host device
> > hw/isa/piix3: Create USB controller in host device
> > hw/isa/piix3: Create power management controller in host device
> > hw/isa/piix3: Drop the "3" from PIIX base class name
> > hw/isa/piix4: Remove unused inbound ISA interrupt lines
> > hw/isa/piix4: Rename "isa" attribute to "isa_irqs_in"
> > hw/isa/piix4: Rename reset control operations to match PIIX3
> > hw/isa/piix4: Reuse struct PIIXState from PIIX3
> > hw/isa/piix3: Merge hw/isa/piix4.c
> > hw/isa/piix: Allow for optional PIC creation in PIIX3
> > hw/isa/piix: Allow for optional PIT creation in PIIX3
> > hw/isa/piix: Harmonize names of reset control memory regions
> > hw/isa/piix: Share PIIX3's base class with PIIX4
> > hw/isa/piix: Reuse PIIX3 base class' realize method in PIIX4
> > hw/isa/piix: Rename functions to be shared for PCI interrupt triggering
> > hw/isa/piix: Reuse PIIX3's PCI interrupt triggering in PIIX4
> > hw/isa/piix: Resolve duplicate code regarding PCI interrupt wiring
> > hw/isa/piix: Implement multi-process QEMU support also for PIIX4
> > hw/i386/pc_piix: Make PIIX4 south bridge usable in PC machine
> >
> > Damien Zammit (1):
> > timer/i8254: Fix one shot PIT mode
> >
> > Dave Jiang (1):
> > hw/cxl: Add QTG _DSM support for ACPI0017 device
> >
> > David Woodhouse (1):
> > intel-iommu: Report interrupt remapping faults, fix return value
> >
> > Hanna Czenczek (1):
> > vhost-user: Fix protocol feature bit conflict
> >
> > Hawkins Jiawei (7):
> > vdpa: Use iovec for vhost_vdpa_net_cvq_add()
> > vdpa: Avoid using vhost_vdpa_net_load_*() outside vhost_vdpa_net_load()
> > vdpa: Check device ack in vhost_vdpa_net_load_rx_mode()
> > vdpa: Move vhost_svq_poll() to the caller of vhost_vdpa_net_cvq_add()
> > vdpa: Introduce cursors to vhost_vdpa_net_loadx()
> > vhost: Expose vhost_svq_available_slots()
> > vdpa: Send cvq state load commands in parallel
> >
> > Ilya Maximets (1):
> > memory: initialize 'fv' in MemoryRegionCache to make Coverity happy
> >
> > Jonathan Cameron (2):
> > tests/acpi: Allow update of DSDT.cxl
> > tests/acpi: Update DSDT.cxl with QTG DSM
> >
> > Laszlo Ersek (7):
> > vhost-user: strip superfluous whitespace
> > vhost-user: tighten "reply_supported" scope in "set_vring_addr"
> > vhost-user: factor out "vhost_user_write_sync"
> > vhost-user: flatten "enforce_reply" into "vhost_user_write_sync"
> > vhost-user: hoist "write_sync", "get_features", "get_u64"
> > vhost-user: allow "vhost_set_vring" to wait for a reply
> > vhost-user: call VHOST_USER_SET_VRING_ENABLE synchronously
> >
> > Li Feng (5):
> > vhost-user-common: send get_inflight_fd once
> > vhost: move and rename the conn retry times
> > vhost-user-scsi: support reconnect to backend
> > vhost-user-scsi: start vhost when guest kicks
> > vhost-user: fix lost reconnect
> >
> > Matheus Tavares Bernardino (1):
> > hw/display: fix memleak from virtio_add_resource
> >
> > Stefan Hajnoczi (3):
> > vhost-user: do not send RESET_OWNER on device reset
> > vhost-backend: remove vhost_kernel_reset_device()
> > virtio: call ->vhost_reset_device() during reset
> >
> > Thomas Huth (1):
> > MAINTAINERS: Add include/hw/intc/i8259.h to the PC chip section
> >
> > Zhao Liu (16):
> > tests: test-smp-parse: Add the test for cores/threads per socket helpers
> > tests: bios-tables-test: Prepare the ACPI table change for smbios type4 count test
> > tests: bios-tables-test: Add test for smbios type4 count
> > tests: bios-tables-test: Add ACPI table binaries for smbios type4 count test
> > tests: bios-tables-test: Prepare the ACPI table change for smbios type4 core count test
> > tests: bios-tables-test: Add test for smbios type4 core count
> > tests: bios-tables-test: Add ACPI table binaries for smbios type4 core count test
> > tests: bios-tables-test: Prepare the ACPI table change for smbios type4 core count2 test
> > tests: bios-tables-test: Extend smbios core count2 test to cover general topology
> > tests: bios-tables-test: Update ACPI table binaries for smbios core count2 test
> > tests: bios-tables-test: Prepare the ACPI table change for smbios type4 thread count test
> > tests: bios-tables-test: Add test for smbios type4 thread count
> > tests: bios-tables-test: Add ACPI table binaries for smbios type4 thread count test
> > tests: bios-tables-test: Prepare the ACPI table change for smbios type4 thread count2 test
> > tests: bios-tables-test: Add test for smbios type4 thread count2
> > tests: bios-tables-test: Add ACPI table binaries for smbios type4 thread count2 test
> >
> > hw/i386/intel_iommu_internal.h | 1 +
> > hw/virtio/vhost-shadow-virtqueue.h | 1 +
> > include/exec/memory.h | 2 +
> > include/hw/acpi/cxl.h | 1 +
> > include/hw/i386/pc.h | 2 +
> > include/hw/southbridge/piix.h | 30 ++-
> > include/hw/virtio/vhost-scsi-common.h | 2 +-
> > include/hw/virtio/vhost-user-scsi.h | 6 +
> > include/hw/virtio/vhost-user.h | 6 +-
> > include/hw/virtio/vhost.h | 12 +
> > subprojects/libvhost-user/libvhost-user.h | 3 +-
> > hw/acpi/cxl.c | 69 ++++++
> > hw/block/vhost-user-blk.c | 6 +-
> > hw/display/virtio-dmabuf.c | 12 +-
> > hw/i386/acpi-build.c | 6 +-
> > hw/i386/intel_iommu.c | 150 ++++++++----
> > hw/i386/pc.c | 19 +-
> > hw/i386/pc_piix.c | 123 +++++++---
> > hw/i386/pc_q35.c | 14 +-
> > hw/isa/lpc_ich9.c | 9 +-
> > hw/isa/{piix3.c => piix.c} | 281 ++++++++++++++++------
> > hw/isa/piix4.c | 302 ------------------------
> > hw/mips/malta.c | 5 +-
> > hw/scsi/vhost-scsi-common.c | 47 ++--
> > hw/scsi/vhost-scsi.c | 6 +-
> > hw/scsi/vhost-user-scsi.c | 254 +++++++++++++++++---
> > hw/timer/i8254_common.c | 4 +-
> > hw/virtio/vhost-backend.c | 6 -
> > hw/virtio/vhost-shadow-virtqueue.c | 2 +-
> > hw/virtio/vhost-user-gpio.c | 5 +-
> > hw/virtio/vhost-user.c | 239 ++++++++++---------
> > hw/virtio/vhost.c | 9 +
> > hw/virtio/virtio.c | 4 +
> > net/vhost-vdpa.c | 374 +++++++++++++++++++-----------
> > tests/qtest/bios-tables-test.c | 116 ++++++++-
> > tests/unit/test-smp-parse.c | 67 ++++--
> > MAINTAINERS | 7 +-
> > docs/interop/vhost-user.rst | 11 +
> > docs/system/target-i386-desc.rst.inc | 8 +
> > hw/i386/Kconfig | 3 +-
> > hw/isa/Kconfig | 8 +-
> > hw/isa/meson.build | 3 +-
> > hw/mips/Kconfig | 2 +-
> > meson.build | 1 +
> > tests/data/acpi/q35/APIC.core-count | Bin 0 -> 544 bytes
> > tests/data/acpi/q35/APIC.core-count2 | Bin 2478 -> 3238 bytes
> > tests/data/acpi/q35/APIC.thread-count | Bin 0 -> 544 bytes
> > tests/data/acpi/q35/APIC.thread-count2 | Bin 0 -> 7398 bytes
> > tests/data/acpi/q35/APIC.type4-count | Bin 0 -> 1072 bytes
> > tests/data/acpi/q35/DSDT.core-count | Bin 0 -> 12913 bytes
> > tests/data/acpi/q35/DSDT.core-count2 | Bin 32495 -> 33770 bytes
> > tests/data/acpi/q35/DSDT.cxl | Bin 9655 -> 9713 bytes
> > tests/data/acpi/q35/DSDT.thread-count | Bin 0 -> 12913 bytes
> > tests/data/acpi/q35/DSDT.thread-count2 | Bin 0 -> 63671 bytes
> > tests/data/acpi/q35/DSDT.type4-count | Bin 0 -> 18589 bytes
> > tests/data/acpi/q35/FACP.core-count | Bin 0 -> 244 bytes
> > tests/data/acpi/q35/FACP.thread-count | Bin 0 -> 244 bytes
> > tests/data/acpi/q35/FACP.thread-count2 | Bin 0 -> 244 bytes
> > tests/data/acpi/q35/FACP.type4-count | Bin 0 -> 244 bytes
> > 59 files changed, 1386 insertions(+), 852 deletions(-)
> > rename hw/isa/{piix3.c => piix.c} (52%)
> > delete mode 100644 hw/isa/piix4.c
> > create mode 100644 tests/data/acpi/q35/APIC.core-count
> > create mode 100644 tests/data/acpi/q35/APIC.thread-count
> > create mode 100644 tests/data/acpi/q35/APIC.thread-count2
> > create mode 100644 tests/data/acpi/q35/APIC.type4-count
> > create mode 100644 tests/data/acpi/q35/DSDT.core-count
> > create mode 100644 tests/data/acpi/q35/DSDT.thread-count
> > create mode 100644 tests/data/acpi/q35/DSDT.thread-count2
> > create mode 100644 tests/data/acpi/q35/DSDT.type4-count
> > create mode 100644 tests/data/acpi/q35/FACP.core-count
> > create mode 100644 tests/data/acpi/q35/FACP.thread-count
> > create mode 100644 tests/data/acpi/q35/FACP.thread-count2
> > create mode 100644 tests/data/acpi/q35/FACP.type4-count
> >
> >
^ permalink raw reply [flat|nested] 81+ messages in thread