* [PATCH 00/10] riscv: create_fdt() related cleanups
@ 2023-01-11 17:09 Daniel Henrique Barboza
2023-01-11 17:09 ` [PATCH 01/10] hw/riscv/spike.c: simplify create_fdt() Daniel Henrique Barboza
` (11 more replies)
0 siblings, 12 replies; 20+ messages in thread
From: Daniel Henrique Barboza @ 2023-01-11 17:09 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv, alistair.francis, Daniel Henrique Barboza
Hi,
This is a follow-up of:
"[PATCH v5 00/11] riscv: OpenSBI boot test and cleanups"
Patches were based on top of riscv-to-apply.next [1] + the series above.
The recent FDT changes made in hw/riscv (all machines are now using the
FDT via MachineState::fdt) allowed for most of the cleanups made here.
Patches 9 and 10 were based on a suggestion made by Phil a few weeks ago.
I decided to go for it.
[1] https://github.com/alistair23/qemu/tree/riscv-to-apply.next
Daniel Henrique Barboza (10):
hw/riscv/spike.c: simplify create_fdt()
hw/riscv/virt.c: simplify create_fdt()
hw/riscv/sifive_u.c: simplify create_fdt()
hw/riscv/virt.c: remove 'is_32_bit' param from
create_fdt_socket_cpus()
hw/riscv: use MachineState::fdt in riscv_socket_fdt_write_id()
hw/riscv: use ms->fdt in riscv_socket_fdt_write_distance_matrix()
hw/riscv: simplify riscv_load_fdt()
hw/riscv/virt.c: calculate socket count once in create_fdt_imsic()
hw/riscv/virt.c: rename MachineState 'mc' pointers to 'ms'
hw/riscv/spike.c: rename MachineState 'mc' pointers to' ms'
hw/riscv/boot.c | 4 +-
hw/riscv/microchip_pfsoc.c | 4 +-
hw/riscv/numa.c | 14 +-
hw/riscv/sifive_u.c | 11 +-
hw/riscv/spike.c | 25 +-
hw/riscv/virt.c | 484 +++++++++++++++++++------------------
include/hw/riscv/boot.h | 2 +-
include/hw/riscv/numa.h | 10 +-
8 files changed, 277 insertions(+), 277 deletions(-)
--
2.39.0
^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCH 01/10] hw/riscv/spike.c: simplify create_fdt() 2023-01-11 17:09 [PATCH 00/10] riscv: create_fdt() related cleanups Daniel Henrique Barboza @ 2023-01-11 17:09 ` Daniel Henrique Barboza 2023-01-16 3:53 ` Alistair Francis 2023-01-11 17:09 ` [PATCH 02/10] hw/riscv/virt.c: " Daniel Henrique Barboza ` (10 subsequent siblings) 11 siblings, 1 reply; 20+ messages in thread From: Daniel Henrique Barboza @ 2023-01-11 17:09 UTC (permalink / raw) To: qemu-devel; +Cc: qemu-riscv, alistair.francis, Daniel Henrique Barboza 'mem_size' and 'cmdline' are unused. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> --- hw/riscv/spike.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index c517885e6e..4a66016d69 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -49,7 +49,6 @@ static const MemMapEntry spike_memmap[] = { }; static void create_fdt(SpikeState *s, const MemMapEntry *memmap, - uint64_t mem_size, const char *cmdline, bool is_32_bit, bool htif_custom_base) { void *fdt; @@ -299,8 +298,7 @@ static void spike_board_init(MachineState *machine) } /* Create device tree */ - create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, - riscv_is_32bit(&s->soc[0]), htif_custom_base); + create_fdt(s, memmap, riscv_is_32bit(&s->soc[0]), htif_custom_base); /* Load kernel */ if (machine->kernel_filename) { -- 2.39.0 ^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [PATCH 01/10] hw/riscv/spike.c: simplify create_fdt() 2023-01-11 17:09 ` [PATCH 01/10] hw/riscv/spike.c: simplify create_fdt() Daniel Henrique Barboza @ 2023-01-16 3:53 ` Alistair Francis 0 siblings, 0 replies; 20+ messages in thread From: Alistair Francis @ 2023-01-16 3:53 UTC (permalink / raw) To: Daniel Henrique Barboza; +Cc: qemu-devel, qemu-riscv, alistair.francis On Thu, Jan 12, 2023 at 3:21 AM Daniel Henrique Barboza <dbarboza@ventanamicro.com> wrote: > > 'mem_size' and 'cmdline' are unused. > > Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > hw/riscv/spike.c | 4 +--- > 1 file changed, 1 insertion(+), 3 deletions(-) > > diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c > index c517885e6e..4a66016d69 100644 > --- a/hw/riscv/spike.c > +++ b/hw/riscv/spike.c > @@ -49,7 +49,6 @@ static const MemMapEntry spike_memmap[] = { > }; > > static void create_fdt(SpikeState *s, const MemMapEntry *memmap, > - uint64_t mem_size, const char *cmdline, > bool is_32_bit, bool htif_custom_base) > { > void *fdt; > @@ -299,8 +298,7 @@ static void spike_board_init(MachineState *machine) > } > > /* Create device tree */ > - create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, > - riscv_is_32bit(&s->soc[0]), htif_custom_base); > + create_fdt(s, memmap, riscv_is_32bit(&s->soc[0]), htif_custom_base); > > /* Load kernel */ > if (machine->kernel_filename) { > -- > 2.39.0 > > ^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 02/10] hw/riscv/virt.c: simplify create_fdt() 2023-01-11 17:09 [PATCH 00/10] riscv: create_fdt() related cleanups Daniel Henrique Barboza 2023-01-11 17:09 ` [PATCH 01/10] hw/riscv/spike.c: simplify create_fdt() Daniel Henrique Barboza @ 2023-01-11 17:09 ` Daniel Henrique Barboza 2023-01-16 3:54 ` Alistair Francis 2023-01-11 17:09 ` [PATCH 03/10] hw/riscv/sifive_u.c: " Daniel Henrique Barboza ` (9 subsequent siblings) 11 siblings, 1 reply; 20+ messages in thread From: Daniel Henrique Barboza @ 2023-01-11 17:09 UTC (permalink / raw) To: qemu-devel; +Cc: qemu-riscv, alistair.francis, Daniel Henrique Barboza 'mem_size' and 'cmdline' aren't being used. Remove them. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> --- hw/riscv/virt.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index a931ed05ab..89c99ec1af 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -999,7 +999,7 @@ static void create_fdt_fw_cfg(RISCVVirtState *s, const MemMapEntry *memmap) } static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, - uint64_t mem_size, const char *cmdline, bool is_32_bit) + bool is_32_bit) { MachineState *mc = MACHINE(s); uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1; @@ -1499,8 +1499,7 @@ static void virt_machine_init(MachineState *machine) virt_flash_map(s, system_memory); /* create device tree */ - create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, - riscv_is_32bit(&s->soc[0])); + create_fdt(s, memmap, riscv_is_32bit(&s->soc[0])); s->machine_done.notify = virt_machine_done; qemu_add_machine_init_done_notifier(&s->machine_done); -- 2.39.0 ^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [PATCH 02/10] hw/riscv/virt.c: simplify create_fdt() 2023-01-11 17:09 ` [PATCH 02/10] hw/riscv/virt.c: " Daniel Henrique Barboza @ 2023-01-16 3:54 ` Alistair Francis 0 siblings, 0 replies; 20+ messages in thread From: Alistair Francis @ 2023-01-16 3:54 UTC (permalink / raw) To: Daniel Henrique Barboza; +Cc: qemu-devel, qemu-riscv, alistair.francis On Thu, Jan 12, 2023 at 3:18 AM Daniel Henrique Barboza <dbarboza@ventanamicro.com> wrote: > > 'mem_size' and 'cmdline' aren't being used. Remove them. > > Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > hw/riscv/virt.c | 5 ++--- > 1 file changed, 2 insertions(+), 3 deletions(-) > > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c > index a931ed05ab..89c99ec1af 100644 > --- a/hw/riscv/virt.c > +++ b/hw/riscv/virt.c > @@ -999,7 +999,7 @@ static void create_fdt_fw_cfg(RISCVVirtState *s, const MemMapEntry *memmap) > } > > static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, > - uint64_t mem_size, const char *cmdline, bool is_32_bit) > + bool is_32_bit) > { > MachineState *mc = MACHINE(s); > uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1; > @@ -1499,8 +1499,7 @@ static void virt_machine_init(MachineState *machine) > virt_flash_map(s, system_memory); > > /* create device tree */ > - create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, > - riscv_is_32bit(&s->soc[0])); > + create_fdt(s, memmap, riscv_is_32bit(&s->soc[0])); > > s->machine_done.notify = virt_machine_done; > qemu_add_machine_init_done_notifier(&s->machine_done); > -- > 2.39.0 > > ^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 03/10] hw/riscv/sifive_u.c: simplify create_fdt() 2023-01-11 17:09 [PATCH 00/10] riscv: create_fdt() related cleanups Daniel Henrique Barboza 2023-01-11 17:09 ` [PATCH 01/10] hw/riscv/spike.c: simplify create_fdt() Daniel Henrique Barboza 2023-01-11 17:09 ` [PATCH 02/10] hw/riscv/virt.c: " Daniel Henrique Barboza @ 2023-01-11 17:09 ` Daniel Henrique Barboza 2023-01-16 3:57 ` Alistair Francis 2023-01-11 17:09 ` [PATCH 04/10] hw/riscv/virt.c: remove 'is_32_bit' param from create_fdt_socket_cpus() Daniel Henrique Barboza ` (8 subsequent siblings) 11 siblings, 1 reply; 20+ messages in thread From: Daniel Henrique Barboza @ 2023-01-11 17:09 UTC (permalink / raw) To: qemu-devel Cc: qemu-riscv, alistair.francis, Daniel Henrique Barboza, Palmer Dabbelt 'cmdline' isn't being used. Remove it. A MachineState pointer is being retrieved via a MACHINE() macro calling qdev_get_machine(). Use MACHINE(s) instead to avoid calling qdev(). 'mem_size' is being set as machine->ram_size by the caller. Retrieve it via ms->ram_size. Cc: Palmer Dabbelt <palmer@dabbelt.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> --- hw/riscv/sifive_u.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 9a75d4aa62..ccad386920 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -94,9 +94,10 @@ static const MemMapEntry sifive_u_memmap[] = { #define GEM_REVISION 0x10070109 static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap, - uint64_t mem_size, const char *cmdline, bool is_32_bit) + bool is_32_bit) { - MachineState *ms = MACHINE(qdev_get_machine()); + MachineState *ms = MACHINE(s); + uint64_t mem_size = ms->ram_size; void *fdt; int cpu, fdt_size; uint32_t *cells; @@ -560,8 +561,7 @@ static void sifive_u_machine_init(MachineState *machine) qemu_allocate_irq(sifive_u_machine_reset, NULL, 0)); /* create device tree */ - create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, - riscv_is_32bit(&s->soc.u_cpus)); + create_fdt(s, memmap, riscv_is_32bit(&s->soc.u_cpus)); if (s->start_in_flash) { /* -- 2.39.0 ^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [PATCH 03/10] hw/riscv/sifive_u.c: simplify create_fdt() 2023-01-11 17:09 ` [PATCH 03/10] hw/riscv/sifive_u.c: " Daniel Henrique Barboza @ 2023-01-16 3:57 ` Alistair Francis 0 siblings, 0 replies; 20+ messages in thread From: Alistair Francis @ 2023-01-16 3:57 UTC (permalink / raw) To: Daniel Henrique Barboza Cc: qemu-devel, qemu-riscv, alistair.francis, Palmer Dabbelt On Thu, Jan 12, 2023 at 3:25 AM Daniel Henrique Barboza <dbarboza@ventanamicro.com> wrote: > > 'cmdline' isn't being used. Remove it. > > A MachineState pointer is being retrieved via a MACHINE() macro calling > qdev_get_machine(). Use MACHINE(s) instead to avoid calling qdev(). > > 'mem_size' is being set as machine->ram_size by the caller. Retrieve it > via ms->ram_size. > > Cc: Palmer Dabbelt <palmer@dabbelt.com> > Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > hw/riscv/sifive_u.c | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c > index 9a75d4aa62..ccad386920 100644 > --- a/hw/riscv/sifive_u.c > +++ b/hw/riscv/sifive_u.c > @@ -94,9 +94,10 @@ static const MemMapEntry sifive_u_memmap[] = { > #define GEM_REVISION 0x10070109 > > static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap, > - uint64_t mem_size, const char *cmdline, bool is_32_bit) > + bool is_32_bit) > { > - MachineState *ms = MACHINE(qdev_get_machine()); > + MachineState *ms = MACHINE(s); > + uint64_t mem_size = ms->ram_size; > void *fdt; > int cpu, fdt_size; > uint32_t *cells; > @@ -560,8 +561,7 @@ static void sifive_u_machine_init(MachineState *machine) > qemu_allocate_irq(sifive_u_machine_reset, NULL, 0)); > > /* create device tree */ > - create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, > - riscv_is_32bit(&s->soc.u_cpus)); > + create_fdt(s, memmap, riscv_is_32bit(&s->soc.u_cpus)); > > if (s->start_in_flash) { > /* > -- > 2.39.0 > > ^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 04/10] hw/riscv/virt.c: remove 'is_32_bit' param from create_fdt_socket_cpus() 2023-01-11 17:09 [PATCH 00/10] riscv: create_fdt() related cleanups Daniel Henrique Barboza ` (2 preceding siblings ...) 2023-01-11 17:09 ` [PATCH 03/10] hw/riscv/sifive_u.c: " Daniel Henrique Barboza @ 2023-01-11 17:09 ` Daniel Henrique Barboza 2023-01-16 3:58 ` Alistair Francis 2023-01-11 17:09 ` [PATCH 05/10] hw/riscv: use MachineState::fdt in riscv_socket_fdt_write_id() Daniel Henrique Barboza ` (7 subsequent siblings) 11 siblings, 1 reply; 20+ messages in thread From: Daniel Henrique Barboza @ 2023-01-11 17:09 UTC (permalink / raw) To: qemu-devel; +Cc: qemu-riscv, alistair.francis, Daniel Henrique Barboza create_fdt_socket_cpus() writes a different 'mmu-type' value if we're running in 32 or 64 bits. However, the flag is being calculated during virt_machine_init(), and is passed around in create_fdt(), then create_fdt_socket(), and then finally create_fdt_socket_cpus(). None of the intermediate functions are using the flag, which is a bit misleading. Remove 'is_32_bit' flag from create_fdt_socket_cpus() and calculate it using the already available RISCVVirtState pointer. This will also change the signature of create_fdt_socket() and create_fdt(), making it clear that these functions don't do anything special when we're running in 32 bit mode. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> --- hw/riscv/virt.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 89c99ec1af..99a0a43a73 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -223,12 +223,13 @@ static void create_pcie_irq_map(RISCVVirtState *s, void *fdt, char *nodename, static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, char *clust_name, uint32_t *phandle, - bool is_32_bit, uint32_t *intc_phandles) + uint32_t *intc_phandles) { int cpu; uint32_t cpu_phandle; MachineState *mc = MACHINE(s); char *name, *cpu_name, *core_name, *intc_name; + bool is_32_bit = riscv_is_32bit(&s->soc[0]); for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { cpu_phandle = (*phandle)++; @@ -721,7 +722,7 @@ static void create_fdt_pmu(RISCVVirtState *s) } static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, - bool is_32_bit, uint32_t *phandle, + uint32_t *phandle, uint32_t *irq_mmio_phandle, uint32_t *irq_pcie_phandle, uint32_t *irq_virtio_phandle, @@ -750,7 +751,7 @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, qemu_fdt_add_subnode(mc->fdt, clust_name); create_fdt_socket_cpus(s, socket, clust_name, phandle, - is_32_bit, &intc_phandles[phandle_pos]); + &intc_phandles[phandle_pos]); create_fdt_socket_memory(s, memmap, socket); @@ -998,8 +999,7 @@ static void create_fdt_fw_cfg(RISCVVirtState *s, const MemMapEntry *memmap) g_free(nodename); } -static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, - bool is_32_bit) +static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap) { MachineState *mc = MACHINE(s); uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1; @@ -1031,9 +1031,9 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, qemu_fdt_setprop_cell(mc->fdt, "/soc", "#size-cells", 0x2); qemu_fdt_setprop_cell(mc->fdt, "/soc", "#address-cells", 0x2); - create_fdt_sockets(s, memmap, is_32_bit, &phandle, - &irq_mmio_phandle, &irq_pcie_phandle, &irq_virtio_phandle, - &msi_pcie_phandle); + create_fdt_sockets(s, memmap, &phandle, &irq_mmio_phandle, + &irq_pcie_phandle, &irq_virtio_phandle, + &msi_pcie_phandle); create_fdt_virtio(s, memmap, irq_virtio_phandle); @@ -1499,7 +1499,7 @@ static void virt_machine_init(MachineState *machine) virt_flash_map(s, system_memory); /* create device tree */ - create_fdt(s, memmap, riscv_is_32bit(&s->soc[0])); + create_fdt(s, memmap); s->machine_done.notify = virt_machine_done; qemu_add_machine_init_done_notifier(&s->machine_done); -- 2.39.0 ^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [PATCH 04/10] hw/riscv/virt.c: remove 'is_32_bit' param from create_fdt_socket_cpus() 2023-01-11 17:09 ` [PATCH 04/10] hw/riscv/virt.c: remove 'is_32_bit' param from create_fdt_socket_cpus() Daniel Henrique Barboza @ 2023-01-16 3:58 ` Alistair Francis 0 siblings, 0 replies; 20+ messages in thread From: Alistair Francis @ 2023-01-16 3:58 UTC (permalink / raw) To: Daniel Henrique Barboza; +Cc: qemu-devel, qemu-riscv, alistair.francis On Thu, Jan 12, 2023 at 3:22 AM Daniel Henrique Barboza <dbarboza@ventanamicro.com> wrote: > > create_fdt_socket_cpus() writes a different 'mmu-type' value if we're > running in 32 or 64 bits. However, the flag is being calculated during > virt_machine_init(), and is passed around in create_fdt(), then > create_fdt_socket(), and then finally create_fdt_socket_cpus(). None of > the intermediate functions are using the flag, which is a bit > misleading. > > Remove 'is_32_bit' flag from create_fdt_socket_cpus() and calculate it > using the already available RISCVVirtState pointer. This will also > change the signature of create_fdt_socket() and create_fdt(), making it > clear that these functions don't do anything special when we're running > in 32 bit mode. > > Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > hw/riscv/virt.c | 18 +++++++++--------- > 1 file changed, 9 insertions(+), 9 deletions(-) > > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c > index 89c99ec1af..99a0a43a73 100644 > --- a/hw/riscv/virt.c > +++ b/hw/riscv/virt.c > @@ -223,12 +223,13 @@ static void create_pcie_irq_map(RISCVVirtState *s, void *fdt, char *nodename, > > static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, > char *clust_name, uint32_t *phandle, > - bool is_32_bit, uint32_t *intc_phandles) > + uint32_t *intc_phandles) > { > int cpu; > uint32_t cpu_phandle; > MachineState *mc = MACHINE(s); > char *name, *cpu_name, *core_name, *intc_name; > + bool is_32_bit = riscv_is_32bit(&s->soc[0]); > > for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { > cpu_phandle = (*phandle)++; > @@ -721,7 +722,7 @@ static void create_fdt_pmu(RISCVVirtState *s) > } > > static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, > - bool is_32_bit, uint32_t *phandle, > + uint32_t *phandle, > uint32_t *irq_mmio_phandle, > uint32_t *irq_pcie_phandle, > uint32_t *irq_virtio_phandle, > @@ -750,7 +751,7 @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, > qemu_fdt_add_subnode(mc->fdt, clust_name); > > create_fdt_socket_cpus(s, socket, clust_name, phandle, > - is_32_bit, &intc_phandles[phandle_pos]); > + &intc_phandles[phandle_pos]); > > create_fdt_socket_memory(s, memmap, socket); > > @@ -998,8 +999,7 @@ static void create_fdt_fw_cfg(RISCVVirtState *s, const MemMapEntry *memmap) > g_free(nodename); > } > > -static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, > - bool is_32_bit) > +static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap) > { > MachineState *mc = MACHINE(s); > uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1; > @@ -1031,9 +1031,9 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, > qemu_fdt_setprop_cell(mc->fdt, "/soc", "#size-cells", 0x2); > qemu_fdt_setprop_cell(mc->fdt, "/soc", "#address-cells", 0x2); > > - create_fdt_sockets(s, memmap, is_32_bit, &phandle, > - &irq_mmio_phandle, &irq_pcie_phandle, &irq_virtio_phandle, > - &msi_pcie_phandle); > + create_fdt_sockets(s, memmap, &phandle, &irq_mmio_phandle, > + &irq_pcie_phandle, &irq_virtio_phandle, > + &msi_pcie_phandle); > > create_fdt_virtio(s, memmap, irq_virtio_phandle); > > @@ -1499,7 +1499,7 @@ static void virt_machine_init(MachineState *machine) > virt_flash_map(s, system_memory); > > /* create device tree */ > - create_fdt(s, memmap, riscv_is_32bit(&s->soc[0])); > + create_fdt(s, memmap); > > s->machine_done.notify = virt_machine_done; > qemu_add_machine_init_done_notifier(&s->machine_done); > -- > 2.39.0 > > ^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 05/10] hw/riscv: use MachineState::fdt in riscv_socket_fdt_write_id() 2023-01-11 17:09 [PATCH 00/10] riscv: create_fdt() related cleanups Daniel Henrique Barboza ` (3 preceding siblings ...) 2023-01-11 17:09 ` [PATCH 04/10] hw/riscv/virt.c: remove 'is_32_bit' param from create_fdt_socket_cpus() Daniel Henrique Barboza @ 2023-01-11 17:09 ` Daniel Henrique Barboza 2023-01-16 4:01 ` Alistair Francis 2023-01-11 17:09 ` [PATCH 06/10] hw/riscv: use ms->fdt in riscv_socket_fdt_write_distance_matrix() Daniel Henrique Barboza ` (6 subsequent siblings) 11 siblings, 1 reply; 20+ messages in thread From: Daniel Henrique Barboza @ 2023-01-11 17:09 UTC (permalink / raw) To: qemu-devel; +Cc: qemu-riscv, alistair.francis, Daniel Henrique Barboza There's no need to use a MachineState pointer and a fdt pointer now that all RISC-V machines are using the FDT from the MachineState. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> --- hw/riscv/numa.c | 6 +++--- hw/riscv/spike.c | 6 +++--- hw/riscv/virt.c | 18 +++++++++--------- include/hw/riscv/numa.h | 6 +++--- 4 files changed, 18 insertions(+), 18 deletions(-) diff --git a/hw/riscv/numa.c b/hw/riscv/numa.c index 7fe92d402f..f4343f5cde 100644 --- a/hw/riscv/numa.c +++ b/hw/riscv/numa.c @@ -156,11 +156,11 @@ uint64_t riscv_socket_mem_size(const MachineState *ms, int socket_id) ms->numa_state->nodes[socket_id].node_mem : 0; } -void riscv_socket_fdt_write_id(const MachineState *ms, void *fdt, - const char *node_name, int socket_id) +void riscv_socket_fdt_write_id(const MachineState *ms, const char *node_name, + int socket_id) { if (numa_enabled(ms)) { - qemu_fdt_setprop_cell(fdt, node_name, "numa-node-id", socket_id); + qemu_fdt_setprop_cell(ms->fdt, node_name, "numa-node-id", socket_id); } } diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 4a66016d69..05d34651cb 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -121,7 +121,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, qemu_fdt_setprop_cell(fdt, cpu_name, "reg", s->soc[socket].hartid_base + cpu); qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu"); - riscv_socket_fdt_write_id(mc, fdt, cpu_name, socket); + riscv_socket_fdt_write_id(mc, cpu_name, socket); qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle); intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name); @@ -154,7 +154,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, qemu_fdt_setprop_cells(fdt, mem_name, "reg", addr >> 32, addr, size >> 32, size); qemu_fdt_setprop_string(fdt, mem_name, "device_type", "memory"); - riscv_socket_fdt_write_id(mc, fdt, mem_name, socket); + riscv_socket_fdt_write_id(mc, mem_name, socket); g_free(mem_name); clint_addr = memmap[SPIKE_CLINT].base + @@ -167,7 +167,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, 0x0, clint_addr, 0x0, memmap[SPIKE_CLINT].size); qemu_fdt_setprop(fdt, clint_name, "interrupts-extended", clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); - riscv_socket_fdt_write_id(mc, fdt, clint_name, socket); + riscv_socket_fdt_write_id(mc, clint_name, socket); g_free(clint_name); g_free(clint_cells); diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 99a0a43a73..1d3bd25cb5 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -253,7 +253,7 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, qemu_fdt_setprop_cell(mc->fdt, cpu_name, "reg", s->soc[socket].hartid_base + cpu); qemu_fdt_setprop_string(mc->fdt, cpu_name, "device_type", "cpu"); - riscv_socket_fdt_write_id(mc, mc->fdt, cpu_name, socket); + riscv_socket_fdt_write_id(mc, cpu_name, socket); qemu_fdt_setprop_cell(mc->fdt, cpu_name, "phandle", cpu_phandle); intc_phandles[cpu] = (*phandle)++; @@ -291,7 +291,7 @@ static void create_fdt_socket_memory(RISCVVirtState *s, qemu_fdt_setprop_cells(mc->fdt, mem_name, "reg", addr >> 32, addr, size >> 32, size); qemu_fdt_setprop_string(mc->fdt, mem_name, "device_type", "memory"); - riscv_socket_fdt_write_id(mc, mc->fdt, mem_name, socket); + riscv_socket_fdt_write_id(mc, mem_name, socket); g_free(mem_name); } @@ -327,7 +327,7 @@ static void create_fdt_socket_clint(RISCVVirtState *s, 0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size); qemu_fdt_setprop(mc->fdt, clint_name, "interrupts-extended", clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); - riscv_socket_fdt_write_id(mc, mc->fdt, clint_name, socket); + riscv_socket_fdt_write_id(mc, clint_name, socket); g_free(clint_name); g_free(clint_cells); @@ -372,7 +372,7 @@ static void create_fdt_socket_aclint(RISCVVirtState *s, aclint_mswi_cells, aclint_cells_size); qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0); qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0); - riscv_socket_fdt_write_id(mc, mc->fdt, name, socket); + riscv_socket_fdt_write_id(mc, name, socket); g_free(name); } @@ -396,7 +396,7 @@ static void create_fdt_socket_aclint(RISCVVirtState *s, 0x0, RISCV_ACLINT_DEFAULT_MTIME); qemu_fdt_setprop(mc->fdt, name, "interrupts-extended", aclint_mtimer_cells, aclint_cells_size); - riscv_socket_fdt_write_id(mc, mc->fdt, name, socket); + riscv_socket_fdt_write_id(mc, name, socket); g_free(name); if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) { @@ -412,7 +412,7 @@ static void create_fdt_socket_aclint(RISCVVirtState *s, aclint_sswi_cells, aclint_cells_size); qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0); qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0); - riscv_socket_fdt_write_id(mc, mc->fdt, name, socket); + riscv_socket_fdt_write_id(mc, name, socket); g_free(name); } @@ -471,7 +471,7 @@ static void create_fdt_socket_plic(RISCVVirtState *s, 0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size); qemu_fdt_setprop_cell(mc->fdt, plic_name, "riscv,ndev", VIRT_IRQCHIP_NUM_SOURCES - 1); - riscv_socket_fdt_write_id(mc, mc->fdt, plic_name, socket); + riscv_socket_fdt_write_id(mc, plic_name, socket); qemu_fdt_setprop_cell(mc->fdt, plic_name, "phandle", plic_phandles[socket]); @@ -663,7 +663,7 @@ static void create_fdt_socket_aplic(RISCVVirtState *s, aplic_s_phandle); qemu_fdt_setprop_cells(mc->fdt, aplic_name, "riscv,delegate", aplic_s_phandle, 0x1, VIRT_IRQCHIP_NUM_SOURCES); - riscv_socket_fdt_write_id(mc, mc->fdt, aplic_name, socket); + riscv_socket_fdt_write_id(mc, aplic_name, socket); qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_m_phandle); g_free(aplic_name); @@ -691,7 +691,7 @@ static void create_fdt_socket_aplic(RISCVVirtState *s, 0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_S].size); qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources", VIRT_IRQCHIP_NUM_SOURCES); - riscv_socket_fdt_write_id(mc, mc->fdt, aplic_name, socket); + riscv_socket_fdt_write_id(mc, aplic_name, socket); qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_s_phandle); if (!socket) { diff --git a/include/hw/riscv/numa.h b/include/hw/riscv/numa.h index 1a9cce3344..634df6673f 100644 --- a/include/hw/riscv/numa.h +++ b/include/hw/riscv/numa.h @@ -90,10 +90,10 @@ bool riscv_socket_check_hartids(const MachineState *ms, int socket_id); * @ms: pointer to machine state * @socket_id: socket index * - * Write NUMA node-id FDT property for given FDT node + * Write NUMA node-id FDT property in MachineState->fdt */ -void riscv_socket_fdt_write_id(const MachineState *ms, void *fdt, - const char *node_name, int socket_id); +void riscv_socket_fdt_write_id(const MachineState *ms, const char *node_name, + int socket_id); /** * riscv_socket_fdt_write_distance_matrix: -- 2.39.0 ^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [PATCH 05/10] hw/riscv: use MachineState::fdt in riscv_socket_fdt_write_id() 2023-01-11 17:09 ` [PATCH 05/10] hw/riscv: use MachineState::fdt in riscv_socket_fdt_write_id() Daniel Henrique Barboza @ 2023-01-16 4:01 ` Alistair Francis 0 siblings, 0 replies; 20+ messages in thread From: Alistair Francis @ 2023-01-16 4:01 UTC (permalink / raw) To: Daniel Henrique Barboza; +Cc: qemu-devel, qemu-riscv, alistair.francis On Thu, Jan 12, 2023 at 3:28 AM Daniel Henrique Barboza <dbarboza@ventanamicro.com> wrote: > > There's no need to use a MachineState pointer and a fdt pointer now that > all RISC-V machines are using the FDT from the MachineState. > > Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > hw/riscv/numa.c | 6 +++--- > hw/riscv/spike.c | 6 +++--- > hw/riscv/virt.c | 18 +++++++++--------- > include/hw/riscv/numa.h | 6 +++--- > 4 files changed, 18 insertions(+), 18 deletions(-) > > diff --git a/hw/riscv/numa.c b/hw/riscv/numa.c > index 7fe92d402f..f4343f5cde 100644 > --- a/hw/riscv/numa.c > +++ b/hw/riscv/numa.c > @@ -156,11 +156,11 @@ uint64_t riscv_socket_mem_size(const MachineState *ms, int socket_id) > ms->numa_state->nodes[socket_id].node_mem : 0; > } > > -void riscv_socket_fdt_write_id(const MachineState *ms, void *fdt, > - const char *node_name, int socket_id) > +void riscv_socket_fdt_write_id(const MachineState *ms, const char *node_name, > + int socket_id) > { > if (numa_enabled(ms)) { > - qemu_fdt_setprop_cell(fdt, node_name, "numa-node-id", socket_id); > + qemu_fdt_setprop_cell(ms->fdt, node_name, "numa-node-id", socket_id); > } > } > > diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c > index 4a66016d69..05d34651cb 100644 > --- a/hw/riscv/spike.c > +++ b/hw/riscv/spike.c > @@ -121,7 +121,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, > qemu_fdt_setprop_cell(fdt, cpu_name, "reg", > s->soc[socket].hartid_base + cpu); > qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu"); > - riscv_socket_fdt_write_id(mc, fdt, cpu_name, socket); > + riscv_socket_fdt_write_id(mc, cpu_name, socket); > qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle); > > intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name); > @@ -154,7 +154,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, > qemu_fdt_setprop_cells(fdt, mem_name, "reg", > addr >> 32, addr, size >> 32, size); > qemu_fdt_setprop_string(fdt, mem_name, "device_type", "memory"); > - riscv_socket_fdt_write_id(mc, fdt, mem_name, socket); > + riscv_socket_fdt_write_id(mc, mem_name, socket); > g_free(mem_name); > > clint_addr = memmap[SPIKE_CLINT].base + > @@ -167,7 +167,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, > 0x0, clint_addr, 0x0, memmap[SPIKE_CLINT].size); > qemu_fdt_setprop(fdt, clint_name, "interrupts-extended", > clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); > - riscv_socket_fdt_write_id(mc, fdt, clint_name, socket); > + riscv_socket_fdt_write_id(mc, clint_name, socket); > > g_free(clint_name); > g_free(clint_cells); > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c > index 99a0a43a73..1d3bd25cb5 100644 > --- a/hw/riscv/virt.c > +++ b/hw/riscv/virt.c > @@ -253,7 +253,7 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, > qemu_fdt_setprop_cell(mc->fdt, cpu_name, "reg", > s->soc[socket].hartid_base + cpu); > qemu_fdt_setprop_string(mc->fdt, cpu_name, "device_type", "cpu"); > - riscv_socket_fdt_write_id(mc, mc->fdt, cpu_name, socket); > + riscv_socket_fdt_write_id(mc, cpu_name, socket); > qemu_fdt_setprop_cell(mc->fdt, cpu_name, "phandle", cpu_phandle); > > intc_phandles[cpu] = (*phandle)++; > @@ -291,7 +291,7 @@ static void create_fdt_socket_memory(RISCVVirtState *s, > qemu_fdt_setprop_cells(mc->fdt, mem_name, "reg", > addr >> 32, addr, size >> 32, size); > qemu_fdt_setprop_string(mc->fdt, mem_name, "device_type", "memory"); > - riscv_socket_fdt_write_id(mc, mc->fdt, mem_name, socket); > + riscv_socket_fdt_write_id(mc, mem_name, socket); > g_free(mem_name); > } > > @@ -327,7 +327,7 @@ static void create_fdt_socket_clint(RISCVVirtState *s, > 0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size); > qemu_fdt_setprop(mc->fdt, clint_name, "interrupts-extended", > clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); > - riscv_socket_fdt_write_id(mc, mc->fdt, clint_name, socket); > + riscv_socket_fdt_write_id(mc, clint_name, socket); > g_free(clint_name); > > g_free(clint_cells); > @@ -372,7 +372,7 @@ static void create_fdt_socket_aclint(RISCVVirtState *s, > aclint_mswi_cells, aclint_cells_size); > qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0); > qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0); > - riscv_socket_fdt_write_id(mc, mc->fdt, name, socket); > + riscv_socket_fdt_write_id(mc, name, socket); > g_free(name); > } > > @@ -396,7 +396,7 @@ static void create_fdt_socket_aclint(RISCVVirtState *s, > 0x0, RISCV_ACLINT_DEFAULT_MTIME); > qemu_fdt_setprop(mc->fdt, name, "interrupts-extended", > aclint_mtimer_cells, aclint_cells_size); > - riscv_socket_fdt_write_id(mc, mc->fdt, name, socket); > + riscv_socket_fdt_write_id(mc, name, socket); > g_free(name); > > if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) { > @@ -412,7 +412,7 @@ static void create_fdt_socket_aclint(RISCVVirtState *s, > aclint_sswi_cells, aclint_cells_size); > qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0); > qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0); > - riscv_socket_fdt_write_id(mc, mc->fdt, name, socket); > + riscv_socket_fdt_write_id(mc, name, socket); > g_free(name); > } > > @@ -471,7 +471,7 @@ static void create_fdt_socket_plic(RISCVVirtState *s, > 0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size); > qemu_fdt_setprop_cell(mc->fdt, plic_name, "riscv,ndev", > VIRT_IRQCHIP_NUM_SOURCES - 1); > - riscv_socket_fdt_write_id(mc, mc->fdt, plic_name, socket); > + riscv_socket_fdt_write_id(mc, plic_name, socket); > qemu_fdt_setprop_cell(mc->fdt, plic_name, "phandle", > plic_phandles[socket]); > > @@ -663,7 +663,7 @@ static void create_fdt_socket_aplic(RISCVVirtState *s, > aplic_s_phandle); > qemu_fdt_setprop_cells(mc->fdt, aplic_name, "riscv,delegate", > aplic_s_phandle, 0x1, VIRT_IRQCHIP_NUM_SOURCES); > - riscv_socket_fdt_write_id(mc, mc->fdt, aplic_name, socket); > + riscv_socket_fdt_write_id(mc, aplic_name, socket); > qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_m_phandle); > g_free(aplic_name); > > @@ -691,7 +691,7 @@ static void create_fdt_socket_aplic(RISCVVirtState *s, > 0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_S].size); > qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources", > VIRT_IRQCHIP_NUM_SOURCES); > - riscv_socket_fdt_write_id(mc, mc->fdt, aplic_name, socket); > + riscv_socket_fdt_write_id(mc, aplic_name, socket); > qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_s_phandle); > > if (!socket) { > diff --git a/include/hw/riscv/numa.h b/include/hw/riscv/numa.h > index 1a9cce3344..634df6673f 100644 > --- a/include/hw/riscv/numa.h > +++ b/include/hw/riscv/numa.h > @@ -90,10 +90,10 @@ bool riscv_socket_check_hartids(const MachineState *ms, int socket_id); > * @ms: pointer to machine state > * @socket_id: socket index > * > - * Write NUMA node-id FDT property for given FDT node > + * Write NUMA node-id FDT property in MachineState->fdt > */ > -void riscv_socket_fdt_write_id(const MachineState *ms, void *fdt, > - const char *node_name, int socket_id); > +void riscv_socket_fdt_write_id(const MachineState *ms, const char *node_name, > + int socket_id); > > /** > * riscv_socket_fdt_write_distance_matrix: > -- > 2.39.0 > > ^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 06/10] hw/riscv: use ms->fdt in riscv_socket_fdt_write_distance_matrix() 2023-01-11 17:09 [PATCH 00/10] riscv: create_fdt() related cleanups Daniel Henrique Barboza ` (4 preceding siblings ...) 2023-01-11 17:09 ` [PATCH 05/10] hw/riscv: use MachineState::fdt in riscv_socket_fdt_write_id() Daniel Henrique Barboza @ 2023-01-11 17:09 ` Daniel Henrique Barboza 2023-01-16 4:04 ` Alistair Francis 2023-01-11 17:09 ` [PATCH 07/10] hw/riscv: simplify riscv_load_fdt() Daniel Henrique Barboza ` (5 subsequent siblings) 11 siblings, 1 reply; 20+ messages in thread From: Daniel Henrique Barboza @ 2023-01-11 17:09 UTC (permalink / raw) To: qemu-devel; +Cc: qemu-riscv, alistair.francis, Daniel Henrique Barboza There's no need to use a MachineState pointer and a fdt pointer now that all RISC-V machines are using the FDT from the MachineState. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> --- hw/riscv/numa.c | 8 ++++---- hw/riscv/spike.c | 2 +- hw/riscv/virt.c | 2 +- include/hw/riscv/numa.h | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/hw/riscv/numa.c b/hw/riscv/numa.c index f4343f5cde..4720102561 100644 --- a/hw/riscv/numa.c +++ b/hw/riscv/numa.c @@ -164,7 +164,7 @@ void riscv_socket_fdt_write_id(const MachineState *ms, const char *node_name, } } -void riscv_socket_fdt_write_distance_matrix(const MachineState *ms, void *fdt) +void riscv_socket_fdt_write_distance_matrix(const MachineState *ms) { int i, j, idx; uint32_t *dist_matrix, dist_matrix_size; @@ -184,10 +184,10 @@ void riscv_socket_fdt_write_distance_matrix(const MachineState *ms, void *fdt) } } - qemu_fdt_add_subnode(fdt, "/distance-map"); - qemu_fdt_setprop_string(fdt, "/distance-map", "compatible", + qemu_fdt_add_subnode(ms->fdt, "/distance-map"); + qemu_fdt_setprop_string(ms->fdt, "/distance-map", "compatible", "numa-distance-map-v1"); - qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", + qemu_fdt_setprop(ms->fdt, "/distance-map", "distance-matrix", dist_matrix, dist_matrix_size); g_free(dist_matrix); } diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 05d34651cb..91bf194ec1 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -174,7 +174,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, g_free(clust_name); } - riscv_socket_fdt_write_distance_matrix(mc, fdt); + riscv_socket_fdt_write_distance_matrix(mc); qemu_fdt_add_subnode(fdt, "/chosen"); qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", "/htif"); diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 1d3bd25cb5..e374b58f89 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -805,7 +805,7 @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, } } - riscv_socket_fdt_write_distance_matrix(mc, mc->fdt); + riscv_socket_fdt_write_distance_matrix(mc); } static void create_fdt_virtio(RISCVVirtState *s, const MemMapEntry *memmap, diff --git a/include/hw/riscv/numa.h b/include/hw/riscv/numa.h index 634df6673f..8f5280211d 100644 --- a/include/hw/riscv/numa.h +++ b/include/hw/riscv/numa.h @@ -100,9 +100,9 @@ void riscv_socket_fdt_write_id(const MachineState *ms, const char *node_name, * @ms: pointer to machine state * @socket_id: socket index * - * Write NUMA distance matrix in FDT for given machine + * Write NUMA distance matrix in MachineState->fdt */ -void riscv_socket_fdt_write_distance_matrix(const MachineState *ms, void *fdt); +void riscv_socket_fdt_write_distance_matrix(const MachineState *ms); CpuInstanceProperties riscv_numa_cpu_index_to_props(MachineState *ms, unsigned cpu_index); -- 2.39.0 ^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [PATCH 06/10] hw/riscv: use ms->fdt in riscv_socket_fdt_write_distance_matrix() 2023-01-11 17:09 ` [PATCH 06/10] hw/riscv: use ms->fdt in riscv_socket_fdt_write_distance_matrix() Daniel Henrique Barboza @ 2023-01-16 4:04 ` Alistair Francis 0 siblings, 0 replies; 20+ messages in thread From: Alistair Francis @ 2023-01-16 4:04 UTC (permalink / raw) To: Daniel Henrique Barboza; +Cc: qemu-devel, qemu-riscv, alistair.francis On Thu, Jan 12, 2023 at 3:26 AM Daniel Henrique Barboza <dbarboza@ventanamicro.com> wrote: > > There's no need to use a MachineState pointer and a fdt pointer now that > all RISC-V machines are using the FDT from the MachineState. > > Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > hw/riscv/numa.c | 8 ++++---- > hw/riscv/spike.c | 2 +- > hw/riscv/virt.c | 2 +- > include/hw/riscv/numa.h | 4 ++-- > 4 files changed, 8 insertions(+), 8 deletions(-) > > diff --git a/hw/riscv/numa.c b/hw/riscv/numa.c > index f4343f5cde..4720102561 100644 > --- a/hw/riscv/numa.c > +++ b/hw/riscv/numa.c > @@ -164,7 +164,7 @@ void riscv_socket_fdt_write_id(const MachineState *ms, const char *node_name, > } > } > > -void riscv_socket_fdt_write_distance_matrix(const MachineState *ms, void *fdt) > +void riscv_socket_fdt_write_distance_matrix(const MachineState *ms) > { > int i, j, idx; > uint32_t *dist_matrix, dist_matrix_size; > @@ -184,10 +184,10 @@ void riscv_socket_fdt_write_distance_matrix(const MachineState *ms, void *fdt) > } > } > > - qemu_fdt_add_subnode(fdt, "/distance-map"); > - qemu_fdt_setprop_string(fdt, "/distance-map", "compatible", > + qemu_fdt_add_subnode(ms->fdt, "/distance-map"); > + qemu_fdt_setprop_string(ms->fdt, "/distance-map", "compatible", > "numa-distance-map-v1"); > - qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", > + qemu_fdt_setprop(ms->fdt, "/distance-map", "distance-matrix", > dist_matrix, dist_matrix_size); > g_free(dist_matrix); > } > diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c > index 05d34651cb..91bf194ec1 100644 > --- a/hw/riscv/spike.c > +++ b/hw/riscv/spike.c > @@ -174,7 +174,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, > g_free(clust_name); > } > > - riscv_socket_fdt_write_distance_matrix(mc, fdt); > + riscv_socket_fdt_write_distance_matrix(mc); > > qemu_fdt_add_subnode(fdt, "/chosen"); > qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", "/htif"); > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c > index 1d3bd25cb5..e374b58f89 100644 > --- a/hw/riscv/virt.c > +++ b/hw/riscv/virt.c > @@ -805,7 +805,7 @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, > } > } > > - riscv_socket_fdt_write_distance_matrix(mc, mc->fdt); > + riscv_socket_fdt_write_distance_matrix(mc); > } > > static void create_fdt_virtio(RISCVVirtState *s, const MemMapEntry *memmap, > diff --git a/include/hw/riscv/numa.h b/include/hw/riscv/numa.h > index 634df6673f..8f5280211d 100644 > --- a/include/hw/riscv/numa.h > +++ b/include/hw/riscv/numa.h > @@ -100,9 +100,9 @@ void riscv_socket_fdt_write_id(const MachineState *ms, const char *node_name, > * @ms: pointer to machine state > * @socket_id: socket index > * > - * Write NUMA distance matrix in FDT for given machine > + * Write NUMA distance matrix in MachineState->fdt > */ > -void riscv_socket_fdt_write_distance_matrix(const MachineState *ms, void *fdt); > +void riscv_socket_fdt_write_distance_matrix(const MachineState *ms); > > CpuInstanceProperties > riscv_numa_cpu_index_to_props(MachineState *ms, unsigned cpu_index); > -- > 2.39.0 > > ^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 07/10] hw/riscv: simplify riscv_load_fdt() 2023-01-11 17:09 [PATCH 00/10] riscv: create_fdt() related cleanups Daniel Henrique Barboza ` (5 preceding siblings ...) 2023-01-11 17:09 ` [PATCH 06/10] hw/riscv: use ms->fdt in riscv_socket_fdt_write_distance_matrix() Daniel Henrique Barboza @ 2023-01-11 17:09 ` Daniel Henrique Barboza 2023-01-12 7:33 ` Philippe Mathieu-Daudé 2023-01-11 17:09 ` [PATCH 08/10] hw/riscv/virt.c: calculate socket count once in create_fdt_imsic() Daniel Henrique Barboza ` (4 subsequent siblings) 11 siblings, 1 reply; 20+ messages in thread From: Daniel Henrique Barboza @ 2023-01-11 17:09 UTC (permalink / raw) To: qemu-devel; +Cc: qemu-riscv, alistair.francis, Daniel Henrique Barboza All callers of riscv_load_fdt() are using machine->ram_size as 'mem_size' and the fdt is always retrievable via machine->fdt. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> --- hw/riscv/boot.c | 4 +++- hw/riscv/microchip_pfsoc.c | 4 ++-- hw/riscv/sifive_u.c | 3 +-- hw/riscv/spike.c | 3 +-- hw/riscv/virt.c | 3 +-- include/hw/riscv/boot.h | 2 +- 6 files changed, 9 insertions(+), 10 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index e868fb6ade..21dea7eac2 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -265,10 +265,12 @@ out: return kernel_entry; } -uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt) +uint64_t riscv_load_fdt(MachineState *ms, hwaddr dram_base) { uint64_t temp, fdt_addr; + uint64_t mem_size = ms->ram_size; hwaddr dram_end = dram_base + mem_size; + void *fdt = ms->fdt; int ret, fdtsize = fdt_totalsize(fdt); if (fdtsize <= 0) { diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index c45023a2b1..6bb08f66bd 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -633,8 +633,8 @@ static void microchip_icicle_kit_machine_init(MachineState *machine) true, NULL); /* Compute the fdt load address in dram */ - fdt_load_addr = riscv_load_fdt(memmap[MICROCHIP_PFSOC_DRAM_LO].base, - machine->ram_size, machine->fdt); + fdt_load_addr = riscv_load_fdt(machine, + memmap[MICROCHIP_PFSOC_DRAM_LO].base); /* Load the reset vector */ riscv_setup_rom_reset_vec(machine, &s->soc.u_cpus, firmware_load_addr, memmap[MICROCHIP_PFSOC_ENVM_DATA].base, diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index ccad386920..fc2a8a7af4 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -609,8 +609,7 @@ static void sifive_u_machine_init(MachineState *machine) } /* Compute the fdt load address in dram */ - fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DEV_DRAM].base, - machine->ram_size, machine->fdt); + fdt_load_addr = riscv_load_fdt(machine, memmap[SIFIVE_U_DEV_DRAM].base); if (!riscv_is_32bit(&s->soc.u_cpus)) { start_addr_hi32 = (uint64_t)start_addr >> 32; } diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 91bf194ec1..82093dd2cb 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -316,8 +316,7 @@ static void spike_board_init(MachineState *machine) } /* Compute the fdt load address in dram */ - fdt_load_addr = riscv_load_fdt(memmap[SPIKE_DRAM].base, - machine->ram_size, machine->fdt); + fdt_load_addr = riscv_load_fdt(machine, memmap[SPIKE_DRAM].base); /* load the reset vector */ riscv_setup_rom_reset_vec(machine, &s->soc[0], memmap[SPIKE_DRAM].base, diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index e374b58f89..0a0252368e 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1300,8 +1300,7 @@ static void virt_machine_done(Notifier *notifier, void *data) } /* Compute the fdt load address in dram */ - fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base, - machine->ram_size, machine->fdt); + fdt_load_addr = riscv_load_fdt(machine, memmap[VIRT_DRAM].base); /* load the reset vector */ riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr, virt_memmap[VIRT_MROM].base, diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index cbd131bad7..3581bbe447 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -47,7 +47,7 @@ target_ulong riscv_load_kernel(MachineState *machine, target_ulong firmware_end_addr, bool load_initrd, symbol_fn_t sym_cb); -uint64_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt); +uint64_t riscv_load_fdt(MachineState *ms, hwaddr dram_start); void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts, hwaddr saddr, hwaddr rom_base, hwaddr rom_size, -- 2.39.0 ^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [PATCH 07/10] hw/riscv: simplify riscv_load_fdt() 2023-01-11 17:09 ` [PATCH 07/10] hw/riscv: simplify riscv_load_fdt() Daniel Henrique Barboza @ 2023-01-12 7:33 ` Philippe Mathieu-Daudé 0 siblings, 0 replies; 20+ messages in thread From: Philippe Mathieu-Daudé @ 2023-01-12 7:33 UTC (permalink / raw) To: Daniel Henrique Barboza, qemu-devel; +Cc: qemu-riscv, alistair.francis On 11/1/23 18:09, Daniel Henrique Barboza wrote: > All callers of riscv_load_fdt() are using machine->ram_size as > 'mem_size' and the fdt is always retrievable via machine->fdt. > > Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > --- > hw/riscv/boot.c | 4 +++- > hw/riscv/microchip_pfsoc.c | 4 ++-- > hw/riscv/sifive_u.c | 3 +-- > hw/riscv/spike.c | 3 +-- > hw/riscv/virt.c | 3 +-- > include/hw/riscv/boot.h | 2 +- > 6 files changed, 9 insertions(+), 10 deletions(-) > > diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c > index e868fb6ade..21dea7eac2 100644 > --- a/hw/riscv/boot.c > +++ b/hw/riscv/boot.c > @@ -265,10 +265,12 @@ out: > return kernel_entry; > } > > -uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt) > +uint64_t riscv_load_fdt(MachineState *ms, hwaddr dram_base) > { > uint64_t temp, fdt_addr; > + uint64_t mem_size = ms->ram_size; > hwaddr dram_end = dram_base + mem_size; What about sparse memory ...? > if (fdtsize <= 0) { > diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c > index c45023a2b1..6bb08f66bd 100644 > --- a/hw/riscv/microchip_pfsoc.c > +++ b/hw/riscv/microchip_pfsoc.c > @@ -633,8 +633,8 @@ static void microchip_icicle_kit_machine_init(MachineState *machine) > true, NULL); > > /* Compute the fdt load address in dram */ > - fdt_load_addr = riscv_load_fdt(memmap[MICROCHIP_PFSOC_DRAM_LO].base, > - machine->ram_size, machine->fdt); > + fdt_load_addr = riscv_load_fdt(machine, > + memmap[MICROCHIP_PFSOC_DRAM_LO].base); ... i.e: hw/riscv/microchip_pfsoc.c: [MICROCHIP_PFSOC_DRAM_LO] = { 0x80000000, 0x40000000 }, hw/riscv/microchip_pfsoc.c: [MICROCHIP_PFSOC_DRAM_HI] = { 0x1000000000, 0x0 }, IIUC FDT is always loaded into a contiguous region, so maybe simply 'dram_base' is a bad name for '[fdt_]load_address'? 'mem_size' is used to calculate 'dram_end'... This function seems buggy. We should pass either start_addr/end_addr or base/size, but the range passed must be contiguous. ^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 08/10] hw/riscv/virt.c: calculate socket count once in create_fdt_imsic() 2023-01-11 17:09 [PATCH 00/10] riscv: create_fdt() related cleanups Daniel Henrique Barboza ` (6 preceding siblings ...) 2023-01-11 17:09 ` [PATCH 07/10] hw/riscv: simplify riscv_load_fdt() Daniel Henrique Barboza @ 2023-01-11 17:09 ` Daniel Henrique Barboza 2023-01-11 17:09 ` [PATCH 09/10] hw/riscv/virt.c: rename MachineState 'mc' pointers to 'ms' Daniel Henrique Barboza ` (3 subsequent siblings) 11 siblings, 0 replies; 20+ messages in thread From: Daniel Henrique Barboza @ 2023-01-11 17:09 UTC (permalink / raw) To: qemu-devel; +Cc: qemu-riscv, alistair.francis, Daniel Henrique Barboza riscv_socket_count() returns either ms->numa_state->num_nodes or 1 depending on NUMA support. In any case the value can be retrieved only once and used in the rest of the function. This will also alleviate the rename we're going to do next by reducing the instances of MachineState 'mc' inside hw/riscv/virt.c. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> --- hw/riscv/virt.c | 34 +++++++++++++++++++--------------- 1 file changed, 19 insertions(+), 15 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 0a0252368e..f9bdf2a70b 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -505,13 +505,14 @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, int cpu, socket; char *imsic_name; MachineState *mc = MACHINE(s); + int socket_count = riscv_socket_count(mc); uint32_t imsic_max_hart_per_socket, imsic_guest_bits; uint32_t *imsic_cells, *imsic_regs, imsic_addr, imsic_size; *msi_m_phandle = (*phandle)++; *msi_s_phandle = (*phandle)++; imsic_cells = g_new0(uint32_t, mc->smp.cpus * 2); - imsic_regs = g_new0(uint32_t, riscv_socket_count(mc) * 4); + imsic_regs = g_new0(uint32_t, socket_count * 4); /* M-level IMSIC node */ for (cpu = 0; cpu < mc->smp.cpus; cpu++) { @@ -519,7 +520,7 @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, imsic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_EXT); } imsic_max_hart_per_socket = 0; - for (socket = 0; socket < riscv_socket_count(mc); socket++) { + for (socket = 0; socket < socket_count; socket++) { imsic_addr = memmap[VIRT_IMSIC_M].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE; imsic_size = IMSIC_HART_SIZE(0) * s->soc[socket].num_harts; @@ -545,14 +546,14 @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended", imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2); qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs, - riscv_socket_count(mc) * sizeof(uint32_t) * 4); + socket_count * sizeof(uint32_t) * 4); qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids", VIRT_IRQCHIP_NUM_MSIS); - if (riscv_socket_count(mc) > 1) { + if (socket_count > 1) { qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits", imsic_num_bits(imsic_max_hart_per_socket)); qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bits", - imsic_num_bits(riscv_socket_count(mc))); + imsic_num_bits(socket_count)); qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-shift", IMSIC_MMIO_GROUP_MIN_SHIFT); } @@ -567,7 +568,7 @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, } imsic_guest_bits = imsic_num_bits(s->aia_guests + 1); imsic_max_hart_per_socket = 0; - for (socket = 0; socket < riscv_socket_count(mc); socket++) { + for (socket = 0; socket < socket_count; socket++) { imsic_addr = memmap[VIRT_IMSIC_S].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE; imsic_size = IMSIC_HART_SIZE(imsic_guest_bits) * @@ -594,18 +595,18 @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended", imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2); qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs, - riscv_socket_count(mc) * sizeof(uint32_t) * 4); + socket_count * sizeof(uint32_t) * 4); qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids", VIRT_IRQCHIP_NUM_MSIS); if (imsic_guest_bits) { qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,guest-index-bits", imsic_guest_bits); } - if (riscv_socket_count(mc) > 1) { + if (socket_count > 1) { qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits", imsic_num_bits(imsic_max_hart_per_socket)); qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bits", - imsic_num_bits(riscv_socket_count(mc))); + imsic_num_bits(socket_count)); qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-shift", IMSIC_MMIO_GROUP_MIN_SHIFT); } @@ -733,6 +734,7 @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, MachineState *mc = MACHINE(s); uint32_t msi_m_phandle = 0, msi_s_phandle = 0; uint32_t *intc_phandles, xplic_phandles[MAX_NODES]; + int socket_count = riscv_socket_count(mc); qemu_fdt_add_subnode(mc->fdt, "/cpus"); qemu_fdt_setprop_cell(mc->fdt, "/cpus", "timebase-frequency", @@ -744,7 +746,7 @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, intc_phandles = g_new0(uint32_t, mc->smp.cpus); phandle_pos = mc->smp.cpus; - for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) { + for (socket = (socket_count - 1); socket >= 0; socket--) { phandle_pos -= s->soc[socket].num_harts; clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket); @@ -775,7 +777,7 @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, } phandle_pos = mc->smp.cpus; - for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) { + for (socket = (socket_count - 1); socket >= 0; socket--) { phandle_pos -= s->soc[socket].num_harts; if (s->aia_type == VIRT_AIA_TYPE_NONE) { @@ -790,7 +792,7 @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, g_free(intc_phandles); - for (socket = 0; socket < riscv_socket_count(mc); socket++) { + for (socket = 0; socket < socket_count; socket++) { if (socket == 0) { *irq_mmio_phandle = xplic_phandles[socket]; *irq_virtio_phandle = xplic_phandles[socket]; @@ -1051,7 +1053,8 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap) /* Pass seed to RNG */ qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed)); - qemu_fdt_setprop(mc->fdt, "/chosen", "rng-seed", rng_seed, sizeof(rng_seed)); + qemu_fdt_setprop(mc->fdt, "/chosen", "rng-seed", + rng_seed, sizeof(rng_seed)); } static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, @@ -1326,9 +1329,10 @@ static void virt_machine_init(MachineState *machine) char *soc_name; DeviceState *mmio_irqchip, *virtio_irqchip, *pcie_irqchip; int i, base_hartid, hart_count; + int socket_count = riscv_socket_count(machine); /* Check socket count limit */ - if (VIRT_SOCKETS_MAX < riscv_socket_count(machine)) { + if (VIRT_SOCKETS_MAX < socket_count) { error_report("number of sockets/nodes should be less than %d", VIRT_SOCKETS_MAX); exit(1); @@ -1336,7 +1340,7 @@ static void virt_machine_init(MachineState *machine) /* Initialize sockets */ mmio_irqchip = virtio_irqchip = pcie_irqchip = NULL; - for (i = 0; i < riscv_socket_count(machine); i++) { + for (i = 0; i < socket_count; i++) { if (!riscv_socket_check_hartids(machine, i)) { error_report("discontinuous hartids in socket%d", i); exit(1); -- 2.39.0 ^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 09/10] hw/riscv/virt.c: rename MachineState 'mc' pointers to 'ms' 2023-01-11 17:09 [PATCH 00/10] riscv: create_fdt() related cleanups Daniel Henrique Barboza ` (7 preceding siblings ...) 2023-01-11 17:09 ` [PATCH 08/10] hw/riscv/virt.c: calculate socket count once in create_fdt_imsic() Daniel Henrique Barboza @ 2023-01-11 17:09 ` Daniel Henrique Barboza 2023-01-11 17:09 ` [PATCH 10/10] hw/riscv/spike.c: rename MachineState 'mc' pointers to' ms' Daniel Henrique Barboza ` (2 subsequent siblings) 11 siblings, 0 replies; 20+ messages in thread From: Daniel Henrique Barboza @ 2023-01-11 17:09 UTC (permalink / raw) To: qemu-devel Cc: qemu-riscv, alistair.francis, Daniel Henrique Barboza, Philippe Mathieu-Daudé We have a convention in other QEMU boards/archs to name MachineState pointers as either 'machine' or 'ms'. MachineClass pointers are usually called 'mc'. The 'virt' RISC-V machine has a lot of instances where MachineState pointers are named 'mc'. There is nothing wrong with that, but we gain more compatibility with the rest of the QEMU code base, and easier reviews, if we follow QEMU conventions. Rename all 'mc' MachineState pointers to 'ms'. This is a very tedious and mechanical patch that was produced by doing the following: - find/replace all 'MachineState *mc' to 'MachineState *ms'; - find/replace all 'mc->fdt' to 'ms->fdt'; - find/replace all 'mc->smp.cpus' to 'ms->smp.cpus'; - replace any remaining occurrences of 'mc' that the compiler complained about. Suggested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> --- hw/riscv/virt.c | 434 ++++++++++++++++++++++++------------------------ 1 file changed, 217 insertions(+), 217 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index f9bdf2a70b..3b73666d2a 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -227,7 +227,7 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, { int cpu; uint32_t cpu_phandle; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); char *name, *cpu_name, *core_name, *intc_name; bool is_32_bit = riscv_is_32bit(&s->soc[0]); @@ -236,40 +236,40 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, cpu_name = g_strdup_printf("/cpus/cpu@%d", s->soc[socket].hartid_base + cpu); - qemu_fdt_add_subnode(mc->fdt, cpu_name); + qemu_fdt_add_subnode(ms->fdt, cpu_name); if (riscv_feature(&s->soc[socket].harts[cpu].env, RISCV_FEATURE_MMU)) { - qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", + qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type", (is_32_bit) ? "riscv,sv32" : "riscv,sv48"); } else { - qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", + qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type", "riscv,none"); } name = riscv_isa_string(&s->soc[socket].harts[cpu]); - qemu_fdt_setprop_string(mc->fdt, cpu_name, "riscv,isa", name); + qemu_fdt_setprop_string(ms->fdt, cpu_name, "riscv,isa", name); g_free(name); - qemu_fdt_setprop_string(mc->fdt, cpu_name, "compatible", "riscv"); - qemu_fdt_setprop_string(mc->fdt, cpu_name, "status", "okay"); - qemu_fdt_setprop_cell(mc->fdt, cpu_name, "reg", + qemu_fdt_setprop_string(ms->fdt, cpu_name, "compatible", "riscv"); + qemu_fdt_setprop_string(ms->fdt, cpu_name, "status", "okay"); + qemu_fdt_setprop_cell(ms->fdt, cpu_name, "reg", s->soc[socket].hartid_base + cpu); - qemu_fdt_setprop_string(mc->fdt, cpu_name, "device_type", "cpu"); - riscv_socket_fdt_write_id(mc, cpu_name, socket); - qemu_fdt_setprop_cell(mc->fdt, cpu_name, "phandle", cpu_phandle); + qemu_fdt_setprop_string(ms->fdt, cpu_name, "device_type", "cpu"); + riscv_socket_fdt_write_id(ms, cpu_name, socket); + qemu_fdt_setprop_cell(ms->fdt, cpu_name, "phandle", cpu_phandle); intc_phandles[cpu] = (*phandle)++; intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name); - qemu_fdt_add_subnode(mc->fdt, intc_name); - qemu_fdt_setprop_cell(mc->fdt, intc_name, "phandle", + qemu_fdt_add_subnode(ms->fdt, intc_name); + qemu_fdt_setprop_cell(ms->fdt, intc_name, "phandle", intc_phandles[cpu]); - qemu_fdt_setprop_string(mc->fdt, intc_name, "compatible", + qemu_fdt_setprop_string(ms->fdt, intc_name, "compatible", "riscv,cpu-intc"); - qemu_fdt_setprop(mc->fdt, intc_name, "interrupt-controller", NULL, 0); - qemu_fdt_setprop_cell(mc->fdt, intc_name, "#interrupt-cells", 1); + qemu_fdt_setprop(ms->fdt, intc_name, "interrupt-controller", NULL, 0); + qemu_fdt_setprop_cell(ms->fdt, intc_name, "#interrupt-cells", 1); core_name = g_strdup_printf("%s/core%d", clust_name, cpu); - qemu_fdt_add_subnode(mc->fdt, core_name); - qemu_fdt_setprop_cell(mc->fdt, core_name, "cpu", cpu_phandle); + qemu_fdt_add_subnode(ms->fdt, core_name); + qemu_fdt_setprop_cell(ms->fdt, core_name, "cpu", cpu_phandle); g_free(core_name); g_free(intc_name); @@ -282,16 +282,16 @@ static void create_fdt_socket_memory(RISCVVirtState *s, { char *mem_name; uint64_t addr, size; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); - addr = memmap[VIRT_DRAM].base + riscv_socket_mem_offset(mc, socket); - size = riscv_socket_mem_size(mc, socket); + addr = memmap[VIRT_DRAM].base + riscv_socket_mem_offset(ms, socket); + size = riscv_socket_mem_size(ms, socket); mem_name = g_strdup_printf("/memory@%lx", (long)addr); - qemu_fdt_add_subnode(mc->fdt, mem_name); - qemu_fdt_setprop_cells(mc->fdt, mem_name, "reg", + qemu_fdt_add_subnode(ms->fdt, mem_name); + qemu_fdt_setprop_cells(ms->fdt, mem_name, "reg", addr >> 32, addr, size >> 32, size); - qemu_fdt_setprop_string(mc->fdt, mem_name, "device_type", "memory"); - riscv_socket_fdt_write_id(mc, mem_name, socket); + qemu_fdt_setprop_string(ms->fdt, mem_name, "device_type", "memory"); + riscv_socket_fdt_write_id(ms, mem_name, socket); g_free(mem_name); } @@ -303,7 +303,7 @@ static void create_fdt_socket_clint(RISCVVirtState *s, char *clint_name; uint32_t *clint_cells; unsigned long clint_addr; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); static const char * const clint_compat[2] = { "sifive,clint0", "riscv,clint0" }; @@ -319,15 +319,15 @@ static void create_fdt_socket_clint(RISCVVirtState *s, clint_addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket); clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr); - qemu_fdt_add_subnode(mc->fdt, clint_name); - qemu_fdt_setprop_string_array(mc->fdt, clint_name, "compatible", + qemu_fdt_add_subnode(ms->fdt, clint_name); + qemu_fdt_setprop_string_array(ms->fdt, clint_name, "compatible", (char **)&clint_compat, ARRAY_SIZE(clint_compat)); - qemu_fdt_setprop_cells(mc->fdt, clint_name, "reg", + qemu_fdt_setprop_cells(ms->fdt, clint_name, "reg", 0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size); - qemu_fdt_setprop(mc->fdt, clint_name, "interrupts-extended", + qemu_fdt_setprop(ms->fdt, clint_name, "interrupts-extended", clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); - riscv_socket_fdt_write_id(mc, clint_name, socket); + riscv_socket_fdt_write_id(ms, clint_name, socket); g_free(clint_name); g_free(clint_cells); @@ -344,7 +344,7 @@ static void create_fdt_socket_aclint(RISCVVirtState *s, uint32_t *aclint_mswi_cells; uint32_t *aclint_sswi_cells; uint32_t *aclint_mtimer_cells; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); aclint_mswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); aclint_mtimer_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); @@ -363,16 +363,16 @@ static void create_fdt_socket_aclint(RISCVVirtState *s, if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) { addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket); name = g_strdup_printf("/soc/mswi@%lx", addr); - qemu_fdt_add_subnode(mc->fdt, name); - qemu_fdt_setprop_string(mc->fdt, name, "compatible", + qemu_fdt_add_subnode(ms->fdt, name); + qemu_fdt_setprop_string(ms->fdt, name, "compatible", "riscv,aclint-mswi"); - qemu_fdt_setprop_cells(mc->fdt, name, "reg", + qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0x0, addr, 0x0, RISCV_ACLINT_SWI_SIZE); - qemu_fdt_setprop(mc->fdt, name, "interrupts-extended", + qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", aclint_mswi_cells, aclint_cells_size); - qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0); - qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0); - riscv_socket_fdt_write_id(mc, name, socket); + qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0); + qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 0); + riscv_socket_fdt_write_id(ms, name, socket); g_free(name); } @@ -386,33 +386,33 @@ static void create_fdt_socket_aclint(RISCVVirtState *s, size = memmap[VIRT_CLINT].size - RISCV_ACLINT_SWI_SIZE; } name = g_strdup_printf("/soc/mtimer@%lx", addr); - qemu_fdt_add_subnode(mc->fdt, name); - qemu_fdt_setprop_string(mc->fdt, name, "compatible", + qemu_fdt_add_subnode(ms->fdt, name); + qemu_fdt_setprop_string(ms->fdt, name, "compatible", "riscv,aclint-mtimer"); - qemu_fdt_setprop_cells(mc->fdt, name, "reg", + qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0x0, addr + RISCV_ACLINT_DEFAULT_MTIME, 0x0, size - RISCV_ACLINT_DEFAULT_MTIME, 0x0, addr + RISCV_ACLINT_DEFAULT_MTIMECMP, 0x0, RISCV_ACLINT_DEFAULT_MTIME); - qemu_fdt_setprop(mc->fdt, name, "interrupts-extended", + qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", aclint_mtimer_cells, aclint_cells_size); - riscv_socket_fdt_write_id(mc, name, socket); + riscv_socket_fdt_write_id(ms, name, socket); g_free(name); if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) { addr = memmap[VIRT_ACLINT_SSWI].base + (memmap[VIRT_ACLINT_SSWI].size * socket); name = g_strdup_printf("/soc/sswi@%lx", addr); - qemu_fdt_add_subnode(mc->fdt, name); - qemu_fdt_setprop_string(mc->fdt, name, "compatible", + qemu_fdt_add_subnode(ms->fdt, name); + qemu_fdt_setprop_string(ms->fdt, name, "compatible", "riscv,aclint-sswi"); - qemu_fdt_setprop_cells(mc->fdt, name, "reg", + qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0x0, addr, 0x0, memmap[VIRT_ACLINT_SSWI].size); - qemu_fdt_setprop(mc->fdt, name, "interrupts-extended", + qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", aclint_sswi_cells, aclint_cells_size); - qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0); - qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0); - riscv_socket_fdt_write_id(mc, name, socket); + qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0); + qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 0); + riscv_socket_fdt_write_id(ms, name, socket); g_free(name); } @@ -430,7 +430,7 @@ static void create_fdt_socket_plic(RISCVVirtState *s, char *plic_name; uint32_t *plic_cells; unsigned long plic_addr; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); static const char * const plic_compat[2] = { "sifive,plic-1.0.0", "riscv,plic0" }; @@ -456,27 +456,27 @@ static void create_fdt_socket_plic(RISCVVirtState *s, plic_phandles[socket] = (*phandle)++; plic_addr = memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * socket); plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr); - qemu_fdt_add_subnode(mc->fdt, plic_name); - qemu_fdt_setprop_cell(mc->fdt, plic_name, + qemu_fdt_add_subnode(ms->fdt, plic_name); + qemu_fdt_setprop_cell(ms->fdt, plic_name, "#interrupt-cells", FDT_PLIC_INT_CELLS); - qemu_fdt_setprop_cell(mc->fdt, plic_name, + qemu_fdt_setprop_cell(ms->fdt, plic_name, "#address-cells", FDT_PLIC_ADDR_CELLS); - qemu_fdt_setprop_string_array(mc->fdt, plic_name, "compatible", + qemu_fdt_setprop_string_array(ms->fdt, plic_name, "compatible", (char **)&plic_compat, ARRAY_SIZE(plic_compat)); - qemu_fdt_setprop(mc->fdt, plic_name, "interrupt-controller", NULL, 0); - qemu_fdt_setprop(mc->fdt, plic_name, "interrupts-extended", + qemu_fdt_setprop(ms->fdt, plic_name, "interrupt-controller", NULL, 0); + qemu_fdt_setprop(ms->fdt, plic_name, "interrupts-extended", plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); - qemu_fdt_setprop_cells(mc->fdt, plic_name, "reg", + qemu_fdt_setprop_cells(ms->fdt, plic_name, "reg", 0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size); - qemu_fdt_setprop_cell(mc->fdt, plic_name, "riscv,ndev", + qemu_fdt_setprop_cell(ms->fdt, plic_name, "riscv,ndev", VIRT_IRQCHIP_NUM_SOURCES - 1); - riscv_socket_fdt_write_id(mc, plic_name, socket); - qemu_fdt_setprop_cell(mc->fdt, plic_name, "phandle", + riscv_socket_fdt_write_id(ms, plic_name, socket); + qemu_fdt_setprop_cell(ms->fdt, plic_name, "phandle", plic_phandles[socket]); if (!socket) { - platform_bus_add_all_fdt_nodes(mc->fdt, plic_name, + platform_bus_add_all_fdt_nodes(ms->fdt, plic_name, memmap[VIRT_PLATFORM_BUS].base, memmap[VIRT_PLATFORM_BUS].size, VIRT_PLATFORM_BUS_IRQ); @@ -504,18 +504,18 @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, { int cpu, socket; char *imsic_name; - MachineState *mc = MACHINE(s); - int socket_count = riscv_socket_count(mc); + MachineState *ms = MACHINE(s); + int socket_count = riscv_socket_count(ms); uint32_t imsic_max_hart_per_socket, imsic_guest_bits; uint32_t *imsic_cells, *imsic_regs, imsic_addr, imsic_size; *msi_m_phandle = (*phandle)++; *msi_s_phandle = (*phandle)++; - imsic_cells = g_new0(uint32_t, mc->smp.cpus * 2); + imsic_cells = g_new0(uint32_t, ms->smp.cpus * 2); imsic_regs = g_new0(uint32_t, socket_count * 4); /* M-level IMSIC node */ - for (cpu = 0; cpu < mc->smp.cpus; cpu++) { + for (cpu = 0; cpu < ms->smp.cpus; cpu++) { imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); imsic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_EXT); } @@ -534,35 +534,35 @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, } imsic_name = g_strdup_printf("/soc/imsics@%lx", (unsigned long)memmap[VIRT_IMSIC_M].base); - qemu_fdt_add_subnode(mc->fdt, imsic_name); - qemu_fdt_setprop_string(mc->fdt, imsic_name, "compatible", + qemu_fdt_add_subnode(ms->fdt, imsic_name); + qemu_fdt_setprop_string(ms->fdt, imsic_name, "compatible", "riscv,imsics"); - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "#interrupt-cells", + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "#interrupt-cells", FDT_IMSIC_INT_CELLS); - qemu_fdt_setprop(mc->fdt, imsic_name, "interrupt-controller", + qemu_fdt_setprop(ms->fdt, imsic_name, "interrupt-controller", NULL, 0); - qemu_fdt_setprop(mc->fdt, imsic_name, "msi-controller", + qemu_fdt_setprop(ms->fdt, imsic_name, "msi-controller", NULL, 0); - qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended", - imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2); - qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs, + qemu_fdt_setprop(ms->fdt, imsic_name, "interrupts-extended", + imsic_cells, ms->smp.cpus * sizeof(uint32_t) * 2); + qemu_fdt_setprop(ms->fdt, imsic_name, "reg", imsic_regs, socket_count * sizeof(uint32_t) * 4); - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids", + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,num-ids", VIRT_IRQCHIP_NUM_MSIS); if (socket_count > 1) { - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits", + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,hart-index-bits", imsic_num_bits(imsic_max_hart_per_socket)); - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bits", + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-bits", imsic_num_bits(socket_count)); - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-shift", + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-shift", IMSIC_MMIO_GROUP_MIN_SHIFT); } - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "phandle", *msi_m_phandle); + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "phandle", *msi_m_phandle); g_free(imsic_name); /* S-level IMSIC node */ - for (cpu = 0; cpu < mc->smp.cpus; cpu++) { + for (cpu = 0; cpu < ms->smp.cpus; cpu++) { imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); imsic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT); } @@ -583,34 +583,34 @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, } imsic_name = g_strdup_printf("/soc/imsics@%lx", (unsigned long)memmap[VIRT_IMSIC_S].base); - qemu_fdt_add_subnode(mc->fdt, imsic_name); - qemu_fdt_setprop_string(mc->fdt, imsic_name, "compatible", + qemu_fdt_add_subnode(ms->fdt, imsic_name); + qemu_fdt_setprop_string(ms->fdt, imsic_name, "compatible", "riscv,imsics"); - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "#interrupt-cells", + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "#interrupt-cells", FDT_IMSIC_INT_CELLS); - qemu_fdt_setprop(mc->fdt, imsic_name, "interrupt-controller", + qemu_fdt_setprop(ms->fdt, imsic_name, "interrupt-controller", NULL, 0); - qemu_fdt_setprop(mc->fdt, imsic_name, "msi-controller", + qemu_fdt_setprop(ms->fdt, imsic_name, "msi-controller", NULL, 0); - qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended", - imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2); - qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs, + qemu_fdt_setprop(ms->fdt, imsic_name, "interrupts-extended", + imsic_cells, ms->smp.cpus * sizeof(uint32_t) * 2); + qemu_fdt_setprop(ms->fdt, imsic_name, "reg", imsic_regs, socket_count * sizeof(uint32_t) * 4); - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids", + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,num-ids", VIRT_IRQCHIP_NUM_MSIS); if (imsic_guest_bits) { - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,guest-index-bits", + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,guest-index-bits", imsic_guest_bits); } if (socket_count > 1) { - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits", + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,hart-index-bits", imsic_num_bits(imsic_max_hart_per_socket)); - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bits", + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-bits", imsic_num_bits(socket_count)); - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-shift", + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-shift", IMSIC_MMIO_GROUP_MIN_SHIFT); } - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "phandle", *msi_s_phandle); + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "phandle", *msi_s_phandle); g_free(imsic_name); g_free(imsic_regs); @@ -629,7 +629,7 @@ static void create_fdt_socket_aplic(RISCVVirtState *s, char *aplic_name; uint32_t *aplic_cells; unsigned long aplic_addr; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); uint32_t aplic_m_phandle, aplic_s_phandle; aplic_m_phandle = (*phandle)++; @@ -644,28 +644,28 @@ static void create_fdt_socket_aplic(RISCVVirtState *s, aplic_addr = memmap[VIRT_APLIC_M].base + (memmap[VIRT_APLIC_M].size * socket); aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr); - qemu_fdt_add_subnode(mc->fdt, aplic_name); - qemu_fdt_setprop_string(mc->fdt, aplic_name, "compatible", "riscv,aplic"); - qemu_fdt_setprop_cell(mc->fdt, aplic_name, + qemu_fdt_add_subnode(ms->fdt, aplic_name); + qemu_fdt_setprop_string(ms->fdt, aplic_name, "compatible", "riscv,aplic"); + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "#interrupt-cells", FDT_APLIC_INT_CELLS); - qemu_fdt_setprop(mc->fdt, aplic_name, "interrupt-controller", NULL, 0); + qemu_fdt_setprop(ms->fdt, aplic_name, "interrupt-controller", NULL, 0); if (s->aia_type == VIRT_AIA_TYPE_APLIC) { - qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended", + qemu_fdt_setprop(ms->fdt, aplic_name, "interrupts-extended", aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2); } else { - qemu_fdt_setprop_cell(mc->fdt, aplic_name, "msi-parent", + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent", msi_m_phandle); } - qemu_fdt_setprop_cells(mc->fdt, aplic_name, "reg", + qemu_fdt_setprop_cells(ms->fdt, aplic_name, "reg", 0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_M].size); - qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources", + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,num-sources", VIRT_IRQCHIP_NUM_SOURCES); - qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,children", + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,children", aplic_s_phandle); - qemu_fdt_setprop_cells(mc->fdt, aplic_name, "riscv,delegate", + qemu_fdt_setprop_cells(ms->fdt, aplic_name, "riscv,delegate", aplic_s_phandle, 0x1, VIRT_IRQCHIP_NUM_SOURCES); - riscv_socket_fdt_write_id(mc, aplic_name, socket); - qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_m_phandle); + riscv_socket_fdt_write_id(ms, aplic_name, socket); + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "phandle", aplic_m_phandle); g_free(aplic_name); /* S-level APLIC node */ @@ -676,27 +676,27 @@ static void create_fdt_socket_aplic(RISCVVirtState *s, aplic_addr = memmap[VIRT_APLIC_S].base + (memmap[VIRT_APLIC_S].size * socket); aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr); - qemu_fdt_add_subnode(mc->fdt, aplic_name); - qemu_fdt_setprop_string(mc->fdt, aplic_name, "compatible", "riscv,aplic"); - qemu_fdt_setprop_cell(mc->fdt, aplic_name, + qemu_fdt_add_subnode(ms->fdt, aplic_name); + qemu_fdt_setprop_string(ms->fdt, aplic_name, "compatible", "riscv,aplic"); + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "#interrupt-cells", FDT_APLIC_INT_CELLS); - qemu_fdt_setprop(mc->fdt, aplic_name, "interrupt-controller", NULL, 0); + qemu_fdt_setprop(ms->fdt, aplic_name, "interrupt-controller", NULL, 0); if (s->aia_type == VIRT_AIA_TYPE_APLIC) { - qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended", + qemu_fdt_setprop(ms->fdt, aplic_name, "interrupts-extended", aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2); } else { - qemu_fdt_setprop_cell(mc->fdt, aplic_name, "msi-parent", + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent", msi_s_phandle); } - qemu_fdt_setprop_cells(mc->fdt, aplic_name, "reg", + qemu_fdt_setprop_cells(ms->fdt, aplic_name, "reg", 0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_S].size); - qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources", + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,num-sources", VIRT_IRQCHIP_NUM_SOURCES); - riscv_socket_fdt_write_id(mc, aplic_name, socket); - qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_s_phandle); + riscv_socket_fdt_write_id(ms, aplic_name, socket); + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "phandle", aplic_s_phandle); if (!socket) { - platform_bus_add_all_fdt_nodes(mc->fdt, aplic_name, + platform_bus_add_all_fdt_nodes(ms->fdt, aplic_name, memmap[VIRT_PLATFORM_BUS].base, memmap[VIRT_PLATFORM_BUS].size, VIRT_PLATFORM_BUS_IRQ); @@ -711,13 +711,13 @@ static void create_fdt_socket_aplic(RISCVVirtState *s, static void create_fdt_pmu(RISCVVirtState *s) { char *pmu_name; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); RISCVCPU hart = s->soc[0].harts[0]; pmu_name = g_strdup_printf("/soc/pmu"); - qemu_fdt_add_subnode(mc->fdt, pmu_name); - qemu_fdt_setprop_string(mc->fdt, pmu_name, "compatible", "riscv,pmu"); - riscv_pmu_generate_fdt_node(mc->fdt, hart.cfg.pmu_num, pmu_name); + qemu_fdt_add_subnode(ms->fdt, pmu_name); + qemu_fdt_setprop_string(ms->fdt, pmu_name, "compatible", "riscv,pmu"); + riscv_pmu_generate_fdt_node(ms->fdt, hart.cfg.pmu_num, pmu_name); g_free(pmu_name); } @@ -731,26 +731,26 @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, { char *clust_name; int socket, phandle_pos; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); uint32_t msi_m_phandle = 0, msi_s_phandle = 0; uint32_t *intc_phandles, xplic_phandles[MAX_NODES]; - int socket_count = riscv_socket_count(mc); + int socket_count = riscv_socket_count(ms); - qemu_fdt_add_subnode(mc->fdt, "/cpus"); - qemu_fdt_setprop_cell(mc->fdt, "/cpus", "timebase-frequency", + qemu_fdt_add_subnode(ms->fdt, "/cpus"); + qemu_fdt_setprop_cell(ms->fdt, "/cpus", "timebase-frequency", RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ); - qemu_fdt_setprop_cell(mc->fdt, "/cpus", "#size-cells", 0x0); - qemu_fdt_setprop_cell(mc->fdt, "/cpus", "#address-cells", 0x1); - qemu_fdt_add_subnode(mc->fdt, "/cpus/cpu-map"); + qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); + qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1); + qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); - intc_phandles = g_new0(uint32_t, mc->smp.cpus); + intc_phandles = g_new0(uint32_t, ms->smp.cpus); - phandle_pos = mc->smp.cpus; + phandle_pos = ms->smp.cpus; for (socket = (socket_count - 1); socket >= 0; socket--) { phandle_pos -= s->soc[socket].num_harts; clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket); - qemu_fdt_add_subnode(mc->fdt, clust_name); + qemu_fdt_add_subnode(ms->fdt, clust_name); create_fdt_socket_cpus(s, socket, clust_name, phandle, &intc_phandles[phandle_pos]); @@ -776,7 +776,7 @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, *msi_pcie_phandle = msi_s_phandle; } - phandle_pos = mc->smp.cpus; + phandle_pos = ms->smp.cpus; for (socket = (socket_count - 1); socket >= 0; socket--) { phandle_pos -= s->soc[socket].num_harts; @@ -807,7 +807,7 @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, } } - riscv_socket_fdt_write_distance_matrix(mc); + riscv_socket_fdt_write_distance_matrix(ms); } static void create_fdt_virtio(RISCVVirtState *s, const MemMapEntry *memmap, @@ -815,23 +815,23 @@ static void create_fdt_virtio(RISCVVirtState *s, const MemMapEntry *memmap, { int i; char *name; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); for (i = 0; i < VIRTIO_COUNT; i++) { name = g_strdup_printf("/soc/virtio_mmio@%lx", (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size)); - qemu_fdt_add_subnode(mc->fdt, name); - qemu_fdt_setprop_string(mc->fdt, name, "compatible", "virtio,mmio"); - qemu_fdt_setprop_cells(mc->fdt, name, "reg", + qemu_fdt_add_subnode(ms->fdt, name); + qemu_fdt_setprop_string(ms->fdt, name, "compatible", "virtio,mmio"); + qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 0x0, memmap[VIRT_VIRTIO].size); - qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent", + qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", irq_virtio_phandle); if (s->aia_type == VIRT_AIA_TYPE_NONE) { - qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", + qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", VIRTIO_IRQ + i); } else { - qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", + qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", VIRTIO_IRQ + i, 0x4); } g_free(name); @@ -843,29 +843,29 @@ static void create_fdt_pcie(RISCVVirtState *s, const MemMapEntry *memmap, uint32_t msi_pcie_phandle) { char *name; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); name = g_strdup_printf("/soc/pci@%lx", (long) memmap[VIRT_PCIE_ECAM].base); - qemu_fdt_add_subnode(mc->fdt, name); - qemu_fdt_setprop_cell(mc->fdt, name, "#address-cells", + qemu_fdt_add_subnode(ms->fdt, name); + qemu_fdt_setprop_cell(ms->fdt, name, "#address-cells", FDT_PCI_ADDR_CELLS); - qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", + qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", FDT_PCI_INT_CELLS); - qemu_fdt_setprop_cell(mc->fdt, name, "#size-cells", 0x2); - qemu_fdt_setprop_string(mc->fdt, name, "compatible", + qemu_fdt_setprop_cell(ms->fdt, name, "#size-cells", 0x2); + qemu_fdt_setprop_string(ms->fdt, name, "compatible", "pci-host-ecam-generic"); - qemu_fdt_setprop_string(mc->fdt, name, "device_type", "pci"); - qemu_fdt_setprop_cell(mc->fdt, name, "linux,pci-domain", 0); - qemu_fdt_setprop_cells(mc->fdt, name, "bus-range", 0, + qemu_fdt_setprop_string(ms->fdt, name, "device_type", "pci"); + qemu_fdt_setprop_cell(ms->fdt, name, "linux,pci-domain", 0); + qemu_fdt_setprop_cells(ms->fdt, name, "bus-range", 0, memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1); - qemu_fdt_setprop(mc->fdt, name, "dma-coherent", NULL, 0); + qemu_fdt_setprop(ms->fdt, name, "dma-coherent", NULL, 0); if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { - qemu_fdt_setprop_cell(mc->fdt, name, "msi-parent", msi_pcie_phandle); + qemu_fdt_setprop_cell(ms->fdt, name, "msi-parent", msi_pcie_phandle); } - qemu_fdt_setprop_cells(mc->fdt, name, "reg", 0, + qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0, memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size); - qemu_fdt_setprop_sized_cells(mc->fdt, name, "ranges", + qemu_fdt_setprop_sized_cells(ms->fdt, name, "ranges", 1, FDT_PCI_RANGE_IOPORT, 2, 0, 2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size, 1, FDT_PCI_RANGE_MMIO, @@ -875,7 +875,7 @@ static void create_fdt_pcie(RISCVVirtState *s, const MemMapEntry *memmap, 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size); - create_pcie_irq_map(s, mc->fdt, name, irq_pcie_phandle); + create_pcie_irq_map(s, ms->fdt, name, irq_pcie_phandle); g_free(name); } @@ -884,39 +884,39 @@ static void create_fdt_reset(RISCVVirtState *s, const MemMapEntry *memmap, { char *name; uint32_t test_phandle; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); test_phandle = (*phandle)++; name = g_strdup_printf("/soc/test@%lx", (long)memmap[VIRT_TEST].base); - qemu_fdt_add_subnode(mc->fdt, name); + qemu_fdt_add_subnode(ms->fdt, name); { static const char * const compat[3] = { "sifive,test1", "sifive,test0", "syscon" }; - qemu_fdt_setprop_string_array(mc->fdt, name, "compatible", + qemu_fdt_setprop_string_array(ms->fdt, name, "compatible", (char **)&compat, ARRAY_SIZE(compat)); } - qemu_fdt_setprop_cells(mc->fdt, name, "reg", + qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0x0, memmap[VIRT_TEST].base, 0x0, memmap[VIRT_TEST].size); - qemu_fdt_setprop_cell(mc->fdt, name, "phandle", test_phandle); - test_phandle = qemu_fdt_get_phandle(mc->fdt, name); + qemu_fdt_setprop_cell(ms->fdt, name, "phandle", test_phandle); + test_phandle = qemu_fdt_get_phandle(ms->fdt, name); g_free(name); name = g_strdup_printf("/reboot"); - qemu_fdt_add_subnode(mc->fdt, name); - qemu_fdt_setprop_string(mc->fdt, name, "compatible", "syscon-reboot"); - qemu_fdt_setprop_cell(mc->fdt, name, "regmap", test_phandle); - qemu_fdt_setprop_cell(mc->fdt, name, "offset", 0x0); - qemu_fdt_setprop_cell(mc->fdt, name, "value", FINISHER_RESET); + qemu_fdt_add_subnode(ms->fdt, name); + qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-reboot"); + qemu_fdt_setprop_cell(ms->fdt, name, "regmap", test_phandle); + qemu_fdt_setprop_cell(ms->fdt, name, "offset", 0x0); + qemu_fdt_setprop_cell(ms->fdt, name, "value", FINISHER_RESET); g_free(name); name = g_strdup_printf("/poweroff"); - qemu_fdt_add_subnode(mc->fdt, name); - qemu_fdt_setprop_string(mc->fdt, name, "compatible", "syscon-poweroff"); - qemu_fdt_setprop_cell(mc->fdt, name, "regmap", test_phandle); - qemu_fdt_setprop_cell(mc->fdt, name, "offset", 0x0); - qemu_fdt_setprop_cell(mc->fdt, name, "value", FINISHER_PASS); + qemu_fdt_add_subnode(ms->fdt, name); + qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-poweroff"); + qemu_fdt_setprop_cell(ms->fdt, name, "regmap", test_phandle); + qemu_fdt_setprop_cell(ms->fdt, name, "offset", 0x0); + qemu_fdt_setprop_cell(ms->fdt, name, "value", FINISHER_PASS); g_free(name); } @@ -924,24 +924,24 @@ static void create_fdt_uart(RISCVVirtState *s, const MemMapEntry *memmap, uint32_t irq_mmio_phandle) { char *name; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); name = g_strdup_printf("/soc/serial@%lx", (long)memmap[VIRT_UART0].base); - qemu_fdt_add_subnode(mc->fdt, name); - qemu_fdt_setprop_string(mc->fdt, name, "compatible", "ns16550a"); - qemu_fdt_setprop_cells(mc->fdt, name, "reg", + qemu_fdt_add_subnode(ms->fdt, name); + qemu_fdt_setprop_string(ms->fdt, name, "compatible", "ns16550a"); + qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0x0, memmap[VIRT_UART0].base, 0x0, memmap[VIRT_UART0].size); - qemu_fdt_setprop_cell(mc->fdt, name, "clock-frequency", 3686400); - qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent", irq_mmio_phandle); + qemu_fdt_setprop_cell(ms->fdt, name, "clock-frequency", 3686400); + qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", irq_mmio_phandle); if (s->aia_type == VIRT_AIA_TYPE_NONE) { - qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", UART0_IRQ); + qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", UART0_IRQ); } else { - qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", UART0_IRQ, 0x4); + qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", UART0_IRQ, 0x4); } - qemu_fdt_add_subnode(mc->fdt, "/chosen"); - qemu_fdt_setprop_string(mc->fdt, "/chosen", "stdout-path", name); + qemu_fdt_add_subnode(ms->fdt, "/chosen"); + qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", name); g_free(name); } @@ -949,20 +949,20 @@ static void create_fdt_rtc(RISCVVirtState *s, const MemMapEntry *memmap, uint32_t irq_mmio_phandle) { char *name; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); name = g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base); - qemu_fdt_add_subnode(mc->fdt, name); - qemu_fdt_setprop_string(mc->fdt, name, "compatible", + qemu_fdt_add_subnode(ms->fdt, name); + qemu_fdt_setprop_string(ms->fdt, name, "compatible", "google,goldfish-rtc"); - qemu_fdt_setprop_cells(mc->fdt, name, "reg", + qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0x0, memmap[VIRT_RTC].base, 0x0, memmap[VIRT_RTC].size); - qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent", + qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", irq_mmio_phandle); if (s->aia_type == VIRT_AIA_TYPE_NONE) { - qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", RTC_IRQ); + qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", RTC_IRQ); } else { - qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", RTC_IRQ, 0x4); + qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", RTC_IRQ, 0x4); } g_free(name); } @@ -970,68 +970,68 @@ static void create_fdt_rtc(RISCVVirtState *s, const MemMapEntry *memmap, static void create_fdt_flash(RISCVVirtState *s, const MemMapEntry *memmap) { char *name; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; hwaddr flashbase = virt_memmap[VIRT_FLASH].base; name = g_strdup_printf("/flash@%" PRIx64, flashbase); - qemu_fdt_add_subnode(mc->fdt, name); - qemu_fdt_setprop_string(mc->fdt, name, "compatible", "cfi-flash"); - qemu_fdt_setprop_sized_cells(mc->fdt, name, "reg", + qemu_fdt_add_subnode(ms->fdt, name); + qemu_fdt_setprop_string(ms->fdt, name, "compatible", "cfi-flash"); + qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg", 2, flashbase, 2, flashsize, 2, flashbase + flashsize, 2, flashsize); - qemu_fdt_setprop_cell(mc->fdt, name, "bank-width", 4); + qemu_fdt_setprop_cell(ms->fdt, name, "bank-width", 4); g_free(name); } static void create_fdt_fw_cfg(RISCVVirtState *s, const MemMapEntry *memmap) { char *nodename; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); hwaddr base = memmap[VIRT_FW_CFG].base; hwaddr size = memmap[VIRT_FW_CFG].size; nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); - qemu_fdt_add_subnode(mc->fdt, nodename); - qemu_fdt_setprop_string(mc->fdt, nodename, + qemu_fdt_add_subnode(ms->fdt, nodename); + qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "qemu,fw-cfg-mmio"); - qemu_fdt_setprop_sized_cells(mc->fdt, nodename, "reg", + qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size); - qemu_fdt_setprop(mc->fdt, nodename, "dma-coherent", NULL, 0); + qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); g_free(nodename); } static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap) { - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1; uint32_t irq_pcie_phandle = 1, irq_virtio_phandle = 1; uint8_t rng_seed[32]; - if (mc->dtb) { - mc->fdt = load_device_tree(mc->dtb, &s->fdt_size); - if (!mc->fdt) { + if (ms->dtb) { + ms->fdt = load_device_tree(ms->dtb, &s->fdt_size); + if (!ms->fdt) { error_report("load_device_tree() failed"); exit(1); } } else { - mc->fdt = create_device_tree(&s->fdt_size); - if (!mc->fdt) { + ms->fdt = create_device_tree(&s->fdt_size); + if (!ms->fdt) { error_report("create_device_tree() failed"); exit(1); } } - qemu_fdt_setprop_string(mc->fdt, "/", "model", "riscv-virtio,qemu"); - qemu_fdt_setprop_string(mc->fdt, "/", "compatible", "riscv-virtio"); - qemu_fdt_setprop_cell(mc->fdt, "/", "#size-cells", 0x2); - qemu_fdt_setprop_cell(mc->fdt, "/", "#address-cells", 0x2); + qemu_fdt_setprop_string(ms->fdt, "/", "model", "riscv-virtio,qemu"); + qemu_fdt_setprop_string(ms->fdt, "/", "compatible", "riscv-virtio"); + qemu_fdt_setprop_cell(ms->fdt, "/", "#size-cells", 0x2); + qemu_fdt_setprop_cell(ms->fdt, "/", "#address-cells", 0x2); - qemu_fdt_add_subnode(mc->fdt, "/soc"); - qemu_fdt_setprop(mc->fdt, "/soc", "ranges", NULL, 0); - qemu_fdt_setprop_string(mc->fdt, "/soc", "compatible", "simple-bus"); - qemu_fdt_setprop_cell(mc->fdt, "/soc", "#size-cells", 0x2); - qemu_fdt_setprop_cell(mc->fdt, "/soc", "#address-cells", 0x2); + qemu_fdt_add_subnode(ms->fdt, "/soc"); + qemu_fdt_setprop(ms->fdt, "/soc", "ranges", NULL, 0); + qemu_fdt_setprop_string(ms->fdt, "/soc", "compatible", "simple-bus"); + qemu_fdt_setprop_cell(ms->fdt, "/soc", "#size-cells", 0x2); + qemu_fdt_setprop_cell(ms->fdt, "/soc", "#address-cells", 0x2); create_fdt_sockets(s, memmap, &phandle, &irq_mmio_phandle, &irq_pcie_phandle, &irq_virtio_phandle, @@ -1053,7 +1053,7 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap) /* Pass seed to RNG */ qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed)); - qemu_fdt_setprop(mc->fdt, "/chosen", "rng-seed", + qemu_fdt_setprop(ms->fdt, "/chosen", "rng-seed", rng_seed, sizeof(rng_seed)); } @@ -1106,14 +1106,14 @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, return dev; } -static FWCfgState *create_fw_cfg(const MachineState *mc) +static FWCfgState *create_fw_cfg(const MachineState *ms) { hwaddr base = virt_memmap[VIRT_FW_CFG].base; FWCfgState *fw_cfg; fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, &address_space_memory); - fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)mc->smp.cpus); + fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus); return fw_cfg; } -- 2.39.0 ^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 10/10] hw/riscv/spike.c: rename MachineState 'mc' pointers to' ms' 2023-01-11 17:09 [PATCH 00/10] riscv: create_fdt() related cleanups Daniel Henrique Barboza ` (8 preceding siblings ...) 2023-01-11 17:09 ` [PATCH 09/10] hw/riscv/virt.c: rename MachineState 'mc' pointers to 'ms' Daniel Henrique Barboza @ 2023-01-11 17:09 ` Daniel Henrique Barboza 2023-01-12 7:36 ` [PATCH 00/10] riscv: create_fdt() related cleanups Philippe Mathieu-Daudé 2023-01-16 4:04 ` Alistair Francis 11 siblings, 0 replies; 20+ messages in thread From: Daniel Henrique Barboza @ 2023-01-11 17:09 UTC (permalink / raw) To: qemu-devel Cc: qemu-riscv, alistair.francis, Daniel Henrique Barboza, Philippe Mathieu-Daudé Follow the QEMU convention of naming MachineState pointers as 'ms' by renaming the instances where we're calling it 'mc'. Suggested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> --- hw/riscv/spike.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 82093dd2cb..d753fb1f31 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -56,7 +56,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, uint64_t addr, size; unsigned long clint_addr; int cpu, socket; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); uint32_t *clint_cells; uint32_t cpu_phandle, intc_phandle, phandle = 1; char *name, *mem_name, *clint_name, *clust_name; @@ -65,7 +65,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, "sifive,clint0", "riscv,clint0" }; - fdt = mc->fdt = create_device_tree(&fdt_size); + fdt = ms->fdt = create_device_tree(&fdt_size); if (!fdt) { error_report("create_device_tree() failed"); exit(1); @@ -96,7 +96,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); qemu_fdt_add_subnode(fdt, "/cpus/cpu-map"); - for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) { + for (socket = (riscv_socket_count(ms) - 1); socket >= 0; socket--) { clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket); qemu_fdt_add_subnode(fdt, clust_name); @@ -121,7 +121,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, qemu_fdt_setprop_cell(fdt, cpu_name, "reg", s->soc[socket].hartid_base + cpu); qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu"); - riscv_socket_fdt_write_id(mc, cpu_name, socket); + riscv_socket_fdt_write_id(ms, cpu_name, socket); qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle); intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name); @@ -147,14 +147,14 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, g_free(cpu_name); } - addr = memmap[SPIKE_DRAM].base + riscv_socket_mem_offset(mc, socket); - size = riscv_socket_mem_size(mc, socket); + addr = memmap[SPIKE_DRAM].base + riscv_socket_mem_offset(ms, socket); + size = riscv_socket_mem_size(ms, socket); mem_name = g_strdup_printf("/memory@%lx", (long)addr); qemu_fdt_add_subnode(fdt, mem_name); qemu_fdt_setprop_cells(fdt, mem_name, "reg", addr >> 32, addr, size >> 32, size); qemu_fdt_setprop_string(fdt, mem_name, "device_type", "memory"); - riscv_socket_fdt_write_id(mc, mem_name, socket); + riscv_socket_fdt_write_id(ms, mem_name, socket); g_free(mem_name); clint_addr = memmap[SPIKE_CLINT].base + @@ -167,14 +167,14 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, 0x0, clint_addr, 0x0, memmap[SPIKE_CLINT].size); qemu_fdt_setprop(fdt, clint_name, "interrupts-extended", clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); - riscv_socket_fdt_write_id(mc, clint_name, socket); + riscv_socket_fdt_write_id(ms, clint_name, socket); g_free(clint_name); g_free(clint_cells); g_free(clust_name); } - riscv_socket_fdt_write_distance_matrix(mc); + riscv_socket_fdt_write_distance_matrix(ms); qemu_fdt_add_subnode(fdt, "/chosen"); qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", "/htif"); -- 2.39.0 ^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [PATCH 00/10] riscv: create_fdt() related cleanups 2023-01-11 17:09 [PATCH 00/10] riscv: create_fdt() related cleanups Daniel Henrique Barboza ` (9 preceding siblings ...) 2023-01-11 17:09 ` [PATCH 10/10] hw/riscv/spike.c: rename MachineState 'mc' pointers to' ms' Daniel Henrique Barboza @ 2023-01-12 7:36 ` Philippe Mathieu-Daudé 2023-01-16 4:04 ` Alistair Francis 11 siblings, 0 replies; 20+ messages in thread From: Philippe Mathieu-Daudé @ 2023-01-12 7:36 UTC (permalink / raw) To: Daniel Henrique Barboza, qemu-devel; +Cc: qemu-riscv, alistair.francis On 11/1/23 18:09, Daniel Henrique Barboza wrote: > Hi, > > This is a follow-up of: > > "[PATCH v5 00/11] riscv: OpenSBI boot test and cleanups" > > Patches were based on top of riscv-to-apply.next [1] + the series above. > > The recent FDT changes made in hw/riscv (all machines are now using the > FDT via MachineState::fdt) allowed for most of the cleanups made here. > > Patches 9 and 10 were based on a suggestion made by Phil a few weeks ago. > I decided to go for it. > > [1] https://github.com/alistair23/qemu/tree/riscv-to-apply.next > > Daniel Henrique Barboza (10): > hw/riscv/spike.c: simplify create_fdt() > hw/riscv/virt.c: simplify create_fdt() > hw/riscv/sifive_u.c: simplify create_fdt() > hw/riscv/virt.c: remove 'is_32_bit' param from > create_fdt_socket_cpus() > hw/riscv: use MachineState::fdt in riscv_socket_fdt_write_id() > hw/riscv: use ms->fdt in riscv_socket_fdt_write_distance_matrix() > hw/riscv: simplify riscv_load_fdt() > hw/riscv/virt.c: calculate socket count once in create_fdt_imsic() > hw/riscv/virt.c: rename MachineState 'mc' pointers to 'ms' > hw/riscv/spike.c: rename MachineState 'mc' pointers to' ms' Patch 7 likely needs rework (problem predating your series). Meanwhile for patches 1-6 & 8-10: Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Thanks for this cleanup! ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 00/10] riscv: create_fdt() related cleanups 2023-01-11 17:09 [PATCH 00/10] riscv: create_fdt() related cleanups Daniel Henrique Barboza ` (10 preceding siblings ...) 2023-01-12 7:36 ` [PATCH 00/10] riscv: create_fdt() related cleanups Philippe Mathieu-Daudé @ 2023-01-16 4:04 ` Alistair Francis 11 siblings, 0 replies; 20+ messages in thread From: Alistair Francis @ 2023-01-16 4:04 UTC (permalink / raw) To: Daniel Henrique Barboza; +Cc: qemu-devel, qemu-riscv, alistair.francis On Thu, Jan 12, 2023 at 3:12 AM Daniel Henrique Barboza <dbarboza@ventanamicro.com> wrote: > > Hi, > > This is a follow-up of: > > "[PATCH v5 00/11] riscv: OpenSBI boot test and cleanups" > > Patches were based on top of riscv-to-apply.next [1] + the series above. > > The recent FDT changes made in hw/riscv (all machines are now using the > FDT via MachineState::fdt) allowed for most of the cleanups made here. > > Patches 9 and 10 were based on a suggestion made by Phil a few weeks ago. > I decided to go for it. > > [1] https://github.com/alistair23/qemu/tree/riscv-to-apply.next > > Daniel Henrique Barboza (10): > hw/riscv/spike.c: simplify create_fdt() > hw/riscv/virt.c: simplify create_fdt() > hw/riscv/sifive_u.c: simplify create_fdt() > hw/riscv/virt.c: remove 'is_32_bit' param from > create_fdt_socket_cpus() > hw/riscv: use MachineState::fdt in riscv_socket_fdt_write_id() > hw/riscv: use ms->fdt in riscv_socket_fdt_write_distance_matrix() > hw/riscv: simplify riscv_load_fdt() > hw/riscv/virt.c: calculate socket count once in create_fdt_imsic() > hw/riscv/virt.c: rename MachineState 'mc' pointers to 'ms' > hw/riscv/spike.c: rename MachineState 'mc' pointers to' ms' Applied patches 1 to 6. Alistair > > hw/riscv/boot.c | 4 +- > hw/riscv/microchip_pfsoc.c | 4 +- > hw/riscv/numa.c | 14 +- > hw/riscv/sifive_u.c | 11 +- > hw/riscv/spike.c | 25 +- > hw/riscv/virt.c | 484 +++++++++++++++++++------------------ > include/hw/riscv/boot.h | 2 +- > include/hw/riscv/numa.h | 10 +- > 8 files changed, 277 insertions(+), 277 deletions(-) > > -- > 2.39.0 > > ^ permalink raw reply [flat|nested] 20+ messages in thread
end of thread, other threads:[~2023-01-16 4:05 UTC | newest] Thread overview: 20+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2023-01-11 17:09 [PATCH 00/10] riscv: create_fdt() related cleanups Daniel Henrique Barboza 2023-01-11 17:09 ` [PATCH 01/10] hw/riscv/spike.c: simplify create_fdt() Daniel Henrique Barboza 2023-01-16 3:53 ` Alistair Francis 2023-01-11 17:09 ` [PATCH 02/10] hw/riscv/virt.c: " Daniel Henrique Barboza 2023-01-16 3:54 ` Alistair Francis 2023-01-11 17:09 ` [PATCH 03/10] hw/riscv/sifive_u.c: " Daniel Henrique Barboza 2023-01-16 3:57 ` Alistair Francis 2023-01-11 17:09 ` [PATCH 04/10] hw/riscv/virt.c: remove 'is_32_bit' param from create_fdt_socket_cpus() Daniel Henrique Barboza 2023-01-16 3:58 ` Alistair Francis 2023-01-11 17:09 ` [PATCH 05/10] hw/riscv: use MachineState::fdt in riscv_socket_fdt_write_id() Daniel Henrique Barboza 2023-01-16 4:01 ` Alistair Francis 2023-01-11 17:09 ` [PATCH 06/10] hw/riscv: use ms->fdt in riscv_socket_fdt_write_distance_matrix() Daniel Henrique Barboza 2023-01-16 4:04 ` Alistair Francis 2023-01-11 17:09 ` [PATCH 07/10] hw/riscv: simplify riscv_load_fdt() Daniel Henrique Barboza 2023-01-12 7:33 ` Philippe Mathieu-Daudé 2023-01-11 17:09 ` [PATCH 08/10] hw/riscv/virt.c: calculate socket count once in create_fdt_imsic() Daniel Henrique Barboza 2023-01-11 17:09 ` [PATCH 09/10] hw/riscv/virt.c: rename MachineState 'mc' pointers to 'ms' Daniel Henrique Barboza 2023-01-11 17:09 ` [PATCH 10/10] hw/riscv/spike.c: rename MachineState 'mc' pointers to' ms' Daniel Henrique Barboza 2023-01-12 7:36 ` [PATCH 00/10] riscv: create_fdt() related cleanups Philippe Mathieu-Daudé 2023-01-16 4:04 ` Alistair Francis
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