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[176.184.32.47]) by smtp.gmail.com with ESMTPSA id o15-20020a198c0f000000b0050e7dcc05a5sm425817lfd.102.2024.01.09.10.22.05 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 09 Jan 2024 10:22:07 -0800 (PST) Message-ID: Date: Tue, 9 Jan 2024 19:22:04 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 09/14] hw/arm: Prefer arm_feature(EL3) over object_property_find(has_el3) Content-Language: en-US To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?UTF-8?Q?Alex_Benn=C3=A9e?= , Leif Lindholm , Radoslaw Biernacki , Kevin Wolf , Markus Armbruster , "Edgar E. Iglesias" , Igor Mitsyanko , Rob Herring , Alistair Francis , Peter Maydell , Marcin Juszkiewicz References: <20240109180930.90793-1-philmd@linaro.org> <20240109180930.90793-10-philmd@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20240109180930.90793-10-philmd@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::12e; envelope-from=philmd@linaro.org; helo=mail-lf1-x12e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 9/1/24 19:09, Philippe Mathieu-Daudé wrote: > The "has_el3" property is added to ARMCPU when the > ARM_FEATURE_EL3 feature is available. Rather than > checking whether the QOM property is present, directly > check the feature. > > Suggested-by: Markus Armbruster > Signed-off-by: Philippe Mathieu-Daudé > --- > hw/arm/exynos4210.c | 4 ++-- > hw/arm/integratorcp.c | 5 ++--- > hw/arm/realview.c | 2 +- > hw/arm/versatilepb.c | 5 ++--- > hw/arm/xilinx_zynq.c | 2 +- > hw/cpu/a15mpcore.c | 11 +++++++---- > hw/cpu/a9mpcore.c | 6 +++--- > 7 files changed, 18 insertions(+), 17 deletions(-) > diff --git a/hw/cpu/a15mpcore.c b/hw/cpu/a15mpcore.c > index bfd8aa5644..cebfe142cf 100644 > --- a/hw/cpu/a15mpcore.c > +++ b/hw/cpu/a15mpcore.c > @@ -53,7 +53,6 @@ static void a15mp_priv_realize(DeviceState *dev, Error **errp) > DeviceState *gicdev; > SysBusDevice *busdev; > int i; > - bool has_el3; > bool has_el2 = false; > Object *cpuobj; > > @@ -62,13 +61,17 @@ static void a15mp_priv_realize(DeviceState *dev, Error **errp) > qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq); > > if (!kvm_irqchip_in_kernel()) { > + CPUState *cpu; > + > /* Make the GIC's TZ support match the CPUs. We assume that > * either all the CPUs have TZ, or none do. > */ > - cpuobj = OBJECT(qemu_get_cpu(0)); > - has_el3 = object_property_find(cpuobj, "has_el3") && > + cpu = qemu_get_cpu(0); > + cpuobj = OBJECT(cpu); > + if (arm_feature(cpu_env(cpu), ARM_FEATURE_EL3)) { > object_property_get_bool(cpuobj, "has_el3", &error_abort); This requires the same change than a9mp_priv_realize(), so squashing: -- >8 -- if (arm_feature(cpu_env(cpu), ARM_FEATURE_EL3)) { - object_property_get_bool(cpuobj, "has_el3", &error_abort); - qdev_prop_set_bit(gicdev, "has-security-extensions", true); + qdev_prop_set_bit(gicdev, "has-security-extensions", + object_property_get_bool(cpuobj, "has_el3", + &error_abort)); } --- > - qdev_prop_set_bit(gicdev, "has-security-extensions", has_el3); > + qdev_prop_set_bit(gicdev, "has-security-extensions", true); > + } > /* Similarly for virtualization support */ > has_el2 = object_property_find(cpuobj, "has_el2") && > object_property_get_bool(cpuobj, "has_el2", &error_abort);