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[189.204.159.168]) by smtp.gmail.com with ESMTPSA id r205-20020acadad6000000b002ef824213c9sm7914319oig.55.2022.03.28.16.16.23 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 28 Mar 2022 16:16:24 -0700 (PDT) Message-ID: Date: Mon, 28 Mar 2022 17:16:22 -0600 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.7.0 Subject: Re: [RFC PATCH v7 20/29] hw/loongarch: Add irq hierarchy for the system Content-Language: en-US To: Xiaojuan Yang , qemu-devel@nongnu.org References: <20220328125749.2918087-1-yangxiaojuan@loongson.cn> <20220328125749.2918087-21-yangxiaojuan@loongson.cn> From: Richard Henderson In-Reply-To: <20220328125749.2918087-21-yangxiaojuan@loongson.cn> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Host-Lookup-Failed: Reverse DNS lookup failed for 2001:4860:4864:20::32 (failed) Received-SPF: pass client-ip=2001:4860:4864:20::32; envelope-from=richard.henderson@linaro.org; helo=mail-oa1-x32.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, PDS_HP_HELO_NORDNS=0.659, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.cave-ayland@ilande.co.uk, Song Gao Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 3/28/22 06:57, Xiaojuan Yang wrote: > +static struct DeviceState *ipi, *extioi; Static variables can't be right. These need to be somewhere else, or ... > @@ -107,12 +115,101 @@ static void loongarch_cpu_init(LoongArchCPU *la_cpu, int cpu_num) > NULL, "iocsr_misc", IOCSR_MEM_SIZE); > > memory_region_add_subregion(&env->system_iocsr, 0, &env->iocsr_mem); > + /* ipi memory region */ > + ipi_addr = SMP_IPI_MAILBOX + cpu_num * 0x100; > + memory_region_add_subregion(&env->system_iocsr, ipi_addr, > + sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), > + cpu_num)); > + /* extioi memory region */ > + memory_region_add_subregion(&env->system_iocsr, APIC_BASE, > + sysbus_mmio_get_region(SYS_BUS_DEVICE(extioi), > + cpu_num)); ... this code needs to be moved somewhere else. > +static void loongarch_irq_init(LoongArchMachineState *lams, > + DeviceState *ipi, DeviceState *extioi) > +{ > + MachineState *ms = MACHINE(lams); > + DeviceState *pch_pic, *pch_msi, *cpudev; > + > + SysBusDevice *d; > + int cpu, pin, i; > + > + for (cpu = 0; cpu < ms->smp.cpus; cpu++) { > + cpudev = DEVICE(qemu_get_cpu(cpu)); > + /* connect ipi irq to cpu irq */ > + qdev_connect_gpio_out(ipi, cpu, qdev_get_gpio_in(cpudev, IRQ_IPI)); > + } > + > + for (i = 0; i < EXTIOI_IRQS; i++) { > + sysbus_connect_irq(SYS_BUS_DEVICE(extioi), > + i, qdev_get_gpio_in(extioi, i)); > + } Um... connecting extioi to itself? I think that graphic that you used in the description of patch 15 belongs here as a comment. > diff --git a/include/hw/pci-host/ls7a.h b/include/hw/pci-host/ls7a.h > new file mode 100644 > index 0000000000..bf80e99ce1 > --- /dev/null > +++ b/include/hw/pci-host/ls7a.h > @@ -0,0 +1,30 @@ > +/* SPDX-License-Identifier: GPL-2.0-or-later */ > +/* > + * QEMU LoongArch CPU > + * > + * Copyright (c) 2021 Loongson Technology Corporation Limited > + */ > + > +#ifndef HW_LS7A_H > +#define HW_LS7A_H > + > +#include "hw/pci/pci.h" > +#include "hw/pci/pcie_host.h" > +#include "hw/pci-host/pam.h" > +#include "qemu/units.h" > +#include "qemu/range.h" > +#include "qom/object.h" > + > +#define LS7A_PCH_REG_BASE 0x10000000UL > +#define LS7A_IOAPIC_REG_BASE (LS7A_PCH_REG_BASE) > +#define LS7A_PCH_MSI_ADDR_LOW 0x2FF00000UL > + > +/* > + * According to the kernel pch irq start from 64 offset > + * 0 ~ 16 irqs used for non-pci device while 16 ~ 64 irqs > + * used for pci device. > + */ > +#define PCH_PIC_IRQ_OFFSET 64 > +#define LS7A_DEVICE_IRQS 16 > +#define LS7A_PCI_IRQS 48 > +#endif Why is this file in this patch? It seems like it should be in either patch 17 or 18? r~