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[174.21.143.238]) by smtp.gmail.com with ESMTPSA id m7sm3412610pgg.69.2020.06.18.16.19.35 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 18 Jun 2020 16:19:36 -0700 (PDT) Subject: Re: [PATCH 1/6] target/ppc: add byte-reverse br[dwh] instructions To: Lijun Pan , qemu-ppc@nongnu.org, qemu-devel@nongnu.org References: <20200613042029.22321-1-ljp@linux.ibm.com> <20200613042029.22321-2-ljp@linux.ibm.com> From: Richard Henderson Message-ID: Date: Thu, 18 Jun 2020 16:19:34 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.8.0 MIME-Version: 1.0 In-Reply-To: <20200613042029.22321-2-ljp@linux.ibm.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::542; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x542.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 6/12/20 9:20 PM, Lijun Pan wrote: > POWER ISA 3.1 introduces following byte-reverse instructions: > brd: Byte-Reverse Doubleword X-form > brw: Byte-Reverse Word X-form > brh: Byte-Reverse Halfword X-form > > Signed-off-by: Lijun Pan > --- > target/ppc/translate.c | 62 ++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 62 insertions(+) > > diff --git a/target/ppc/translate.c b/target/ppc/translate.c > index 4ce3d664b5..2d48fbc8db 100644 > --- a/target/ppc/translate.c > +++ b/target/ppc/translate.c > @@ -6971,7 +6971,69 @@ static void gen_dform3D(DisasContext *ctx) > return gen_invalid(ctx); > } > > +/* brd */ > +static void gen_brd(DisasContext *ctx) > +{ > + TCGv_i64 temp = tcg_temp_new_i64(); > + > + tcg_gen_bswap64_i64(temp, cpu_gpr[rS(ctx->opcode)]); > + tcg_gen_st_i64(temp, cpu_env, offsetof(CPUPPCState, gpr[rA(ctx->opcode)])); The store is wrong. You cannot modify storage behind a tcg global variable like that. This should just be tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); Is this code is within an ifdef for TARGET_PPC64? If not, then this will break the 32-bit qemu-system-ppc build. Are you sure you have built and tested all configurations? > +/* brw */ > +static void gen_brw(DisasContext *ctx) > +{ > + TCGv_i64 temp = tcg_temp_new_i64(); > + TCGv_i64 lsb = tcg_temp_new_i64(); > + TCGv_i64 msb = tcg_temp_new_i64(); > + > + tcg_gen_movi_i64(lsb, 0x00000000ffffffffull); > + tcg_gen_and_i64(temp, lsb, cpu_gpr[rS(ctx->opcode)]); > + tcg_gen_bswap32_i64(lsb, temp); > + > + tcg_gen_shri_i64(msb, cpu_gpr[rS(ctx->opcode)], 32); > + tcg_gen_bswap32_i64(temp, msb); > + tcg_gen_shli_i64(msb, temp, 32); > + > + tcg_gen_or_i64(temp, lsb, msb); > + > + tcg_gen_st_i64(temp, cpu_env, offsetof(CPUPPCState, gpr[rA(ctx->opcode)])); Again, the store is wrong. In addition, this can be computed as tcg_gen_bswap64_i64(dest, source); tcg_gen_rotli_i64(dest, dest, 32); > +static void gen_brh(DisasContext *ctx) > +{ > + TCGv_i64 temp = tcg_temp_new_i64(); > + TCGv_i64 t0 = tcg_temp_new_i64(); > + TCGv_i64 t1 = tcg_temp_new_i64(); > + TCGv_i64 t2 = tcg_temp_new_i64(); > + TCGv_i64 t3 = tcg_temp_new_i64(); > + > + tcg_gen_movi_i64(t0, 0x00ff00ff00ff00ffull); > + tcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8); > + tcg_gen_and_i64(t2, t1, t0); > + tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], t0); > + tcg_gen_shli_i64(t1, t1, 8); > + tcg_gen_or_i64(temp, t1, t2); > + tcg_gen_st_i64(temp, cpu_env, offsetof(CPUPPCState, gpr[rA(ctx->opcode)])); Again, the store is wrong. r~