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([2a01:e0a:280:24f0:576b:abc6:6396:ed4a]) by smtp.gmail.com with ESMTPSA id n12-20020a1c720c000000b003f90b58df65sm1783541wmc.29.2023.06.23.02.32.58 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 23 Jun 2023 02:32:58 -0700 (PDT) Message-ID: Date: Fri, 23 Jun 2023 11:32:58 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.12.0 Subject: Re: [PATCH] target/ppc: Better CTRL SPR implementation Content-Language: en-US To: Nicholas Piggin , qemu-ppc@nongnu.org Cc: qemu-devel@nongnu.org, Harsh Prateek Bora , Daniel Henrique Barboza References: <20230620131523.169340-1-npiggin@gmail.com> From: =?UTF-8?Q?C=c3=a9dric_Le_Goater?= In-Reply-To: <20230620131523.169340-1-npiggin@gmail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.129.124; envelope-from=clegoate@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.09, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 6/20/23 15:15, Nicholas Piggin wrote: > The CTRL register is able to write the bit in the RUN field, which gets > reflected into the TS field which is read-only and contains the state of > the RUN field for all threads in the core. > > TCG does not implement SMT, so the correct implementation just requires > mirroring the RUN bit into the first bit of the TS field. > > Signed-off-by: Nicholas Piggin Applied to ppc-next. Thanks, C. > --- > This is also unchanged from last posting except improved changelog. > The pseries TCG SMT patches depend on this one, but it is good to go > by itself too (this is what CTRL appears like to hardware KVM guest). > > Thanks, > Nick > > target/ppc/translate.c | 9 ++++++++- > 1 file changed, 8 insertions(+), 1 deletion(-) > > diff --git a/target/ppc/translate.c b/target/ppc/translate.c > index b591f2e496..1ade063616 100644 > --- a/target/ppc/translate.c > +++ b/target/ppc/translate.c > @@ -418,7 +418,14 @@ void spr_write_generic32(DisasContext *ctx, int sprn, int gprn) > > void spr_write_CTRL(DisasContext *ctx, int sprn, int gprn) > { > - spr_write_generic32(ctx, sprn, gprn); > + /* This does not implement >1 thread */ > + TCGv t0 = tcg_temp_new(); > + TCGv t1 = tcg_temp_new(); > + tcg_gen_extract_tl(t0, cpu_gpr[gprn], 0, 1); /* Extract RUN field */ > + tcg_gen_shli_tl(t1, t0, 8); /* Duplicate the bit in TS */ > + tcg_gen_or_tl(t1, t1, t0); > + gen_store_spr(sprn, t1); > + spr_store_dump_spr(sprn); > > /* > * SPR_CTRL writes must force a new translation block,