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From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: Thomas Huth <thuth@redhat.com>, qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, qemu-ppc@nongnu.org,
	"Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
	"Alistair Francis" <alistair@alistair23.me>,
	"Richard Henderson" <richard.henderson@linaro.org>,
	"Markus Armbruster" <armbru@redhat.com>,
	qemu-arm@nongnu.org, "Daniel P. Berrangé" <berrange@redhat.com>
Subject: Re: [PATCH v6 02/11] hw/intc/xilinx_intc: Make device endianness configurable
Date: Wed, 12 Feb 2025 12:44:23 +0100	[thread overview]
Message-ID: <e2c0e0fe-dafa-4ed6-be0d-63f9afb5a8b2@linaro.org> (raw)
In-Reply-To: <125a3dac-8ef9-4748-a3ce-f8fb97d8cb59@redhat.com>

On 12/2/25 12:42, Thomas Huth wrote:
> On 12/02/2025 12.24, Philippe Mathieu-Daudé wrote:
>> Replace the DEVICE_NATIVE_ENDIAN MemoryRegionOps by a pair
>> of DEVICE_LITTLE_ENDIAN / DEVICE_BIG_ENDIAN.
>> Add the "little-endian" property to select the device
>> endianness, defaulting to little endian.
>> Set the proper endianness for each machine using the device.
>>
>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>> ---
>>   hw/intc/xilinx_intc.c                    | 60 ++++++++++++++++++------
>>   hw/microblaze/petalogix_ml605_mmu.c      |  1 +
>>   hw/microblaze/petalogix_s3adsp1800_mmu.c |  3 ++
>>   hw/ppc/virtex_ml507.c                    |  1 +
>>   hw/riscv/microblaze-v-generic.c          |  1 +
>>   5 files changed, 52 insertions(+), 14 deletions(-)
>>
>> diff --git a/hw/intc/xilinx_intc.c b/hw/intc/xilinx_intc.c
>> index 6930f83907a..523402b688c 100644
>> --- a/hw/intc/xilinx_intc.c
>> +++ b/hw/intc/xilinx_intc.c
>> @@ -3,6 +3,9 @@
>>    *
>>    * Copyright (c) 2009 Edgar E. Iglesias.
>>    *
>> + * https://docs.amd.com/v/u/en-US/xps_intc
>> + * DS572: LogiCORE IP XPS Interrupt Controller (v2.01a)
>> + *
>>    * Permission is hereby granted, free of charge, to any person 
>> obtaining a copy
>>    * of this software and associated documentation files (the 
>> "Software"), to deal
>>    * in the Software without restriction, including without limitation 
>> the rights
>> @@ -23,10 +26,12 @@
>>    */
>>   #include "qemu/osdep.h"
>> +#include "qapi/error.h"
>>   #include "hw/sysbus.h"
>>   #include "qemu/module.h"
>>   #include "hw/irq.h"
>>   #include "hw/qdev-properties.h"
>> +#include "hw/qdev-properties-system.h"
>>   #include "qom/object.h"
>>   #define D(x)
>> @@ -49,6 +54,7 @@ struct XpsIntc
>>   {
>>       SysBusDevice parent_obj;
>> +    EndianMode model_endianness;
>>       MemoryRegion mmio;
>>       qemu_irq parent_irq;
>> @@ -140,18 +146,29 @@ static void pic_write(void *opaque, hwaddr addr,
>>       update_irq(p);
>>   }
>> -static const MemoryRegionOps pic_ops = {
>> -    .read = pic_read,
>> -    .write = pic_write,
>> -    .endianness = DEVICE_NATIVE_ENDIAN,
>> -    .impl = {
>> -        .min_access_size = 4,
>> -        .max_access_size = 4,
>> +static const MemoryRegionOps pic_ops[2] = {
>> +    [0 ... 1] = {
> 
> Hmm, ok, so here we have now an assumption that ENDIAN_MODE_BIG and 
> ENDIAN_MODE_LITTLE match 0 and 1, which would not work anymore when 
> using 0 as unspecified... a little bit ugly ... so maybe instead of 
> changing pic_ops into an array ....
> 
>> +        .read = pic_read,
>> +        .write = pic_write,
>> +        .endianness = DEVICE_BIG_ENDIAN,
>> +        .impl = {
>> +            .min_access_size = 4,
>> +            .max_access_size = 4,
>> +        },
>> +        .valid = {
>> +            /*
>> +             * All XPS INTC registers are accessed through the PLB 
>> interface.
>> +             * The base address for these registers is provided by the
>> +             * configuration parameter, C_BASEADDR. Each register is 
>> 32 bits
>> +             * although some bits may be unused and is accessed on a 
>> 4-byte
>> +             * boundary offset from the base address.
>> +             */
>> +            .min_access_size = 4,
>> +            .max_access_size = 4,
>> +        },
>>       },
>> -    .valid = {
>> -        .min_access_size = 4,
>> -        .max_access_size = 4
>> -    }
>> +    [ENDIAN_MODE_BIG].endianness = DEVICE_BIG_ENDIAN,
>> +    [ENDIAN_MODE_LITTLE].endianness = DEVICE_LITTLE_ENDIAN,
>>   };
>>   static void irq_handler(void *opaque, int irq, int level)
>> @@ -174,13 +191,27 @@ static void xilinx_intc_init(Object *obj)
>>       qdev_init_gpio_in(DEVICE(obj), irq_handler, 32);
>>       sysbus_init_irq(SYS_BUS_DEVICE(obj), &p->parent_irq);
>> -
>> -    memory_region_init_io(&p->mmio, obj, &pic_ops, p, "xlnx.xps-intc",
>> -                          R_MAX * 4);
>>       sysbus_init_mmio(SYS_BUS_DEVICE(obj), &p->mmio);
>>   }
>> +static void xilinx_intc_realize(DeviceState *dev, Error **errp)
>> +{
>> +    XpsIntc *p = XILINX_INTC(dev);
>> +
>> +    if (p->model_endianness == ENDIAN_MODE_UNSPECIFIED) {
>> +        error_setg(errp, TYPE_XILINX_INTC " property 'endianness'"
>> +                         " must be set to 'big' or 'little'");
>> +        return;
>> +    }
> 
> ... would it be possible to patch in the right value for pic_ops.endianness
> here instead?

Ah, clever than my reply on the previous patch. I'll give it a try, thanks!

> 
>   Thomas



  reply	other threads:[~2025-02-12 11:45 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-02-12 11:24 [PATCH v6 00/11] hw/microblaze: Allow running cross-endian vCPUs Philippe Mathieu-Daudé
2025-02-12 11:24 ` [PATCH v6 01/11] hw/qdev-properties-system: Introduce EndianMode QAPI enum Philippe Mathieu-Daudé
2025-02-12 11:37   ` Thomas Huth
2025-02-12 11:43     ` Philippe Mathieu-Daudé
2025-02-12 12:02       ` Philippe Mathieu-Daudé
2025-02-12 12:11         ` Daniel P. Berrangé
2025-02-12 12:56       ` BALATON Zoltan
2025-02-12 13:53         ` Philippe Mathieu-Daudé
2025-02-12 14:03           ` Philippe Mathieu-Daudé
2025-02-12 16:23             ` BALATON Zoltan
2025-02-12 18:17               ` Philippe Mathieu-Daudé
2025-02-12 22:34                 ` BALATON Zoltan
2025-02-13  7:07                   ` Thomas Huth
2025-02-13 13:59                     ` BALATON Zoltan
2025-02-13 14:24                       ` Philippe Mathieu-Daudé
2025-02-13 14:33                       ` Thomas Huth
2025-02-13 14:56                         ` BALATON Zoltan
2025-02-12 11:24 ` [PATCH v6 02/11] hw/intc/xilinx_intc: Make device endianness configurable Philippe Mathieu-Daudé
2025-02-12 11:42   ` Thomas Huth
2025-02-12 11:44     ` Philippe Mathieu-Daudé [this message]
2025-02-12 11:24 ` [PATCH v6 03/11] hw/net/xilinx_ethlite: " Philippe Mathieu-Daudé
2025-02-12 11:24 ` [PATCH v6 04/11] hw/timer/xilinx_timer: " Philippe Mathieu-Daudé
2025-02-12 11:24 ` [PATCH v6 05/11] hw/char/xilinx_uartlite: " Philippe Mathieu-Daudé
2025-02-12 11:24 ` [PATCH v6 06/11] hw/ssi/xilinx_spi: " Philippe Mathieu-Daudé
2025-02-12 11:24 ` [PATCH v6 07/11] tests/functional: Avoid using www.qemu-advent-calendar.org URL Philippe Mathieu-Daudé
2025-02-12 11:49   ` Thomas Huth
2025-02-12 11:53     ` Philippe Mathieu-Daudé
2025-02-12 11:24 ` [PATCH v6 08/11] tests/functional: Explicit endianness of microblaze assets Philippe Mathieu-Daudé
2025-02-12 11:24 ` [PATCH v6 09/11] tests/functional: Allow microblaze tests to take a machine name argument Philippe Mathieu-Daudé
2025-02-12 11:24 ` [PATCH v6 10/11] tests/functional: Remove sleep() kludges from microblaze tests Philippe Mathieu-Daudé
2025-02-12 11:24 ` [PATCH v6 11/11] tests/functional: Have microblaze tests inherit common parent class Philippe Mathieu-Daudé
2025-02-12 11:46   ` Thomas Huth
2025-02-12 11:55     ` Philippe Mathieu-Daudé

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