From: Paolo Bonzini <pbonzini@redhat.com>
To: Alistair Francis <alistair23@gmail.com>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Bin Meng <bmeng.cn@gmail.com>,
Alistair Francis <alistair.francis@wdc.com>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>
Subject: Re: [PATCH v2 2/3] hw/timer: Initial commit of Ibex Timer
Date: Fri, 11 Jun 2021 13:52:13 +0200 [thread overview]
Message-ID: <e2d39538-ee41-97e5-f547-793229a998b0@redhat.com> (raw)
In-Reply-To: <CAKmqyKNs5GwcGwRUZ8v17MJd40_STjOgqu-2vRU7ee21x79cKw@mail.gmail.com>
On 11/06/21 01:01, Alistair Francis wrote:
> On Wed, Jun 9, 2021 at 5:57 PM Paolo Bonzini <pbonzini@redhat.com> wrote:
>>
>> On 09/06/21 01:48, Alistair Francis wrote:
>>> Add support for the Ibex timer. This is used with the RISC-V
>>> mtime/mtimecmp similar to the SiFive CLINT.
>>>
>>> We currently don't support changing the prescale or the timervalue.
>>>
>>> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
>>
>> Any chance this could have a qtest? It would also be nice if the CPU
>
> Yep, do you have a good example of what the qtest should look like?
Without having access to the IRQ line it's a bit hard to write it, but
the qtests for various real-time clocks are probably the closest.
>> had qemu_irqs for MEIP/MTIP/SEIP (possibly MSIP too but that one is
>> bidirectional), so that instead of riscv_cpu_update_mip you can just
>> connect to a GPIO pin of the CPU and do qemu_set_irq. It could also be
>> used by the qtests via irq_intercept_in.
>
> Yeah the riscv_cpu_update_mip() is not ideal. As it is what we
> currently also use for the CLINT I don't want to fix it up here. In
> the future I'll work on changing riscv_cpu_update_mip in all the
> RISC-V timers to use GPIO lines instead.
If you add GPIO output pins to the CPU, the devices can be converted
away from riscv_cpu_update_mip one by one.
Paolo
next prev parent reply other threads:[~2021-06-11 11:53 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-08 23:48 [PATCH v2 0/3] hw/riscv: OpenTitan: Add support for the RISC-V timer Alistair Francis
2021-06-08 23:48 ` [PATCH v2 1/3] hw/char/ibex_uart: Make the register layout private Alistair Francis
2021-06-08 23:48 ` [PATCH v2 2/3] hw/timer: Initial commit of Ibex Timer Alistair Francis
2021-06-09 1:44 ` Bin Meng
2021-06-10 23:00 ` Alistair Francis
2021-06-09 7:57 ` Paolo Bonzini
2021-06-10 23:01 ` Alistair Francis
2021-06-11 11:52 ` Paolo Bonzini [this message]
2021-06-18 7:02 ` Alistair Francis
2021-06-08 23:49 ` [PATCH v2 3/3] hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer Alistair Francis
2021-06-09 1:44 ` Bin Meng
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