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([2001:b07:6468:f312:c8dd:75d4:99ab:290a]) by smtp.gmail.com with ESMTPSA id x10sm6805931wrt.26.2021.06.11.04.52.14 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 11 Jun 2021 04:52:14 -0700 (PDT) Subject: Re: [PATCH v2 2/3] hw/timer: Initial commit of Ibex Timer To: Alistair Francis References: From: Paolo Bonzini Message-ID: Date: Fri, 11 Jun 2021 13:52:13 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.10.1 MIME-Version: 1.0 In-Reply-To: Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=pbonzini@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=216.205.24.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.199, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "open list:RISC-V" , Palmer Dabbelt , Bin Meng , Alistair Francis , "qemu-devel@nongnu.org Developers" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 11/06/21 01:01, Alistair Francis wrote: > On Wed, Jun 9, 2021 at 5:57 PM Paolo Bonzini wrote: >> >> On 09/06/21 01:48, Alistair Francis wrote: >>> Add support for the Ibex timer. This is used with the RISC-V >>> mtime/mtimecmp similar to the SiFive CLINT. >>> >>> We currently don't support changing the prescale or the timervalue. >>> >>> Signed-off-by: Alistair Francis >> >> Any chance this could have a qtest? It would also be nice if the CPU > > Yep, do you have a good example of what the qtest should look like? Without having access to the IRQ line it's a bit hard to write it, but the qtests for various real-time clocks are probably the closest. >> had qemu_irqs for MEIP/MTIP/SEIP (possibly MSIP too but that one is >> bidirectional), so that instead of riscv_cpu_update_mip you can just >> connect to a GPIO pin of the CPU and do qemu_set_irq. It could also be >> used by the qtests via irq_intercept_in. > > Yeah the riscv_cpu_update_mip() is not ideal. As it is what we > currently also use for the CLINT I don't want to fix it up here. In > the future I'll work on changing riscv_cpu_update_mip in all the > RISC-V timers to use GPIO lines instead. If you add GPIO output pins to the CPU, the devices can be converted away from riscv_cpu_update_mip one by one. Paolo