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From: "Philippe Mathieu-Daudé" <philmd@redhat.com>
To: Yoshinori Sato <ysato@users.sourceforge.jp>, qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org,
	Richard Henderson <richard.henderson@linaro.org>
Subject: Re: [Qemu-devel] [PATCH v17 19/24] target/rx: Replace operand with prt_ldmi in disassembler
Date: Fri, 7 Jun 2019 15:42:54 +0200	[thread overview]
Message-ID: <e30e5562-6de8-80cb-7b88-8f30b89bb7a7@redhat.com> (raw)
In-Reply-To: <20190607091116.49044-20-ysato@users.sourceforge.jp>

On 6/7/19 11:11 AM, Yoshinori Sato wrote:
> From: Richard Henderson <richard.henderson@linaro.org>
> 
> This has consistency with prt_ri().  It loads all data before
> beginning output.  It uses exactly one call to prt() to emit
> the full instruction.
> 
> Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Again:
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>

> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
> ---
>  target/rx/disas.c | 77 +++++++++++++++++++------------------------------------
>  1 file changed, 27 insertions(+), 50 deletions(-)
> 
> diff --git a/target/rx/disas.c b/target/rx/disas.c
> index 64342537ee..515b365528 100644
> --- a/target/rx/disas.c
> +++ b/target/rx/disas.c
> @@ -135,18 +135,18 @@ static void rx_index_addr(DisasContext *ctx, char out[8], int ld, int mi)
>      sprintf(out, "%u", dsp << (mi < 3 ? mi : 4 - mi));
>  }
>  
> -static void operand(DisasContext *ctx, int ld, int mi, int rs, int rd)
> +static void prt_ldmi(DisasContext *ctx, const char *insn,
> +                     int ld, int mi, int rs, int rd)
>  {
>      static const char sizes[][4] = {".b", ".w", ".l", ".uw", ".ub"};
>      char dsp[8];
>  
>      if (ld < 3) {
>          rx_index_addr(ctx, dsp, ld, mi);
> -        prt("%s[r%d]%s", dsp, rs, sizes[mi]);
> +        prt("%s\t%s[r%d]%s, r%d", insn, dsp, rs, sizes[mi], rd);
>      } else {
> -        prt("r%d", rs);
> +        prt("%s\tr%d, r%d", insn, rs, rd);
>      }
> -    prt(", r%d", rd);
>  }
>  
>  static void prt_ir(DisasContext *ctx, const char *insn, int imm, int rd)
> @@ -416,8 +416,7 @@ static bool trans_AND_ir(DisasContext *ctx, arg_AND_ir *a)
>  /* and rs,rd */
>  static bool trans_AND_mr(DisasContext *ctx, arg_AND_mr *a)
>  {
> -    prt("and\t");
> -    operand(ctx, a->ld, a->mi, a->rs, a->rd);
> +    prt_ldmi(ctx, "and", a->ld, a->mi, a->rs, a->rd);
>      return true;
>  }
>  
> @@ -440,8 +439,7 @@ static bool trans_OR_ir(DisasContext *ctx, arg_OR_ir *a)
>  /* or rs,rd */
>  static bool trans_OR_mr(DisasContext *ctx, arg_OR_mr *a)
>  {
> -    prt("or\t");
> -    operand(ctx, a->ld, a->mi, a->rs, a->rd);
> +    prt_ldmi(ctx, "or", a->ld, a->mi, a->rs, a->rd);
>      return true;
>  }
>  
> @@ -463,8 +461,7 @@ static bool trans_XOR_ir(DisasContext *ctx, arg_XOR_ir *a)
>  /* xor rs,rd */
>  static bool trans_XOR_mr(DisasContext *ctx, arg_XOR_mr *a)
>  {
> -    prt("xor\t");
> -    operand(ctx, a->ld, a->mi, a->rs, a->rd);
> +    prt_ldmi(ctx, "xor", a->ld, a->mi, a->rs, a->rd);
>      return true;
>  }
>  
> @@ -479,8 +476,7 @@ static bool trans_TST_ir(DisasContext *ctx, arg_TST_ir *a)
>  /* tst rs, rd */
>  static bool trans_TST_mr(DisasContext *ctx, arg_TST_mr *a)
>  {
> -    prt("tst\t");
> -    operand(ctx, a->ld, a->mi, a->rs, a->rd);
> +    prt_ldmi(ctx, "tst", a->ld, a->mi, a->rs, a->rd);
>      return true;
>  }
>  
> @@ -548,8 +544,7 @@ static bool trans_ADD_irr(DisasContext *ctx, arg_ADD_irr *a)
>  /* add dsp[rs], rd */
>  static bool trans_ADD_mr(DisasContext *ctx, arg_ADD_mr *a)
>  {
> -    prt("add\t");
> -    operand(ctx, a->ld, a->mi, a->rs, a->rd);
> +    prt_ldmi(ctx, "add", a->ld, a->mi, a->rs, a->rd);
>      return true;
>  }
>  
> @@ -573,8 +568,7 @@ static bool trans_CMP_ir(DisasContext *ctx, arg_CMP_ir *a)
>  /* cmp dsp[rs], rs2 */
>  static bool trans_CMP_mr(DisasContext *ctx, arg_CMP_mr *a)
>  {
> -    prt("cmp\t");
> -    operand(ctx, a->ld, a->mi, a->rs, a->rd);
> +    prt_ldmi(ctx, "cmp", a->ld, a->mi, a->rs, a->rd);
>      return true;
>  }
>  
> @@ -589,8 +583,7 @@ static bool trans_SUB_ir(DisasContext *ctx, arg_SUB_ir *a)
>  /* sub dsp[rs], rd */
>  static bool trans_SUB_mr(DisasContext *ctx, arg_SUB_mr *a)
>  {
> -    prt("sub\t");
> -    operand(ctx, a->ld, a->mi, a->rs, a->rd);
> +    prt_ldmi(ctx, "sub", a->ld, a->mi, a->rs, a->rd);
>      return true;
>  }
>  
> @@ -611,8 +604,7 @@ static bool trans_SBB_rr(DisasContext *ctx, arg_SBB_rr *a)
>  /* sbb dsp[rs], rd */
>  static bool trans_SBB_mr(DisasContext *ctx, arg_SBB_mr *a)
>  {
> -    prt("sbb\t");
> -    operand(ctx, a->ld, RX_IM_LONG, a->rs, a->rd);
> +    prt_ldmi(ctx, "sbb", a->ld, RX_IM_LONG, a->rs, a->rd);
>      return true;
>  }
>  
> @@ -640,8 +632,7 @@ static bool trans_MAX_ir(DisasContext *ctx, arg_MAX_ir *a)
>  /* max dsp[rs], rd */
>  static bool trans_MAX_mr(DisasContext *ctx, arg_MAX_mr *a)
>  {
> -    prt("max\t");
> -    operand(ctx, a->ld, a->mi, a->rs, a->rd);
> +    prt_ldmi(ctx, "max", a->ld, a->mi, a->rs, a->rd);
>      return true;
>  }
>  
> @@ -656,8 +647,7 @@ static bool trans_MIN_ir(DisasContext *ctx, arg_MIN_ir *a)
>  /* min dsp[rs], rd */
>  static bool trans_MIN_mr(DisasContext *ctx, arg_MIN_mr *a)
>  {
> -    prt("max\t");
> -    operand(ctx, a->ld, a->mi, a->rs, a->rd);
> +    prt_ldmi(ctx, "min", a->ld, a->mi, a->rs, a->rd);
>      return true;
>  }
>  
> @@ -673,8 +663,7 @@ static bool trans_MUL_ir(DisasContext *ctx, arg_MUL_ir *a)
>  /* mul dsp[rs], rd */
>  static bool trans_MUL_mr(DisasContext *ctx, arg_MUL_mr *a)
>  {
> -    prt("mul\t");
> -    operand(ctx, a->ld, a->mi, a->rs, a->rd);
> +    prt_ldmi(ctx, "mul", a->ld, a->mi, a->rs, a->rd);
>      return true;
>  }
>  
> @@ -696,8 +685,7 @@ static bool trans_EMUL_ir(DisasContext *ctx, arg_EMUL_ir *a)
>  /* emul dsp[rs], rd */
>  static bool trans_EMUL_mr(DisasContext *ctx, arg_EMUL_mr *a)
>  {
> -    prt("emul\t");
> -    operand(ctx, a->ld, a->mi, a->rs, a->rd);
> +    prt_ldmi(ctx, "emul", a->ld, a->mi, a->rs, a->rd);
>      return true;
>  }
>  
> @@ -712,8 +700,7 @@ static bool trans_EMULU_ir(DisasContext *ctx, arg_EMULU_ir *a)
>  /* emulu dsp[rs], rd */
>  static bool trans_EMULU_mr(DisasContext *ctx, arg_EMULU_mr *a)
>  {
> -    prt("emulu\t");
> -    operand(ctx, a->ld, a->mi, a->rs, a->rd);
> +    prt_ldmi(ctx, "emulu", a->ld, a->mi, a->rs, a->rd);
>      return true;
>  }
>  
> @@ -728,8 +715,7 @@ static bool trans_DIV_ir(DisasContext *ctx, arg_DIV_ir *a)
>  /* div dsp[rs], rd */
>  static bool trans_DIV_mr(DisasContext *ctx, arg_DIV_mr *a)
>  {
> -    prt("div\t");
> -    operand(ctx, a->ld, a->mi, a->rs, a->rd);
> +    prt_ldmi(ctx, "div", a->ld, a->mi, a->rs, a->rd);
>      return true;
>  }
>  
> @@ -744,8 +730,7 @@ static bool trans_DIVU_ir(DisasContext *ctx, arg_DIVU_ir *a)
>  /* divu dsp[rs], rd */
>  static bool trans_DIVU_mr(DisasContext *ctx, arg_DIVU_mr *a)
>  {
> -    prt("divu\t");
> -    operand(ctx, a->ld, a->mi, a->rs, a->rd);
> +    prt_ldmi(ctx, "divu", a->ld, a->mi, a->rs, a->rd);
>      return true;
>  }
>  
> @@ -1089,8 +1074,7 @@ static bool trans_FADD_ir(DisasContext *ctx, arg_FADD_ir *a)
>  /* fadd rs, rd */
>  static bool trans_FADD_mr(DisasContext *ctx, arg_FADD_mr *a)
>  {
> -    prt("fadd\t");
> -    operand(ctx, a->ld, RX_IM_LONG, a->rs, a->rd);
> +    prt_ldmi(ctx, "fadd", a->ld, RX_IM_LONG, a->rs, a->rd);
>      return true;
>  }
>  
> @@ -1105,8 +1089,7 @@ static bool trans_FCMP_ir(DisasContext *ctx, arg_FCMP_ir *a)
>  /* fcmp rs, rd */
>  static bool trans_FCMP_mr(DisasContext *ctx, arg_FCMP_mr *a)
>  {
> -    prt("fcmp\t");
> -    operand(ctx, a->ld, RX_IM_LONG, a->rs, a->rd);
> +    prt_ldmi(ctx, "fcmp", a->ld, RX_IM_LONG, a->rs, a->rd);
>      return true;
>  }
>  
> @@ -1121,8 +1104,7 @@ static bool trans_FSUB_ir(DisasContext *ctx, arg_FSUB_ir *a)
>  /* fsub rs, rd */
>  static bool trans_FSUB_mr(DisasContext *ctx, arg_FSUB_mr *a)
>  {
> -    prt("fsub\t");
> -    operand(ctx, a->ld, RX_IM_LONG, a->rs, a->rd);
> +    prt_ldmi(ctx, "fsub", a->ld, RX_IM_LONG, a->rs, a->rd);
>      return true;
>  }
>  
> @@ -1130,8 +1112,7 @@ static bool trans_FSUB_mr(DisasContext *ctx, arg_FSUB_mr *a)
>  /* ftoi rs, rd */
>  static bool trans_FTOI(DisasContext *ctx, arg_FTOI *a)
>  {
> -    prt("ftoi\t");
> -    operand(ctx, a->ld, RX_IM_LONG, a->rs, a->rd);
> +    prt_ldmi(ctx, "ftoi", a->ld, RX_IM_LONG, a->rs, a->rd);
>      return true;
>  }
>  
> @@ -1146,8 +1127,7 @@ static bool trans_FMUL_ir(DisasContext *ctx, arg_FMUL_ir *a)
>  /* fmul rs, rd */
>  static bool trans_FMUL_mr(DisasContext *ctx, arg_FMUL_mr *a)
>  {
> -    prt("fmul\t");
> -    operand(ctx, a->ld, RX_IM_LONG, a->rs, a->rd);
> +    prt_ldmi(ctx, "fmul", a->ld, RX_IM_LONG, a->rs, a->rd);
>      return true;
>  }
>  
> @@ -1162,8 +1142,7 @@ static bool trans_FDIV_ir(DisasContext *ctx, arg_FDIV_ir *a)
>  /* fdiv rs, rd */
>  static bool trans_FDIV_mr(DisasContext *ctx, arg_FDIV_mr *a)
>  {
> -    prt("fdiv\t");
> -    operand(ctx, a->ld, RX_IM_LONG, a->rs, a->rd);
> +    prt_ldmi(ctx, "fdiv", a->ld, RX_IM_LONG, a->rs, a->rd);
>      return true;
>  }
>  
> @@ -1171,8 +1150,7 @@ static bool trans_FDIV_mr(DisasContext *ctx, arg_FDIV_mr *a)
>  /* round rs, rd */
>  static bool trans_ROUND(DisasContext *ctx, arg_ROUND *a)
>  {
> -    prt("round\t");
> -    operand(ctx, a->ld, RX_IM_LONG, a->rs, a->rd);
> +    prt_ldmi(ctx, "round", a->ld, RX_IM_LONG, a->rs, a->rd);
>      return true;
>  }
>  
> @@ -1180,8 +1158,7 @@ static bool trans_ROUND(DisasContext *ctx, arg_ROUND *a)
>  /* itof dsp[rs], rd */
>  static bool trans_ITOF(DisasContext *ctx, arg_ITOF *a)
>  {
> -    prt("itof\t");
> -    operand(ctx, a->ld, RX_IM_LONG, a->rs, a->rd);
> +    prt_ldmi(ctx, "itof", a->ld, RX_IM_LONG, a->rs, a->rd);
>      return true;
>  }
>  
> 


  reply	other threads:[~2019-06-07 13:52 UTC|newest]

Thread overview: 44+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-06-07  9:10 [Qemu-devel] [PATCH v17 00/24] Add RX archtecture support Yoshinori Sato
2019-06-07  9:10 ` [Qemu-devel] [PATCH v17 01/24] target/rx: TCG translation Yoshinori Sato
2019-06-07  9:10 ` [Qemu-devel] [PATCH v17 02/24] target/rx: TCG helper Yoshinori Sato
2019-06-07  9:10 ` [Qemu-devel] [PATCH v17 03/24] target/rx: CPU definition Yoshinori Sato
2019-06-07  9:10 ` [Qemu-devel] [PATCH v17 04/24] target/rx: RX disassembler Yoshinori Sato
2019-06-07  9:10 ` [Qemu-devel] [PATCH v17 05/24] hw/intc: RX62N interrupt controller (ICUa) Yoshinori Sato
2019-06-07  9:10 ` [Qemu-devel] [PATCH v17 06/24] hw/timer: RX62N internal timer modules Yoshinori Sato
2019-06-07  9:10 ` [Qemu-devel] [PATCH v17 07/24] hw/char: RX62N serial communication interface (SCI) Yoshinori Sato
2019-06-07  9:11 ` [Qemu-devel] [PATCH v17 08/24] hw/rx: RX Target hardware definition Yoshinori Sato
2019-06-07  9:11 ` [Qemu-devel] [PATCH v17 09/24] qemu/bitops.h: Add extract8 and extract16 Yoshinori Sato
2019-06-07  9:11 ` [Qemu-devel] [PATCH v17 10/24] hw/registerfields.h: Add 8bit and 16bit register macros Yoshinori Sato
2019-06-07  9:11 ` [Qemu-devel] [PATCH v17 11/24] target/rx: Convert to CPUClass::tlb_fill Yoshinori Sato
2019-06-07  9:11 ` [Qemu-devel] [PATCH v17 12/24] target/rx: Add RX to SysEmuTarget Yoshinori Sato
2019-06-07 13:39   ` Philippe Mathieu-Daudé
2019-06-07  9:11 ` [Qemu-devel] [PATCH v17 13/24] target/rx: Fix cpu types and names Yoshinori Sato
2019-06-07 14:06   ` Philippe Mathieu-Daudé
2019-06-07 14:19   ` Igor Mammedov
2019-06-10  5:51     ` Yoshinori Sato
2019-06-07  9:11 ` [Qemu-devel] [PATCH v17 14/24] tests: Add rx to machine-none-test.c Yoshinori Sato
2019-06-07 14:05   ` Philippe Mathieu-Daudé
2019-06-07  9:11 ` [Qemu-devel] [PATCH v17 15/24] hw/rx: Honor -accel qtest Yoshinori Sato
2019-06-07 13:40   ` Philippe Mathieu-Daudé
2019-06-07  9:11 ` [Qemu-devel] [PATCH v17 16/24] Add rx-softmmu Yoshinori Sato
2019-06-07 13:44   ` Philippe Mathieu-Daudé
2019-06-07 14:03     ` Richard Henderson
2019-06-07 14:08       ` Philippe Mathieu-Daudé
2019-06-07  9:11 ` [Qemu-devel] [PATCH v17 17/24] MAINTAINERS: Add RX Yoshinori Sato
2019-06-07  9:11 ` [Qemu-devel] [PATCH v17 18/24] target/rx: Disassemble rx_index_addr into a string Yoshinori Sato
2019-06-07  9:11 ` [Qemu-devel] [PATCH v17 19/24] target/rx: Replace operand with prt_ldmi in disassembler Yoshinori Sato
2019-06-07 13:42   ` Philippe Mathieu-Daudé [this message]
2019-06-07  9:11 ` [Qemu-devel] [PATCH v17 20/24] target/rx: Use prt_ldmi for XCHG_mr disassembly Yoshinori Sato
2019-06-07 13:43   ` Philippe Mathieu-Daudé
2019-06-07  9:11 ` [Qemu-devel] [PATCH v17 21/24] target/rx: Emit all disassembly in one prt() Yoshinori Sato
2019-06-07 13:42   ` Philippe Mathieu-Daudé
2019-06-07  9:11 ` [Qemu-devel] [PATCH v17 22/24] target/rx: Collect all bytes during disassembly Yoshinori Sato
2019-06-07 13:43   ` Philippe Mathieu-Daudé
2019-06-07  9:11 ` [Qemu-devel] [PATCH v17 23/24] target/rx: Dump bytes for each insn " Yoshinori Sato
2019-06-07 13:42   ` Philippe Mathieu-Daudé
2019-06-07  9:11 ` [Qemu-devel] [PATCH v17 24/24] target/rx: Remove suffix in cpu class Yoshinori Sato
2019-06-07 14:04   ` Philippe Mathieu-Daudé
2019-06-07 11:46 ` [Qemu-devel] [PATCH v17 00/24] Add RX archtecture support no-reply
2019-06-07 13:25 ` no-reply
2019-06-07 14:06 ` Philippe Mathieu-Daudé
2019-06-07 17:12 ` no-reply

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