From: Jiangyifei via <qemu-devel@nongnu.org>
To: Richard Henderson <richard.henderson@linaro.org>,
"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
"qemu-riscv@nongnu.org" <qemu-riscv@nongnu.org>
Cc: "bin.meng@windriver.com" <bin.meng@windriver.com>,
"limingwang (A)" <limingwang@huawei.com>,
"kvm@vger.kernel.org" <kvm@vger.kernel.org>,
"libvir-list@redhat.com" <libvir-list@redhat.com>,
"anup.patel@wdc.com" <anup.patel@wdc.com>,
"wanbo (G)" <wanbo13@huawei.com>,
"Alistair.Francis@wdc.com" <Alistair.Francis@wdc.com>,
"kvm-riscv@lists.infradead.org" <kvm-riscv@lists.infradead.org>,
"Wanghaibin (D)" <wanghaibin.wang@huawei.com>,
"palmer@dabbelt.com" <palmer@dabbelt.com>,
"Fanliang (EulerOS)" <fanliang@huawei.com>,
"Wubin (H)" <wu.wubin@huawei.com>
Subject: RE: [PATCH v1 12/12] target/riscv: Support virtual time context synchronization
Date: Fri, 10 Dec 2021 10:03:40 +0000 [thread overview]
Message-ID: <e30f810bbb1349f6883204cfeebd503b@huawei.com> (raw)
In-Reply-To: <d9c9196a-692c-cbcf-339b-8e84ecde7cee@linaro.org>
> -----Original Message-----
> From: Richard Henderson [mailto:richard.henderson@linaro.org]
> Sent: Sunday, November 21, 2021 6:35 AM
> To: Jiangyifei <jiangyifei@huawei.com>; qemu-devel@nongnu.org;
> qemu-riscv@nongnu.org
> Cc: bin.meng@windriver.com; limingwang (A) <limingwang@huawei.com>;
> kvm@vger.kernel.org; libvir-list@redhat.com; anup.patel@wdc.com; wanbo (G)
> <wanbo13@huawei.com>; Alistair.Francis@wdc.com;
> kvm-riscv@lists.infradead.org; Wanghaibin (D)
> <wanghaibin.wang@huawei.com>; palmer@dabbelt.com; Fanliang (EulerOS)
> <fanliang@huawei.com>; Wubin (H) <wu.wubin@huawei.com>
> Subject: Re: [PATCH v1 12/12] target/riscv: Support virtual time context
> synchronization
>
> On 11/20/21 8:46 AM, Yifei Jiang wrote:
> > const VMStateDescription vmstate_riscv_cpu = {
> > .name = "cpu",
> > .version_id = 3,
> > .minimum_version_id = 3,
> > + .post_load = cpu_post_load,
> > .fields = (VMStateField[]) {
> > VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
> > VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32), @@ -211,6
> > +221,10 @@ const VMStateDescription vmstate_riscv_cpu = {
> > VMSTATE_UINT64(env.mtohost, RISCVCPU),
> > VMSTATE_UINT64(env.timecmp, RISCVCPU),
> >
> > + VMSTATE_UINT64(env.kvm_timer_time, RISCVCPU),
> > + VMSTATE_UINT64(env.kvm_timer_compare, RISCVCPU),
> > + VMSTATE_UINT64(env.kvm_timer_state, RISCVCPU),
> > +
> > VMSTATE_END_OF_LIST()
> > },
>
> Can't alter VMStateDescription.fields without bumping version.
>
> If this is really kvm-only state, consider placing it into a subsection. But I
> worry about kvm-only state because ideally we'd be able to migrate between
> tcg and kvm (if only for debugging).
>
>
> r~
Thanks, I will update the version in the next series and place it into a subsection.
Yifei
next prev parent reply other threads:[~2021-12-10 10:05 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-20 7:46 [PATCH v1 00/12] Add riscv kvm accel support Yifei Jiang
2021-11-20 7:46 ` [PATCH v1 01/12] update-linux-headers: Add asm-riscv/kvm.h Yifei Jiang
2021-11-23 6:13 ` Alistair Francis
2021-12-03 5:07 ` Anup Patel
2021-11-20 7:46 ` [PATCH v1 02/12] target/riscv: Add target/riscv/kvm.c to place the public kvm interface Yifei Jiang
2021-12-03 5:08 ` Anup Patel
2021-11-20 7:46 ` [PATCH v1 03/12] target/riscv: Implement function kvm_arch_init_vcpu Yifei Jiang
2021-11-20 22:19 ` Richard Henderson
2021-12-10 9:55 ` Jiangyifei via
2021-11-20 7:46 ` [PATCH v1 04/12] target/riscv: Implement kvm_arch_get_registers Yifei Jiang
2021-12-03 6:20 ` Anup Patel
2021-12-10 9:57 ` Jiangyifei via
2021-11-20 7:46 ` [PATCH v1 05/12] target/riscv: Implement kvm_arch_put_registers Yifei Jiang
2021-12-03 6:22 ` Anup Patel
2021-12-10 9:58 ` Jiangyifei via
2021-11-20 7:46 ` [PATCH v1 06/12] target/riscv: Support start kernel directly by KVM Yifei Jiang
2021-12-03 6:31 ` Anup Patel
2021-12-10 10:00 ` Jiangyifei via
2021-11-20 7:46 ` [PATCH v1 07/12] target/riscv: Support setting external interrupt " Yifei Jiang
2021-12-03 9:15 ` Anup Patel
2021-12-10 10:01 ` Jiangyifei via
2021-11-20 7:46 ` [PATCH v1 08/12] target/riscv: Handle KVM_EXIT_RISCV_SBI exit Yifei Jiang
2021-11-20 12:24 ` Philippe Mathieu-Daudé
2021-12-10 10:02 ` Jiangyifei via
2021-11-20 7:46 ` [PATCH v1 09/12] target/riscv: Add host cpu type Yifei Jiang
2021-12-03 9:26 ` Anup Patel
2021-11-20 7:46 ` [PATCH v1 10/12] target/riscv: Add kvm_riscv_get/put_regs_timer Yifei Jiang
2021-12-03 9:38 ` Anup Patel
2021-12-10 10:03 ` Jiangyifei via
2021-11-20 7:46 ` [PATCH v1 11/12] target/riscv: Implement virtual time adjusting with vm state changing Yifei Jiang
2021-11-20 7:46 ` [PATCH v1 12/12] target/riscv: Support virtual time context synchronization Yifei Jiang
2021-11-20 22:34 ` Richard Henderson
2021-12-10 10:03 ` Jiangyifei via [this message]
2021-12-10 10:11 ` Paolo Bonzini
2021-12-03 8:41 ` [PATCH v1 00/12] Add riscv kvm accel support Michal Prívozník
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