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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 10/19/23 03:46, Paolo Bonzini wrote: > This includes: > > - implementing SHA and CMPccXADD instruction extensions > > - introducing a new mechanism for flags writeback that avoids a > tricky failure > > - converting the more orthogonal parts of the one-byte opcode > map, as well as the CMOVcc and SETcc instructions. > > Tested by booting several 32-bit and 64-bit guests. > > The new decoder produces roughly 2% more ops, but after optimization there > are just 0.5% more and almost all of them come from cmp instructions. > For some reason that I have not investigated, these end up with an extra > mov even after optimization: > > sub_i64 tmp0,rax,$0x33 > mov_i64 cc_src,$0x33 mov_i64 cc_dst,tmp0 > sub_i64 cc_dst,rax,$0x33 mov_i64 cc_src,$0x33 > discard cc_src2 discard cc_src2 > discard cc_op discard cc_op > > It could be easily fixed by not reusing gen_SUB for cmp instructions, > or by debugging what goes on in the optimizer. However, it does not > result in larger assembly. This is expected behaviour out of the tcg optimizer. We don't forward-propagate outputs at that point. But during register allocation of the "mov cc_dst,tmp0" opcode, we will see that tmp0 is dead and re-assign the register from tmp0 to cc_dst without emitting an host instruction. r~