From: Gustavo Romero <gustavo.romero@linaro.org>
To: Richard Henderson <richard.henderson@linaro.org>, qemu-devel@nongnu.org
Subject: Re: [PULL 00/76] target-arm queue
Date: Fri, 10 Oct 2025 16:58:27 -0300 [thread overview]
Message-ID: <e3314d25-dd8a-46a9-bbfc-44fba387099a@linaro.org> (raw)
In-Reply-To: <35087274-df34-4528-88a2-d855768fb5af@linaro.org>
Hi,
On 10/10/25 16:03, Richard Henderson wrote:
> On 10/10/25 06:04, Peter Maydell wrote:
>> Hi; this is another target-arm pullreq. It's a big one but it's
>> only two series: FEAT_MEC and FEAT_GCS.
>>
>> thanks
>> -- PMM
>>
>> The following changes since commit 94474a7733a57365d5a27efc28c05462e90e8944:
>>
>> Merge tag 'pull-loongarch-20251009' ofhttps://github.com/gaosong715/qemu into staging (2025-10-09 07:59:29 -0700)
>>
>> are available in the Git repository at:
>>
>> https://gitlab.com/pm215/qemu.git tags/pull-target-arm-20251010
>>
>> for you to fetch changes up to 00936783abf77ebb47a78312a2e6500c6a13d938:
>>
>> target/arm: Enable FEAT_MEC in -cpu max (2025-10-10 13:22:05 +0100)
>>
>> ----------------------------------------------------------------
>> target-arm queue:
>> * Implement FEAT_GCS
>> * Implement FEAT_MEC
>
> Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/10.2 as appropriate.
Could somebody give me access to https://wiki.qemu.org/ChangeLog/10.2, please?
Cheers,
Gustavo
next prev parent reply other threads:[~2025-10-10 19:59 UTC|newest]
Thread overview: 80+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-10 13:04 [PULL 00/76] target-arm queue Peter Maydell
2025-10-10 13:04 ` [PULL 01/76] tests/functional: update tests using TF-A/TF-RMM to support FEAT_GCS Peter Maydell
2025-10-10 13:04 ` [PULL 02/76] target/arm: Add isar feature test for FEAT_S1PIE, FEAT_S2PIE Peter Maydell
2025-10-10 13:04 ` [PULL 03/76] target/arm: Enable TCR2_ELx.PIE Peter Maydell
2025-10-10 13:04 ` [PULL 04/76] target/arm: Implement PIR_ELx, PIRE0_ELx, S2PIR_EL2 registers Peter Maydell
2025-10-10 13:04 ` [PULL 05/76] target/arm: Force HPD for stage2 translations Peter Maydell
2025-10-10 13:04 ` [PULL 06/76] target/arm: Cache NV1 early in get_phys_addr_lpae Peter Maydell
2025-10-10 13:04 ` [PULL 07/76] target/arm: Populate PIE in aa64_va_parameters Peter Maydell
2025-10-10 13:04 ` [PULL 08/76] target/arm: Implement get_S1prot_indirect Peter Maydell
2025-10-10 13:04 ` [PULL 09/76] target/arm: Implement get_S2prot_indirect Peter Maydell
2025-10-10 13:04 ` [PULL 10/76] target/arm: Expand CPUARMState.exception.syndrome to 64 bits Peter Maydell
2025-10-10 13:04 ` [PULL 11/76] target/arm: Expand syndrome parameter to raise_exception* Peter Maydell
2025-10-10 13:04 ` [PULL 12/76] target/arm: Implement dirtybit check for PIE Peter Maydell
2025-10-10 13:04 ` [PULL 13/76] target/arm: Enable FEAT_S1PIE and FEAT_S2PIE on -cpu max Peter Maydell
2025-10-10 13:04 ` [PULL 14/76] include/exec/memopidx: Adjust for 32 mmu indexes Peter Maydell
2025-10-10 13:04 ` [PULL 15/76] include/hw/core/cpu: Widen MMUIdxMap Peter Maydell
2025-10-10 13:04 ` [PULL 16/76] target/arm: Split out mmuidx.h from cpu.h Peter Maydell
2025-10-10 13:04 ` [PULL 17/76] target/arm: Convert arm_mmu_idx_to_el from switch to table Peter Maydell
2025-10-10 13:04 ` [PULL 18/76] target/arm: Remove unused env argument from regime_el Peter Maydell
2025-10-10 13:04 ` [PULL 19/76] target/arm: Convert regime_el from switch to table Peter Maydell
2025-10-10 13:04 ` [PULL 20/76] target/arm: Convert regime_has_2_ranges " Peter Maydell
2025-10-10 13:04 ` [PULL 21/76] target/arm: Remove unused env argument from regime_is_pan Peter Maydell
2025-10-10 13:04 ` [PULL 22/76] target/arm: Convert regime_is_pan from switch to table Peter Maydell
2025-10-10 13:04 ` [PULL 23/76] target/arm: Remove unused env argument from regime_is_user Peter Maydell
2025-10-10 13:04 ` [PULL 24/76] target/arm: Convert regime_is_user from switch to table Peter Maydell
2025-10-10 13:04 ` [PULL 25/76] target/arm: Convert arm_mmu_idx_is_stage1_of_2 " Peter Maydell
2025-10-10 13:04 ` [PULL 26/76] target/arm: Convert regime_is_stage2 " Peter Maydell
2025-10-10 13:04 ` [PULL 27/76] target/arm: Introduce mmu indexes for GCS Peter Maydell
2025-10-10 13:04 ` [PULL 28/76] target/arm: Introduce regime_to_gcs Peter Maydell
2025-10-10 13:04 ` [PULL 29/76] target/arm: Support page protections for GCS mmu indexes Peter Maydell
2025-10-10 13:04 ` [PULL 30/76] target/arm: Implement gcs bit for data abort Peter Maydell
2025-10-10 13:04 ` [PULL 31/76] target/arm: Add GCS cpregs Peter Maydell
2025-10-10 13:04 ` [PULL 32/76] target/arm: Add GCS enable and trap levels to DisasContext Peter Maydell
2025-10-10 13:04 ` [PULL 33/76] target/arm: Implement FEAT_CHK Peter Maydell
2025-10-10 13:04 ` [PULL 34/76] target/arm: Make helper_exception_return system-only Peter Maydell
2025-10-10 13:04 ` [PULL 35/76] target/arm: Export cpsr_{read_for, write_from}_spsr_elx Peter Maydell
2025-10-10 13:04 ` [PULL 36/76] target/arm: Expand pstate to 64 bits Peter Maydell
2025-10-10 13:04 ` [PULL 37/76] target/arm: Add syndrome data for EC_GCS Peter Maydell
2025-10-10 13:04 ` [PULL 38/76] target/arm: Add arm_hcr_el2_nvx_eff Peter Maydell
2025-10-10 13:04 ` [PULL 39/76] target/arm: Use arm_hcr_el2_nvx_eff in access_nv1 Peter Maydell
2025-10-10 13:04 ` [PULL 40/76] target/arm: Split out access_nv1_with_nvx Peter Maydell
2025-10-10 13:04 ` [PULL 41/76] target/arm: Implement EXLOCKException for ELR_ELx and SPSR_ELx Peter Maydell
2025-10-10 13:04 ` [PULL 42/76] target/arm: Split {full,core}_a64_user_mem_index Peter Maydell
2025-10-10 13:04 ` [PULL 43/76] target/arm: Introduce delay_exception{_el} Peter Maydell
2025-10-10 13:04 ` [PULL 44/76] target/arm: Emit HSTR trap exception out of line Peter Maydell
2025-10-10 13:04 ` [PULL 45/76] target/arm: Emit v7m LTPSIZE " Peter Maydell
2025-10-10 13:04 ` [PULL 46/76] target/arm: Implement GCSSTR, GCSSTTR Peter Maydell
2025-10-10 13:04 ` [PULL 47/76] target/arm: Implement GCSB Peter Maydell
2025-10-10 13:04 ` [PULL 48/76] target/arm: Implement GCSPUSHM Peter Maydell
2025-10-10 13:05 ` [PULL 49/76] target/arm: Implement GCSPOPM Peter Maydell
2025-10-10 13:05 ` [PULL 50/76] target/arm: Implement GCSPUSHX Peter Maydell
2025-10-10 13:05 ` [PULL 51/76] target/arm: Implement GCSPOPX Peter Maydell
2025-10-10 13:05 ` [PULL 52/76] target/arm: Implement GCSPOPCX Peter Maydell
2025-10-10 13:05 ` [PULL 53/76] target/arm: Implement GCSSS1 Peter Maydell
2025-10-10 13:05 ` [PULL 54/76] target/arm: Implement GCSSS2 Peter Maydell
2025-10-10 13:05 ` [PULL 55/76] target/arm: Add gcs record for BL Peter Maydell
2025-10-10 13:05 ` [PULL 56/76] target/arm: Add gcs record for BLR Peter Maydell
2025-10-10 13:05 ` [PULL 57/76] target/arm: Add gcs record for BLR with PAuth Peter Maydell
2025-10-10 13:05 ` [PULL 58/76] target/arm: Load gcs record for RET Peter Maydell
2025-10-10 13:05 ` [PULL 59/76] target/arm: Load gcs record for RET with PAuth Peter Maydell
2025-10-10 13:05 ` [PULL 60/76] target/arm: Copy EXLOCKEn to EXLOCK on exception to the same EL Peter Maydell
2025-10-10 13:05 ` [PULL 61/76] target/arm: Implement EXLOCK check during exception return Peter Maydell
2025-10-10 13:05 ` [PULL 62/76] target/arm: Enable FEAT_GCS with -cpu max Peter Maydell
2025-10-10 13:05 ` [PULL 63/76] linux-user/aarch64: Implement prctls for GCS Peter Maydell
2025-10-10 13:05 ` [PULL 64/76] linux-user/aarch64: Allocate new gcs stack on clone Peter Maydell
2025-10-10 13:05 ` [PULL 65/76] linux-user/aarch64: Release gcs stack on thread exit Peter Maydell
2025-10-10 13:05 ` [PULL 66/76] linux-user/aarch64: Implement map_shadow_stack syscall Peter Maydell
2025-10-10 13:05 ` [PULL 67/76] target/arm: Enable GCSPR_EL0 for read in user-mode Peter Maydell
2025-10-10 13:05 ` [PULL 68/76] linux-user/aarch64: Inject SIGSEGV for GCS faults Peter Maydell
2025-10-10 13:05 ` [PULL 69/76] linux-user/aarch64: Generate GCS signal records Peter Maydell
2025-10-10 13:05 ` [PULL 70/76] linux-user/aarch64: Enable GCS in HWCAP Peter Maydell
2025-10-10 13:05 ` [PULL 71/76] tests/tcg/aarch64: Add gcsstr Peter Maydell
2025-10-10 13:05 ` [PULL 72/76] tests/tcg/aarch64: Add gcspushm Peter Maydell
2025-10-10 13:05 ` [PULL 73/76] tests/tcg/aarch64: Add gcsss Peter Maydell
2025-10-10 13:05 ` [PULL 74/76] target/arm: Add a cpreg flag to indicate no trap in NV Peter Maydell
2025-10-10 13:05 ` [PULL 75/76] target/arm: Implement FEAT_MEC registers Peter Maydell
2025-10-10 13:05 ` [PULL 76/76] target/arm: Enable FEAT_MEC in -cpu max Peter Maydell
2025-10-10 19:03 ` [PULL 00/76] target-arm queue Richard Henderson
2025-10-10 19:58 ` Gustavo Romero [this message]
2025-10-12 19:58 ` Peter Maydell
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=e3314d25-dd8a-46a9-bbfc-44fba387099a@linaro.org \
--to=gustavo.romero@linaro.org \
--cc=qemu-devel@nongnu.org \
--cc=richard.henderson@linaro.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).