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[88.21.202.78]) by smtp.gmail.com with ESMTPSA id d22sm6904813wmd.39.2020.02.11.22.48.12 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 11 Feb 2020 22:48:12 -0800 (PST) Subject: Re: [PATCH 06/13] target/arm: Use FIELD macros for clearing ID_DFR0 PERFMON field To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20200211173726.22541-1-peter.maydell@linaro.org> <20200211173726.22541-7-peter.maydell@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Wed, 12 Feb 2020 07:48:11 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 MIME-Version: 1.0 In-Reply-To: <20200211173726.22541-7-peter.maydell@linaro.org> Content-Language: en-US X-MC-Unique: fq4NnM6DP6ma3zJGh1d9cw-1 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 205.139.110.120 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eric Auger , Aaron Lindsay , Richard Henderson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 2/11/20 6:37 PM, Peter Maydell wrote: > We already define FIELD macros for ID_DFR0, so use them in the > one place where we're doing direct bit value manipulation. >=20 > Signed-off-by: Peter Maydell > --- > We have lots of this non-FIELD style in the code, of course; > I change this one purely because it otherwise looks a bit odd > sat next to the ID_AA64DFR0 line that was changed in the previous > patch... > --- > target/arm/cpu.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) >=20 > diff --git a/target/arm/cpu.c b/target/arm/cpu.c > index dc582da8fa4..e7858b073b5 100644 > --- a/target/arm/cpu.c > +++ b/target/arm/cpu.c > @@ -1603,7 +1603,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) > #endif > } else { > cpu->id_aa64dfr0 =3D FIELD_DP32(cpu->id_aa64dfr0, ID_AA64DFR0, = PMUVER, 0); While this one should be FIELD_DP64(), > - cpu->id_dfr0 &=3D ~(0xf << 24); > + cpu->id_dfr0 =3D FIELD_DP32(cpu->id_dfr0, ID_DFR0, PERFMON, 0); this one is correct. Reviewed-by: Philippe Mathieu-Daud=C3=A9 > cpu->pmceid0 =3D 0; > cpu->pmceid1 =3D 0; > } >=20