From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: Kinsey Moore <kinsey.moore@oarcorp.com>, qemu-devel@nongnu.org
Subject: Re: [PATCH v2] hw/arm/xlnx: Connect secondary CGEM IRQs
Date: Sun, 18 Jun 2023 00:50:47 +0200 [thread overview]
Message-ID: <e36a681f-53e2-8379-078e-25e43fc3966e@linaro.org> (raw)
In-Reply-To: <20230616143803.73926-1-kinsey.moore@oarcorp.com>
On 16/6/23 16:38, Kinsey Moore wrote:
> The Cadence GEM peripherals as configured for Zynq MPSoC and Versal
> platforms have two priority queues with separate interrupt sources for
> each. If the interrupt source for the second priority queue is not
> connected, they work in polling mode only. This change connects the
> second interrupt source for platforms where it is available. This patch
> has been tested using the lwIP stack with a Xilinx-supplied driver from
> their embeddedsw repository.
>
> Signed-off-by: Kinsey Moore <kinsey.moore@oarcorp.com>
> ---
> hw/arm/xlnx-versal.c | 12 +++++++++++-
> hw/arm/xlnx-zynqmp.c | 11 ++++++++++-
> include/hw/arm/xlnx-versal.h | 1 +
> include/hw/arm/xlnx-zynqmp.h | 1 +
> 4 files changed, 23 insertions(+), 2 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
next prev parent reply other threads:[~2023-06-17 22:51 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-16 14:38 [PATCH v2] hw/arm/xlnx: Connect secondary CGEM IRQs Kinsey Moore
2023-06-16 20:25 ` Francisco Iglesias
2023-06-17 22:50 ` Philippe Mathieu-Daudé [this message]
2023-07-10 14:09 ` Francisco Iglesias
2024-09-25 19:34 ` Kinsey Moore
2024-09-27 16:48 ` Peter Maydell
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