[PATCH 0/3] target/arm: Add support for FEAT_SSBS

[PATCH 0/3] target/arm: Add support for FEAT_SSBS

[Rebecca Cran]

Add support for FEAT_SSBS, Speculative Store Bypass Safe. SSBS is an
optional feature in ARMv8.0 and is mandatory in ARMv8.5.

Rebecca Cran (3):
  target/arm: Add support for FEAT_SSBS, Speculative Store Bypass Safe
  target/arm: Enable FEAT_SSBS for "max" AARCH64 CPU
  target/arm: Set ID_PFR2.SSBS to 1 for "max" 32-bit CPU

 target/arm/cpu.c           |  4 ++
 target/arm/cpu.h           | 15 +++++-
 target/arm/cpu64.c         |  5 ++
 target/arm/helper-a64.c    |  6 +++
 target/arm/helper.c        | 52 ++++++++++++++++++++
 target/arm/internals.h     |  6 +++
 target/arm/translate-a64.c | 12 +++++
 7 files changed, 99 insertions(+), 1 deletion(-)

-- 
2.26.2

[PATCH 1/3] target/arm: Add support for FEAT_SSBS, Speculative Store Bypass Safe

[Rebecca Cran]

Add support for FEAT_SSBS. SSBS (Speculative Store Bypass Safe) is an
optional feature in ARMv8.0, and mandatory in ARMv8.5.

Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
---
 target/arm/cpu.h           | 15 +++++-
 target/arm/helper-a64.c    |  6 +++
 target/arm/helper.c        | 52 ++++++++++++++++++++
 target/arm/internals.h     |  6 +++
 target/arm/translate-a64.c | 12 +++++
 5 files changed, 90 insertions(+), 1 deletion(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index f240275407bc..a0a3ee7bcde9 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1201,6 +1201,7 @@ void pmu_init(ARMCPU *cpu);
 #define SCTLR_TE      (1U << 30) /* AArch32 only */
 #define SCTLR_EnIB    (1U << 30) /* v8.3, AArch64 only */
 #define SCTLR_EnIA    (1U << 31) /* v8.3, AArch64 only */
+#define SCTLR_DSSBS_32 (1U << 31) /* v8.5, AArch32 only */
 #define SCTLR_BT0     (1ULL << 35) /* v8.5-BTI */
 #define SCTLR_BT1     (1ULL << 36) /* v8.5-BTI */
 #define SCTLR_ITFSB   (1ULL << 37) /* v8.5-MemTag */
@@ -1208,7 +1209,7 @@ void pmu_init(ARMCPU *cpu);
 #define SCTLR_TCF     (3ULL << 40) /* v8.5-MemTag */
 #define SCTLR_ATA0    (1ULL << 42) /* v8.5-MemTag */
 #define SCTLR_ATA     (1ULL << 43) /* v8.5-MemTag */
-#define SCTLR_DSSBS   (1ULL << 44) /* v8.5 */
+#define SCTLR_DSSBS_64 (1ULL << 44) /* v8.5, AArch64 only */
 
 #define CPTR_TCPAC    (1U << 31)
 #define CPTR_TTA      (1U << 20)
@@ -1245,6 +1246,7 @@ void pmu_init(ARMCPU *cpu);
 #define CPSR_IL (1U << 20)
 #define CPSR_DIT (1U << 21)
 #define CPSR_PAN (1U << 22)
+#define CPSR_SSBS (1U << 23)
 #define CPSR_J (1U << 24)
 #define CPSR_IT_0_1 (3U << 25)
 #define CPSR_Q (1U << 27)
@@ -1307,6 +1309,7 @@ void pmu_init(ARMCPU *cpu);
 #define PSTATE_A (1U << 8)
 #define PSTATE_D (1U << 9)
 #define PSTATE_BTYPE (3U << 10)
+#define PSTATE_SSBS (1U << 12)
 #define PSTATE_IL (1U << 20)
 #define PSTATE_SS (1U << 21)
 #define PSTATE_PAN (1U << 22)
@@ -3883,6 +3886,11 @@ static inline bool isar_feature_aa32_dit(const ARMISARegisters *id)
     return FIELD_EX32(id->id_pfr0, ID_PFR0, DIT) != 0;
 }
 
+static inline bool isar_feature_aa32_ssbs(const ARMISARegisters *id)
+{
+    return FIELD_EX32(id->id_pfr2, ID_PFR2, SSBS) != 0;
+}
+
 /*
  * 64-bit feature tests via id registers.
  */
@@ -4137,6 +4145,11 @@ static inline bool isar_feature_aa64_dit(const ARMISARegisters *id)
     return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0;
 }
 
+static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id)
+{
+    return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0;
+}
+
 /*
  * Feature tests for "does this exist in either 32-bit or 64-bit?"
  */
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index ae611d73c2c4..6b204c5a67ac 100644
--- a/target/arm/helper-a64.c
+++ b/target/arm/helper-a64.c
@@ -960,6 +960,12 @@ static void cpsr_write_from_spsr_elx(CPUARMState *env,
         val |= CPSR_DIT;
     }
 
+    /* Move SSBS to the correct location for CPSR */
+    if (val & PSTATE_SSBS) {
+        val &= ~PSTATE_SSBS;
+        val |= CPSR_SSBS;
+    }
+
     mask = aarch32_cpsr_valid_mask(env->features, \
         &env_archcpu(env)->isar);
     cpsr_write(env, val, mask, CPSRWriteRaw);
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 0e1a3b94211c..a7c5dc3d420d 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -4450,6 +4450,24 @@ static const ARMCPRegInfo dit_reginfo = {
     .readfn = aa64_dit_read, .writefn = aa64_dit_write
 };
 
+static uint64_t aa64_ssbs_read(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+    return env->pstate & PSTATE_SSBS;
+}
+
+static void aa64_ssbs_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                           uint64_t value)
+{
+    env->pstate = (env->pstate & ~PSTATE_SSBS) | (value & PSTATE_SSBS);
+}
+
+static const ARMCPRegInfo ssbs_reginfo = {
+    .name = "SSBS", .state = ARM_CP_STATE_AA64,
+    .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 6,
+    .type = ARM_CP_NO_RAW, .access = PL0_RW,
+    .readfn = aa64_ssbs_read, .writefn = aa64_ssbs_write
+};
+
 static CPAccessResult aa64_cacheop_poc_access(CPUARMState *env,
                                               const ARMCPRegInfo *ri,
                                               bool isread)
@@ -8244,6 +8262,9 @@ void register_cp_regs_for_features(ARMCPU *cpu)
     if (cpu_isar_feature(aa64_dit, cpu)) {
         define_one_arm_cp_reg(cpu, &dit_reginfo);
     }
+    if (cpu_isar_feature(aa64_ssbs, cpu)) {
+        define_one_arm_cp_reg(cpu, &ssbs_reginfo);
+    }
 
     if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu)) {
         define_arm_cp_regs(cpu, vhe_reginfo);
@@ -9466,6 +9487,14 @@ static void take_aarch32_exception(CPUARMState *env, int new_mode,
     if (new_mode == ARM_CPU_MODE_HYP) {
         env->thumb = (env->cp15.sctlr_el[2] & SCTLR_TE) != 0;
         env->elr_el[2] = env->regs[15];
+
+        if (cpu_isar_feature(aa32_ssbs, env_archcpu(env))) {
+            if (env->cp15.hsctlr & SCTLR_DSSBS_32) {
+                env->uncached_cpsr |= CPSR_SSBS;
+            } else {
+                env->uncached_cpsr &= ~CPSR_SSBS;
+            }
+        }
     } else {
         /* CPSR.PAN is normally preserved preserved unless...  */
         if (cpu_isar_feature(aa32_pan, env_archcpu(env))) {
@@ -9486,6 +9515,14 @@ static void take_aarch32_exception(CPUARMState *env, int new_mode,
                 break;
             }
         }
+
+        if (cpu_isar_feature(aa32_ssbs, env_archcpu(env))) {
+            if (env->cp15.sctlr_el[new_el] & SCTLR_DSSBS_32) {
+                env->uncached_cpsr |= CPSR_SSBS;
+            } else {
+                env->uncached_cpsr &= ~CPSR_SSBS;
+            }
+        }
         /*
          * this is a lie, as there was no c1_sys on V4T/V5, but who cares
          * and we should just guard the thumb mode on V4
@@ -9809,6 +9846,13 @@ static uint32_t cpsr_read_for_spsr_elx(CPUARMState *env)
         ret &= ~CPSR_DIT;
         ret |= PSTATE_DIT;
     }
+
+    /* Move SSBS to the correct location for SPSR_ELx */
+    if (ret & CPSR_SSBS) {
+        ret &= ~CPSR_SSBS;
+        ret |= PSTATE_SSBS;
+    }
+
     /* Merge PSTATE.SS into SPSR_ELx */
     ret |= env->pstate & PSTATE_SS;
 
@@ -9973,6 +10017,14 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
         new_mode |= PSTATE_TCO;
     }
 
+    if (cpu_isar_feature(aa64_ssbs, cpu)) {
+        if (env->cp15.sctlr_el[new_el] & SCTLR_DSSBS_64) {
+            new_mode |= PSTATE_SSBS;
+        } else {
+            new_mode &= ~PSTATE_SSBS;
+        }
+    }
+
     pstate_write(env, PSTATE_DAIF | new_mode);
     env->aarch64 = 1;
     aarch64_restore_sp(env, new_el);
diff --git a/target/arm/internals.h b/target/arm/internals.h
index b251fe44506b..d92aeb57d782 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -1231,6 +1231,9 @@ static inline uint32_t aarch32_cpsr_valid_mask(uint64_t features,
     if (isar_feature_aa32_dit(id)) {
         valid |= CPSR_DIT;
     }
+    if (isar_feature_aa32_ssbs(id)) {
+        valid |= CPSR_SSBS;
+    }
 
     return valid;
 }
@@ -1252,6 +1255,9 @@ static inline uint32_t aarch64_pstate_valid_mask(const ARMISARegisters *id)
     if (isar_feature_aa64_dit(id)) {
         valid |= PSTATE_DIT;
     }
+    if (isar_feature_aa64_ssbs(id)) {
+        valid |= PSTATE_SSBS;
+    }
     if (isar_feature_aa64_mte(id)) {
         valid |= PSTATE_TCO;
     }
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 1c4b8d02f3b8..2372d55ea18b 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -1712,6 +1712,18 @@ static void handle_msr_i(DisasContext *s, uint32_t insn,
         /* There's no need to rebuild hflags because DIT is a nop */
         break;
 
+    case 0x19: /* SSBS */
+        if (!dc_isar_feature(aa64_ssbs, s)) {
+            goto do_unallocated;
+        }
+        if (crm & 1) {
+            set_pstate_bits(PSTATE_SSBS);
+        } else {
+            clear_pstate_bits(PSTATE_SSBS);
+        }
+        /* Don't need to rebuild hflags since SSBS is a nop */
+        break;
+
     case 0x1e: /* DAIFSet */
         t1 = tcg_const_i32(crm);
         gen_helper_msr_i_daifset(cpu_env, t1);
-- 
2.26.2

Re: [PATCH 1/3] target/arm: Add support for FEAT_SSBS, Speculative Store Bypass Safe

[Richard Henderson]

On 2/15/21 1:58 PM, Rebecca Cran wrote:
> @@ -960,6 +960,12 @@ static void cpsr_write_from_spsr_elx(CPUARMState *env,
>          val |= CPSR_DIT;
>      }
>  
> +    /* Move SSBS to the correct location for CPSR */
> +    if (val & PSTATE_SSBS) {
> +        val &= ~PSTATE_SSBS;
> +        val |= CPSR_SSBS;
> +    }

Incorrect.  SPSR_ELx leaves this at the same position as CPSR: bit 23.

>          }
> +
> +        if (cpu_isar_feature(aa32_ssbs, env_archcpu(env))) {
> +            if (env->cp15.sctlr_el[new_el] & SCTLR_DSSBS_32) {
> +                env->uncached_cpsr |= CPSR_SSBS;
> +            } else {
> +                env->uncached_cpsr &= ~CPSR_SSBS;
> +            }
> +        }

Hoist this so that it can be shared with the HYP branch (hsctlr is mapped to
sctlr_el[2] and HYP maps to el=2).

> @@ -9809,6 +9846,13 @@ static uint32_t cpsr_read_for_spsr_elx(CPUARMState *env)
>          ret &= ~CPSR_DIT;
>          ret |= PSTATE_DIT;
>      }
> +
> +    /* Move SSBS to the correct location for SPSR_ELx */
> +    if (ret & CPSR_SSBS) {
> +        ret &= ~CPSR_SSBS;
> +        ret |= PSTATE_SSBS;
> +    }

Incorrect, like in cpsr_write_from_spsr_elx.

> diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
> index 1c4b8d02f3b8..2372d55ea18b 100644
> --- a/target/arm/translate-a64.c
> +++ b/target/arm/translate-a64.c
> @@ -1712,6 +1712,18 @@ static void handle_msr_i(DisasContext *s, uint32_t insn,
>          /* There's no need to rebuild hflags because DIT is a nop */
>          break;
>  
> +    case 0x19: /* SSBS */
> +        if (!dc_isar_feature(aa64_ssbs, s)) {
> +            goto do_unallocated;
> +        }
> +        if (crm & 1) {
> +            set_pstate_bits(PSTATE_SSBS);
> +        } else {
> +            clear_pstate_bits(PSTATE_SSBS);
> +        }
> +        /* Don't need to rebuild hflags since SSBS is a nop */
> +        break;

Put this above DIT (0x1a) to keep the numbers in order.


r~

Re: [PATCH 1/3] target/arm: Add support for FEAT_SSBS, Speculative Store Bypass Safe

[Rebecca Cran]

On 2/15/21 5:19 PM, Richard Henderson wrote:
> On 2/15/21 1:58 PM, Rebecca Cran wrote:
>> @@ -960,6 +960,12 @@ static void cpsr_write_from_spsr_elx(CPUARMState *env,
>>           val |= CPSR_DIT;
>>       }
>>   
>> +    /* Move SSBS to the correct location for CPSR */
>> +    if (val & PSTATE_SSBS) {
>> +        val &= ~PSTATE_SSBS;
>> +        val |= CPSR_SSBS;
>> +    }
> 
> Incorrect.  SPSR_ELx leaves this at the same position as CPSR: bit 23.

Okay, I see where I'm going wrong now - SPSR_ELx has different formats 
for exceptions taken from aarch32 and aarch64 states, which I hadn't 
fully understood. I'll fix it.

-- 
Rebecca Cran

[PATCH 2/3] target/arm: Enable FEAT_SSBS for "max" AARCH64 CPU

[Rebecca Cran]

Set ID_AA64PFR1_EL1.SSBS to 2 and ID_PFR2.SSBS to 1.

Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
---
 target/arm/cpu64.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index c255f1bcc393..f0a9e968c9c1 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -674,6 +674,7 @@ static void aarch64_max_initfn(Object *obj)
 
         t = cpu->isar.id_aa64pfr1;
         t = FIELD_DP64(t, ID_AA64PFR1, BT, 1);
+        t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2);
         /*
          * Begin with full support for MTE. This will be downgraded to MTE=0
          * during realize if the board provides no tag memory, much like
@@ -723,6 +724,10 @@ static void aarch64_max_initfn(Object *obj)
         u = FIELD_DP32(u, ID_PFR0, DIT, 1);
         cpu->isar.id_pfr0 = u;
 
+        u = cpu->isar.id_pfr2;
+        u = FIELD_DP32(u, ID_PFR2, SSBS, 1);
+        cpu->isar.id_pfr2 = u;
+
         u = cpu->isar.id_mmfr3;
         u = FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */
         cpu->isar.id_mmfr3 = u;
-- 
2.26.2

Re: [PATCH 2/3] target/arm: Enable FEAT_SSBS for "max" AARCH64 CPU

[Richard Henderson]

On 2/15/21 1:58 PM, Rebecca Cran wrote:
> Set ID_AA64PFR1_EL1.SSBS to 2 and ID_PFR2.SSBS to 1.
> 
> Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
> ---
>  target/arm/cpu64.c | 5 +++++
>  1 file changed, 5 insertions(+)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

[PATCH 3/3] target/arm: Set ID_PFR2.SSBS to 1 for "max" 32-bit CPU

[Rebecca Cran]

Enable FEAT_SSBS for the "max" 32-bit CPU.

Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
---
 target/arm/cpu.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 5cf6c056c50f..88a6b183d325 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2206,6 +2206,10 @@ static void arm_max_initfn(Object *obj)
         t = cpu->isar.id_pfr0;
         t = FIELD_DP32(t, ID_PFR0, DIT, 1);
         cpu->isar.id_pfr0 = t;
+
+        t = cpu->isar.id_pfr2;
+        t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
+        cpu->isar.id_mfr2 = t;
     }
 #endif
 }
-- 
2.26.2

Re: [PATCH 3/3] target/arm: Set ID_PFR2.SSBS to 1 for "max" 32-bit CPU

[Richard Henderson]

On 2/15/21 1:58 PM, Rebecca Cran wrote:
> Enable FEAT_SSBS for the "max" 32-bit CPU.
> 
> Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
> ---
>  target/arm/cpu.c | 4 ++++
>  1 file changed, 4 insertions(+)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~