* [PATCH 00/17] RISU misc updates
@ 2024-05-11 11:53 Richard Henderson
2024-05-11 11:53 ` [PATCH 01/17] ppc64: Fix <sys/user.h> include order Richard Henderson
` (17 more replies)
0 siblings, 18 replies; 38+ messages in thread
From: Richard Henderson @ 2024-05-11 11:53 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
Some of these have been sitting on a branch for a couple of years.
Except perhaps the first, which I assume to be some sort of odd
build error from the time, they still seem reasonable.
There are some updates for SME1, but not yet the ZT register for SME2.
I'll get to that later after I've done the qemu linux-user work.
Finally, let's start phasing out raw binary test cases. We can
make it much easier for ourselves if we package test cases in ELF,
which "objdump -d" can parse directly, without having to be given
all sorts of "-b binary -m some-arch-flags" etc.
For future work, I plan to make changes to risugen so that it writes
out asm files and invokes the assembler and linker to produce the
final output file.
r~
Richard Henderson (17):
ppc64: Fix <sys/user.h> include order
Fix load_image error check for mmap
Standardize reginfo_dump_mismatch printing
Add --fulldump and --diffdup options
Remove return value from reginfo_dump
ppc64: Clean register values in reginfo_init
ppc64: Compare all bits of CCR
ppc64: Simplify reginfo_is_eq
ppc64: Clean up reginfo_dump
aarch64: Tidy reginfo dumping ahead of ZA state
aarch64: Add support for ZA storage
aarch64: Trivial SME test
Use bool for reginfo_is_eq
aarch64: Use bool for sve_{z,p}reg_is_eq
risu: Allow use of ELF test files
configure: Enable loongarch64
Build elf test cases instead of raw binaries
Makefile | 19 ++--
risu.h | 12 +-
risu_reginfo_aarch64.h | 52 ++++++++-
risu.c | 178 ++++++++++++++++++++++++++----
risu_ppc64.c | 3 +-
risu_reginfo_aarch64.c | 218 +++++++++++++++++++++++++++++--------
risu_reginfo_arm.c | 28 +++--
risu_reginfo_i386.c | 16 +--
risu_reginfo_loongarch64.c | 21 ++--
risu_reginfo_m68k.c | 45 +++-----
risu_reginfo_ppc64.c | 134 ++++++++---------------
risu_reginfo_s390x.c | 28 ++---
configure | 4 +-
test.ld | 12 ++
test_aarch64.s | 4 +-
test_arm.s | 16 ++-
test_i386.S | 4 +-
test_sme_aarch64.s | 63 +++++++++++
18 files changed, 588 insertions(+), 269 deletions(-)
create mode 100644 test.ld
create mode 100644 test_sme_aarch64.s
--
2.34.1
^ permalink raw reply [flat|nested] 38+ messages in thread
* [PATCH 01/17] ppc64: Fix <sys/user.h> include order
2024-05-11 11:53 [PATCH 00/17] RISU misc updates Richard Henderson
@ 2024-05-11 11:53 ` Richard Henderson
2024-05-15 13:11 ` Philippe Mathieu-Daudé
2024-05-11 11:53 ` [PATCH 02/17] Fix load_image error check for mmap Richard Henderson
` (16 subsequent siblings)
17 siblings, 1 reply; 38+ messages in thread
From: Richard Henderson @ 2024-05-11 11:53 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
risu_ppc64.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/risu_ppc64.c b/risu_ppc64.c
index 9df8d58..62cf6aa 100644
--- a/risu_ppc64.c
+++ b/risu_ppc64.c
@@ -11,9 +11,8 @@
* based on Peter Maydell's risu_arm.c
*****************************************************************************/
-#include <sys/user.h>
-
#include "risu.h"
+#include <sys/user.h>
void advance_pc(void *vuc)
{
--
2.34.1
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH 02/17] Fix load_image error check for mmap
2024-05-11 11:53 [PATCH 00/17] RISU misc updates Richard Henderson
2024-05-11 11:53 ` [PATCH 01/17] ppc64: Fix <sys/user.h> include order Richard Henderson
@ 2024-05-11 11:53 ` Richard Henderson
2024-05-15 12:51 ` Philippe Mathieu-Daudé
2024-05-11 11:53 ` [PATCH 03/17] Standardize reginfo_dump_mismatch printing Richard Henderson
` (15 subsequent siblings)
17 siblings, 1 reply; 38+ messages in thread
From: Richard Henderson @ 2024-05-11 11:53 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
mmap does not return null on failure, but MAP_FAILED.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
risu.c | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/risu.c b/risu.c
index 36fc82a..6b6295c 100644
--- a/risu.c
+++ b/risu.c
@@ -362,10 +362,9 @@ static void load_image(const char *imgfile)
/* Map writable because we include the memory area for store
* testing in the image.
*/
- addr =
- mmap(0, len, PROT_READ | PROT_WRITE | PROT_EXEC, MAP_PRIVATE, fd,
- 0);
- if (!addr) {
+ addr = mmap(0, len, PROT_READ | PROT_WRITE | PROT_EXEC,
+ MAP_PRIVATE, fd, 0);
+ if (addr == MAP_FAILED) {
perror("mmap");
exit(EXIT_FAILURE);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH 03/17] Standardize reginfo_dump_mismatch printing
2024-05-11 11:53 [PATCH 00/17] RISU misc updates Richard Henderson
2024-05-11 11:53 ` [PATCH 01/17] ppc64: Fix <sys/user.h> include order Richard Henderson
2024-05-11 11:53 ` [PATCH 02/17] Fix load_image error check for mmap Richard Henderson
@ 2024-05-11 11:53 ` Richard Henderson
2024-05-21 12:20 ` Peter Maydell
2024-05-11 11:53 ` [PATCH 04/17] Add --fulldump and --diffdup options Richard Henderson
` (14 subsequent siblings)
17 siblings, 1 reply; 38+ messages in thread
From: Richard Henderson @ 2024-05-11 11:53 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
Hoist the "master vs apprentice" label to apprentice(), since
we will want different labels for dumping. Remove all of the
"mismatch" text from reginfo_dump_mismatch -- just print "vs".
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
risu.h | 4 ++--
risu.c | 1 +
risu_reginfo_aarch64.c | 12 +++++-------
risu_reginfo_arm.c | 18 +++++++++---------
risu_reginfo_i386.c | 6 +-----
risu_reginfo_loongarch64.c | 11 ++++-------
risu_reginfo_m68k.c | 23 +++++++----------------
risu_reginfo_ppc64.c | 25 ++++++++++++-------------
risu_reginfo_s390x.c | 18 +++++++-----------
9 files changed, 48 insertions(+), 70 deletions(-)
diff --git a/risu.h b/risu.h
index 2c43384..1b87af2 100644
--- a/risu.h
+++ b/risu.h
@@ -123,8 +123,8 @@ int reginfo_is_eq(struct reginfo *r1, struct reginfo *r2);
/* print reginfo state to a stream, returns 1 on success, 0 on failure */
int reginfo_dump(struct reginfo *ri, FILE * f);
-/* reginfo_dump_mismatch: print mismatch details to a stream, ret nonzero=ok */
-int reginfo_dump_mismatch(struct reginfo *m, struct reginfo *a, FILE *f);
+/* reginfo_dump_mismatch: print mismatch details to a stream */
+void reginfo_dump_mismatch(struct reginfo *m, struct reginfo *a, FILE *f);
/* return size of reginfo */
int reginfo_size(struct reginfo *ri);
diff --git a/risu.c b/risu.c
index 6b6295c..9c31b8c 100644
--- a/risu.c
+++ b/risu.c
@@ -448,6 +448,7 @@ static int apprentice(void)
reginfo_dump(&ri[MASTER], stderr);
fprintf(stderr, "apprentice reginfo:\n");
reginfo_dump(&ri[APPRENTICE], stderr);
+ fprintf(stderr, "mismatch detail (master : apprentice):\n");
reginfo_dump_mismatch(&ri[MASTER], &ri[APPRENTICE], stderr);
return EXIT_FAILURE;
diff --git a/risu_reginfo_aarch64.c b/risu_reginfo_aarch64.c
index 1244454..da221d5 100644
--- a/risu_reginfo_aarch64.c
+++ b/risu_reginfo_aarch64.c
@@ -275,15 +275,15 @@ int reginfo_dump(struct reginfo *ri, FILE * f)
return !ferror(f);
}
-/* reginfo_dump_mismatch: print mismatch details to a stream, ret nonzero=ok */
-int reginfo_dump_mismatch(struct reginfo *m, struct reginfo *a, FILE * f)
+void reginfo_dump_mismatch(struct reginfo *m, struct reginfo *a, FILE * f)
{
int i;
- fprintf(f, "mismatch detail (master : apprentice):\n");
+
if (m->faulting_insn != a->faulting_insn) {
- fprintf(f, " faulting insn mismatch %08x vs %08x\n",
+ fprintf(f, " faulting insn: %08x vs %08x\n",
m->faulting_insn, a->faulting_insn);
}
+
for (i = 0; i < 31; i++) {
if (m->regs[i] != a->regs[i]) {
fprintf(f, " X%-2d : %016" PRIx64 " vs %016" PRIx64 "\n",
@@ -342,7 +342,7 @@ int reginfo_dump_mismatch(struct reginfo *m, struct reginfo *a, FILE * f)
sve_dump_preg_diff(f, vq, pm, pa);
}
}
- return !ferror(f);
+ return;
}
for (i = 0; i < 32; i++) {
@@ -356,6 +356,4 @@ int reginfo_dump_mismatch(struct reginfo *m, struct reginfo *a, FILE * f)
i, mv[1], mv[0], av[1], av[0]);
}
}
-
- return !ferror(f);
}
diff --git a/risu_reginfo_arm.c b/risu_reginfo_arm.c
index 85a39ac..221bd8a 100644
--- a/risu_reginfo_arm.c
+++ b/risu_reginfo_arm.c
@@ -183,32 +183,33 @@ int reginfo_dump(struct reginfo *ri, FILE *f)
return !ferror(f);
}
-int reginfo_dump_mismatch(struct reginfo *m, struct reginfo *a, FILE *f)
+void reginfo_dump_mismatch(struct reginfo *m, struct reginfo *a, FILE *f)
{
int i;
- fprintf(f, "mismatch detail (master : apprentice):\n");
if (m->faulting_insn_size != a->faulting_insn_size) {
- fprintf(f, " faulting insn size mismatch %d vs %d\n",
+ fprintf(f, " faulting insn size: %d vs %d\n",
m->faulting_insn_size, a->faulting_insn_size);
} else if (m->faulting_insn != a->faulting_insn) {
if (m->faulting_insn_size == 2) {
- fprintf(f, " faulting insn mismatch %04x vs %04x\n",
+ fprintf(f, " faulting insn: %04x vs %04x\n",
m->faulting_insn, a->faulting_insn);
} else {
- fprintf(f, " faulting insn mismatch %08x vs %08x\n",
+ fprintf(f, " faulting insn: %08x vs %08x\n",
m->faulting_insn, a->faulting_insn);
}
}
+
for (i = 0; i < 16; i++) {
if (m->gpreg[i] != a->gpreg[i]) {
- fprintf(f, " r%d: %08x vs %08x\n", i, m->gpreg[i],
- a->gpreg[i]);
+ fprintf(f, " r%d: %08x vs %08x\n", i, m->gpreg[i], a->gpreg[i]);
}
}
+
if (m->cpsr != a->cpsr) {
fprintf(f, " cpsr: %08x vs %08x\n", m->cpsr, a->cpsr);
}
+
for (i = 0; i < 32; i++) {
if (m->fpregs[i] != a->fpregs[i]) {
fprintf(f, " d%d: %016llx vs %016llx\n", i,
@@ -216,9 +217,8 @@ int reginfo_dump_mismatch(struct reginfo *m, struct reginfo *a, FILE *f)
(unsigned long long) a->fpregs[i]);
}
}
+
if (m->fpscr != a->fpscr) {
fprintf(f, " fpscr: %08x vs %08x\n", m->fpscr, a->fpscr);
}
-
- return !ferror(f);
}
diff --git a/risu_reginfo_i386.c b/risu_reginfo_i386.c
index 834b2ed..18d15ca 100644
--- a/risu_reginfo_i386.c
+++ b/risu_reginfo_i386.c
@@ -349,14 +349,12 @@ int reginfo_dump(struct reginfo *ri, FILE *f)
return !ferror(f);
}
-int reginfo_dump_mismatch(struct reginfo *m, struct reginfo *a, FILE *f)
+void reginfo_dump_mismatch(struct reginfo *m, struct reginfo *a, FILE *f)
{
int i, j, n, w;
uint64_t features;
char r;
- fprintf(f, "Mismatch (master v apprentice):\n");
-
for (i = 0; i < NGREG; i++) {
if (m->gregs[i] != a->gregs[i]) {
assert(regname[i]);
@@ -399,6 +397,4 @@ int reginfo_dump_mismatch(struct reginfo *m, struct reginfo *a, FILE *f)
i, m->kregs[i], a->kregs[i]);
}
}
-
- return !ferror(f);
}
diff --git a/risu_reginfo_loongarch64.c b/risu_reginfo_loongarch64.c
index 09a1eb6..630d6b2 100644
--- a/risu_reginfo_loongarch64.c
+++ b/risu_reginfo_loongarch64.c
@@ -195,18 +195,17 @@ int reginfo_dump(struct reginfo *ri, FILE * f)
return !ferror(f);
}
-/* reginfo_dump_mismatch: print mismatch details to a stream, ret nonzero=ok */
-int reginfo_dump_mismatch(struct reginfo *m, struct reginfo *a, FILE * f)
+/* reginfo_dump_mismatch: print mismatch details to a stream */
+void reginfo_dump_mismatch(struct reginfo *m, struct reginfo *a, FILE * f)
{
int i;
- fprintf(f, "mismatch detail (master : apprentice):\n");
if (m->vl != a->vl) {
- fprintf(f, " vl mismatch %08lx vs %08lx\n", m->vl, a->vl);
+ fprintf(f, " vl : %08lx vs %08lx\n", m->vl, a->vl);
}
if (m->faulting_insn != a->faulting_insn) {
- fprintf(f, " faulting insn mismatch %08x vs %08x\n",
+ fprintf(f, " insn : %08x vs %08x\n",
m->faulting_insn, a->faulting_insn);
}
/* r2:tp, r3:sp */
@@ -263,6 +262,4 @@ int reginfo_dump_mismatch(struct reginfo *m, struct reginfo *a, FILE * f)
}
}
}
-
- return !ferror(f);
}
diff --git a/risu_reginfo_m68k.c b/risu_reginfo_m68k.c
index e29da84..18ae1d8 100644
--- a/risu_reginfo_m68k.c
+++ b/risu_reginfo_m68k.c
@@ -118,13 +118,12 @@ int reginfo_dump(struct reginfo *ri, FILE *f)
return !ferror(f);
}
-int reginfo_dump_mismatch(struct reginfo *m, struct reginfo *a, FILE * f)
+void reginfo_dump_mismatch(struct reginfo *m, struct reginfo *a, FILE *f)
{
int i;
if (m->gregs[R_PS] != a->gregs[R_PS]) {
- fprintf(f, "Mismatch: Register PS\n");
- fprintf(f, "master: [%x] - apprentice: [%x]\n",
+ fprintf(f, " PS: %08x vs %08x\n",
m->gregs[R_PS], a->gregs[R_PS]);
}
@@ -133,22 +132,18 @@ int reginfo_dump_mismatch(struct reginfo *m, struct reginfo *a, FILE * f)
continue;
}
if (m->gregs[i] != a->gregs[i]) {
- fprintf(f, "Mismatch: Register %c%d\n", i < 8 ? 'D' : 'A',
- i % 8);
- fprintf(f, "master: [%x] - apprentice: [%x]\n", m->gregs[i],
- a->gregs[i]);
+ fprintf(f, " %c%d: %08x vs %08x\n",
+ i < 8 ? 'D' : 'A', i % 8, m->gregs[i], a->gregs[i]);
}
}
if (m->fpregs.f_pcr != a->fpregs.f_pcr) {
- fprintf(f, "Mismatch: Register FPCR\n");
- fprintf(f, "m: [%04x] != a: [%04x]\n",
+ fprintf(f, " FPCR: %04x vs %04x\n",
m->fpregs.f_pcr, a->fpregs.f_pcr);
}
if (m->fpregs.f_psr != a->fpregs.f_psr) {
- fprintf(f, "Mismatch: Register FPSR\n");
- fprintf(f, "m: [%08x] != a: [%08x]\n",
+ fprintf(f, " FPSR: %04x vs %04x\n",
m->fpregs.f_psr, a->fpregs.f_psr);
}
@@ -156,14 +151,10 @@ int reginfo_dump_mismatch(struct reginfo *m, struct reginfo *a, FILE * f)
if (m->fpregs.f_fpregs[i][0] != a->fpregs.f_fpregs[i][0] ||
m->fpregs.f_fpregs[i][1] != a->fpregs.f_fpregs[i][1] ||
m->fpregs.f_fpregs[i][2] != a->fpregs.f_fpregs[i][2]) {
- fprintf(f, "Mismatch: Register FP%d\n", i);
- fprintf(f, "m: [%08x %08x %08x] != a: [%08x %08x %08x]\n",
+ fprintf(f, " FP%d: %08x%08x%08x vs %08x%08x%08x\n", i,
m->fpregs.f_fpregs[i][0], m->fpregs.f_fpregs[i][1],
m->fpregs.f_fpregs[i][2], a->fpregs.f_fpregs[i][0],
a->fpregs.f_fpregs[i][1], a->fpregs.f_fpregs[i][2]);
}
}
-
-
- return !ferror(f);
}
diff --git a/risu_reginfo_ppc64.c b/risu_reginfo_ppc64.c
index bbdd63c..486bbf9 100644
--- a/risu_reginfo_ppc64.c
+++ b/risu_reginfo_ppc64.c
@@ -147,35 +147,35 @@ int reginfo_dump(struct reginfo *ri, FILE * f)
return !ferror(f);
}
-int reginfo_dump_mismatch(struct reginfo *m, struct reginfo *a, FILE *f)
+void reginfo_dump_mismatch(struct reginfo *m, struct reginfo *a, FILE *f)
{
int i;
+
for (i = 0; i < 32; i++) {
if (i == 1 || i == 13) {
continue;
}
-
if (m->gregs[i] != a->gregs[i]) {
- fprintf(f, "Mismatch: Register r%d\n", i);
- fprintf(f, "master: [%lx] - apprentice: [%lx]\n",
+ fprintf(f, "%*s%d: %016lx vs %016lx\n",
+ 6 - (1 < 10 ? 1 : 2), "r", i,
m->gregs[i], a->gregs[i]);
}
}
if (m->gregs[XER] != a->gregs[XER]) {
- fprintf(f, "Mismatch: XER\n");
- fprintf(f, "m: [%lx] != a: [%lx]\n", m->gregs[XER], a->gregs[XER]);
+ fprintf(f, "%6s: %016lx vs %016lx\n",
+ "xer", m->gregs[XER], a->gregs[XER]);
}
if (m->gregs[CCR] != a->gregs[CCR]) {
- fprintf(f, "Mismatch: Cond. Register\n");
- fprintf(f, "m: [%lx] != a: [%lx]\n", m->gregs[CCR], a->gregs[CCR]);
+ fprintf(f, "%6s: %016lx vs %016lx\n",
+ "ccr", m->gregs[CCR], a->gregs[CCR]);
}
for (i = 0; i < 32; i++) {
if (m->fpregs[i] != a->fpregs[i]) {
- fprintf(f, "Mismatch: Register f%d\n", i);
- fprintf(f, "m: [%016lx] != a: [%016lx]\n",
+ fprintf(f, "%*s%d: %016lx vs %016lx\n",
+ 6 - (i < 10 ? 1 : 2), "f", i,
m->fpregs[i], a->fpregs[i]);
}
}
@@ -186,13 +186,12 @@ int reginfo_dump_mismatch(struct reginfo *m, struct reginfo *a, FILE *f)
m->vrregs.vrregs[i][2] != a->vrregs.vrregs[i][2] ||
m->vrregs.vrregs[i][3] != a->vrregs.vrregs[i][3]) {
- fprintf(f, "Mismatch: Register vr%d\n", i);
- fprintf(f, "m: [%x, %x, %x, %x] != a: [%x, %x, %x, %x]\n",
+ fprintf(f, "%*s%d: %08x%08x%08x%08x vs %08x%08x%08x%08x\n",
+ 6 - (i < 10 ? 1 : 2), "vr", i,
m->vrregs.vrregs[i][0], m->vrregs.vrregs[i][1],
m->vrregs.vrregs[i][2], m->vrregs.vrregs[i][3],
a->vrregs.vrregs[i][0], a->vrregs.vrregs[i][1],
a->vrregs.vrregs[i][2], a->vrregs.vrregs[i][3]);
}
}
- return !ferror(f);
}
diff --git a/risu_reginfo_s390x.c b/risu_reginfo_s390x.c
index 3fd91b9..9c8fcfd 100644
--- a/risu_reginfo_s390x.c
+++ b/risu_reginfo_s390x.c
@@ -107,34 +107,30 @@ int reginfo_dump(struct reginfo *ri, FILE * f)
return !ferror(f);
}
-int reginfo_dump_mismatch(struct reginfo *m, struct reginfo *a, FILE *f)
+void reginfo_dump_mismatch(struct reginfo *m, struct reginfo *a, FILE *f)
{
int i;
if (m->pc_offset != a->pc_offset) {
- fprintf(f, "Mismatch: PC offset master: [%016lx] - PC offset apprentice: [%016lx]\n",
+ fprintf(f, " PC : %016lx vs %016lx\n",
m->pc_offset, a->pc_offset);
}
for (i = 0; i < 16; i++) {
if (m->gprs[i] != a->gprs[i]) {
- fprintf(f, "Mismatch: r%d master: [%016lx] - r%d apprentice: [%016lx]\n",
- i, m->gprs[i], i, a->gprs[i]);
+ fprintf(f, " r%-2d : %016lx vs %016lx\n",
+ i, m->gprs[i], a->gprs[i]);
}
}
for (i = 0; i < 16; i++) {
if (*(uint64_t *)&m->fprs[i] != *(uint64_t *)&a->fprs[i]) {
- fprintf(f, "Mismatch: f%d master: [%016lx] - f%d apprentice: [%016lx]\n",
- i, *(uint64_t *)&m->fprs[i],
- i, *(uint64_t *)&a->fprs[i]);
+ fprintf(f, " f%-2d : %016lx vs %016lx\n",
+ i, *(uint64_t *)&m->fprs[i], *(uint64_t *)&a->fprs[i]);
}
}
if (m->fpc != a->fpc) {
- fprintf(f, "Mismatch: FPC master: [%08x] - FPC apprentice: [%08x]\n",
- m->fpc, a->fpc);
+ fprintf(f, " FPC : %08x vs %08x\n", m->fpc, a->fpc);
}
-
- return !ferror(f);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH 04/17] Add --fulldump and --diffdup options
2024-05-11 11:53 [PATCH 00/17] RISU misc updates Richard Henderson
` (2 preceding siblings ...)
2024-05-11 11:53 ` [PATCH 03/17] Standardize reginfo_dump_mismatch printing Richard Henderson
@ 2024-05-11 11:53 ` Richard Henderson
2024-05-11 11:53 ` [PATCH 05/17] Remove return value from reginfo_dump Richard Henderson
` (13 subsequent siblings)
17 siblings, 0 replies; 38+ messages in thread
From: Richard Henderson @ 2024-05-11 11:53 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
These allow the inspection of the trace files.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
risu.c | 117 +++++++++++++++++++++++++++++++++++++++++++++++++--------
1 file changed, 102 insertions(+), 15 deletions(-)
diff --git a/risu.c b/risu.c
index 9c31b8c..c28b4a5 100644
--- a/risu.c
+++ b/risu.c
@@ -483,23 +483,101 @@ static int apprentice(void)
}
}
-static int ismaster;
+static int dump_trace(bool isfull)
+{
+ RisuResult res;
+ int tick = 0;
+
+ while (1) {
+ struct reginfo *this_ri;
+
+ this_ri = &ri[tick & 1];
+ res = recv_register_info(this_ri);
+
+ switch (res) {
+ case RES_OK:
+ switch (header.risu_op) {
+ case OP_COMPARE:
+ case OP_TESTEND:
+ case OP_SIGILL:
+ printf("%s: (pc %#lx)\n", op_name(header.risu_op),
+ (unsigned long)header.pc);
+
+ if (isfull || tick == 0) {
+ reginfo_dump(this_ri, stdout);
+ } else {
+ struct reginfo *prev_ri = &ri[(tick - 1) & 1];
+
+ if (reginfo_is_eq(prev_ri, this_ri)) {
+ /*
+ * ??? There should never be no change -- at minimum
+ * PC should have advanced. But for completeness...
+ */
+ printf("change detail: none\n");
+ } else {
+ printf("change detail (prev : next):\n");
+ reginfo_dump_mismatch(prev_ri, this_ri, stdout);
+ }
+ }
+ putchar('\n');
+ if (header.risu_op == OP_TESTEND) {
+ return EXIT_SUCCESS;
+ }
+ tick++;
+ break;
+
+ case OP_COMPAREMEM:
+ /* TODO: Dump 8k of data? */
+ /* fall through */
+ default:
+ printf("%s\n", op_name(header.risu_op));
+ break;
+ }
+ break;
+
+ case RES_BAD_IO:
+ fprintf(stderr, "I/O error\n");
+ return EXIT_FAILURE;
+ case RES_BAD_MAGIC:
+ fprintf(stderr, "Unexpected magic number: %#08x\n", header.magic);
+ return EXIT_FAILURE;
+ case RES_BAD_SIZE:
+ fprintf(stderr, "Unexpected payload size: %u\n", header.size);
+ return EXIT_FAILURE;
+ case RES_BAD_OP:
+ fprintf(stderr, "Unexpected opcode: %d\n", header.risu_op);
+ return EXIT_FAILURE;
+ default:
+ fprintf(stderr, "Unexpected recv result %d\n", res);
+ return EXIT_FAILURE;
+ }
+ }
+}
+
+enum {
+ DO_APPRENTICE,
+ DO_MASTER,
+ DO_FULLDUMP,
+ DO_DIFFDUMP,
+};
+
+static int operation = DO_APPRENTICE;
static void usage(void)
{
fprintf(stderr,
- "Usage: risu [--master] [--host <ip>] [--port <port>] <image file>"
- "\n\n");
- fprintf(stderr,
- "Run through the pattern file verifying each instruction\n");
- fprintf(stderr, "between master and apprentice risu processes.\n\n");
- fprintf(stderr, "Options:\n");
- fprintf(stderr, " --master Be the master (server)\n");
- fprintf(stderr, " -t, --trace=FILE Record/playback " TRACE_TYPE " trace file\n");
- fprintf(stderr,
- " -h, --host=HOST Specify master host machine (apprentice only)"
- "\n");
- fprintf(stderr,
+ "Usage: risu [--master|--fulldump|--diffdump]\n"
+ " [--host <ip>] [--port <port>] <image file>\n"
+ "\n"
+ "Run through the pattern file verifying each instruction\n"
+ "between master and apprentice risu processes.\n"
+ "\n"
+ "Options:\n"
+ " --master Be the master (server)\n"
+ " --fulldump Dump each record\n"
+ " --diffdump Dump difference between each record\n"
+ " -t, --trace=FILE Record/playback " TRACE_TYPE " trace file\n"
+ " -h, --host=HOST Specify master host machine\n"
" -p, --port=PORT Specify the port to connect to/listen on "
"(default 9191)\n");
if (arch_extra_help) {
@@ -511,7 +589,9 @@ static struct option * setup_options(char **short_opts)
{
static struct option default_longopts[] = {
{"help", no_argument, 0, '?'},
- {"master", no_argument, &ismaster, 1},
+ {"master", no_argument, &operation, DO_MASTER},
+ {"fulldump", no_argument, &operation, DO_FULLDUMP},
+ {"diffdump", no_argument, &operation, DO_DIFFDUMP},
{"host", required_argument, 0, 'h'},
{"port", required_argument, 0, 'p'},
{"trace", required_argument, 0, 't'},
@@ -519,7 +599,7 @@ static struct option * setup_options(char **short_opts)
};
struct option *lopts = &default_longopts[0];
- *short_opts = "h:p:t:";
+ *short_opts = "d:h:p:t:";
if (arch_long_opts) {
const size_t osize = sizeof(struct option);
@@ -551,6 +631,7 @@ int main(int argc, char **argv)
struct option *longopts;
char *shortopts;
stack_t ss;
+ bool ismaster;
longopts = setup_options(&shortopts);
@@ -586,6 +667,8 @@ int main(int argc, char **argv)
}
}
+ ismaster = operation == DO_MASTER;
+
if (trace) {
if (strcmp(trace_fn, "-") == 0) {
comm_fd = ismaster ? STDOUT_FILENO : STDIN_FILENO;
@@ -609,6 +692,10 @@ int main(int argc, char **argv)
}
}
+ if (operation == DO_FULLDUMP || operation == DO_DIFFDUMP) {
+ return dump_trace(operation == DO_FULLDUMP);
+ }
+
imgfile = argv[optind];
if (!imgfile) {
fprintf(stderr, "Error: must specify image file name\n\n");
--
2.34.1
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH 05/17] Remove return value from reginfo_dump
2024-05-11 11:53 [PATCH 00/17] RISU misc updates Richard Henderson
` (3 preceding siblings ...)
2024-05-11 11:53 ` [PATCH 04/17] Add --fulldump and --diffdup options Richard Henderson
@ 2024-05-11 11:53 ` Richard Henderson
2024-05-15 12:52 ` Philippe Mathieu-Daudé
2024-05-11 11:53 ` [PATCH 06/17] ppc64: Clean register values in reginfo_init Richard Henderson
` (12 subsequent siblings)
17 siblings, 1 reply; 38+ messages in thread
From: Richard Henderson @ 2024-05-11 11:53 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
No uses actually checked the error indication. Even if we wanted
to check ferror on the stream, we should do that generically rather
than per arch.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
risu.h | 4 ++--
risu_reginfo_aarch64.c | 8 +++-----
risu_reginfo_arm.c | 6 ++----
risu_reginfo_i386.c | 6 ++----
risu_reginfo_loongarch64.c | 6 ++----
risu_reginfo_m68k.c | 6 ++----
risu_reginfo_ppc64.c | 6 ++----
risu_reginfo_s390x.c | 6 ++----
8 files changed, 17 insertions(+), 31 deletions(-)
diff --git a/risu.h b/risu.h
index 1b87af2..aa8cc22 100644
--- a/risu.h
+++ b/risu.h
@@ -120,8 +120,8 @@ void reginfo_init(struct reginfo *ri, ucontext_t *uc, void *siaddr);
/* return 1 if structs are equal, 0 otherwise. */
int reginfo_is_eq(struct reginfo *r1, struct reginfo *r2);
-/* print reginfo state to a stream, returns 1 on success, 0 on failure */
-int reginfo_dump(struct reginfo *ri, FILE * f);
+/* print reginfo state to a stream */
+void reginfo_dump(struct reginfo *ri, FILE *f);
/* reginfo_dump_mismatch: print mismatch details to a stream */
void reginfo_dump_mismatch(struct reginfo *m, struct reginfo *a, FILE *f);
diff --git a/risu_reginfo_aarch64.c b/risu_reginfo_aarch64.c
index da221d5..0161044 100644
--- a/risu_reginfo_aarch64.c
+++ b/risu_reginfo_aarch64.c
@@ -219,8 +219,8 @@ static void sve_dump_zreg_diff(FILE *f, int vq, const uint64_t *za,
}
}
-/* reginfo_dump: print state to a stream, returns nonzero on success */
-int reginfo_dump(struct reginfo *ri, FILE * f)
+/* reginfo_dump: print state to a stream */
+void reginfo_dump(struct reginfo *ri, FILE * f)
{
int i;
fprintf(f, " faulting insn %08x\n", ri->faulting_insn);
@@ -263,7 +263,7 @@ int reginfo_dump(struct reginfo *ri, FILE * f)
sve_dump_preg(f, vq, p);
fprintf(f, "\n");
}
- return !ferror(f);
+ return;
}
for (i = 0; i < 32; i++) {
@@ -271,8 +271,6 @@ int reginfo_dump(struct reginfo *ri, FILE * f)
fprintf(f, " V%-2d : %016" PRIx64 "%016" PRIx64 "\n",
i, v[1], v[0]);
}
-
- return !ferror(f);
}
void reginfo_dump_mismatch(struct reginfo *m, struct reginfo *a, FILE * f)
diff --git a/risu_reginfo_arm.c b/risu_reginfo_arm.c
index 221bd8a..0e179be 100644
--- a/risu_reginfo_arm.c
+++ b/risu_reginfo_arm.c
@@ -161,8 +161,8 @@ int reginfo_is_eq(struct reginfo *r1, struct reginfo *r2)
return memcmp(r1, r2, sizeof(*r1)) == 0; /* ok since we memset 0 */
}
-/* reginfo_dump: print the state to a stream, returns nonzero on success */
-int reginfo_dump(struct reginfo *ri, FILE *f)
+/* reginfo_dump: print the state to a stream */
+void reginfo_dump(struct reginfo *ri, FILE *f)
{
int i;
if (ri->faulting_insn_size == 2) {
@@ -179,8 +179,6 @@ int reginfo_dump(struct reginfo *ri, FILE *f)
i, (unsigned long long) ri->fpregs[i]);
}
fprintf(f, " fpscr: %08x\n", ri->fpscr);
-
- return !ferror(f);
}
void reginfo_dump_mismatch(struct reginfo *m, struct reginfo *a, FILE *f)
diff --git a/risu_reginfo_i386.c b/risu_reginfo_i386.c
index 18d15ca..f4cf9a3 100644
--- a/risu_reginfo_i386.c
+++ b/risu_reginfo_i386.c
@@ -310,8 +310,8 @@ static char get_vecletter(uint64_t features)
}
}
-/* reginfo_dump: print state to a stream, returns nonzero on success */
-int reginfo_dump(struct reginfo *ri, FILE *f)
+/* reginfo_dump: print state to a stream */
+void reginfo_dump(struct reginfo *ri, FILE *f)
{
uint64_t features;
int i, j, n, w;
@@ -345,8 +345,6 @@ int reginfo_dump(struct reginfo *ri, FILE *f)
fprintf(f, " k%-5d: %016" PRIx64 "\n", i, ri->kregs[i]);
}
}
-
- return !ferror(f);
}
void reginfo_dump_mismatch(struct reginfo *m, struct reginfo *a, FILE *f)
diff --git a/risu_reginfo_loongarch64.c b/risu_reginfo_loongarch64.c
index 630d6b2..060715f 100644
--- a/risu_reginfo_loongarch64.c
+++ b/risu_reginfo_loongarch64.c
@@ -159,8 +159,8 @@ int reginfo_is_eq(struct reginfo *r1, struct reginfo *r2)
return !memcmp(r1, r2, sizeof(*r1));
}
-/* reginfo_dump: print state to a stream, returns nonzero on success */
-int reginfo_dump(struct reginfo *ri, FILE * f)
+/* reginfo_dump: print state to a stream */
+void reginfo_dump(struct reginfo *ri, FILE * f)
{
int i;
fprintf(f, " faulting insn %08x\n", ri->faulting_insn);
@@ -191,8 +191,6 @@ int reginfo_dump(struct reginfo *ri, FILE * f)
fprintf(f, " vreg%-2d : %016lx\n", i, ri->vregs[4 * i]);
}
}
-
- return !ferror(f);
}
/* reginfo_dump_mismatch: print mismatch details to a stream */
diff --git a/risu_reginfo_m68k.c b/risu_reginfo_m68k.c
index 18ae1d8..a53244d 100644
--- a/risu_reginfo_m68k.c
+++ b/risu_reginfo_m68k.c
@@ -92,8 +92,8 @@ int reginfo_is_eq(struct reginfo *m, struct reginfo *a)
return 1;
}
-/* reginfo_dump: print state to a stream, returns nonzero on success */
-int reginfo_dump(struct reginfo *ri, FILE *f)
+/* reginfo_dump: print state to a stream */
+void reginfo_dump(struct reginfo *ri, FILE *f)
{
int i;
fprintf(f, " pc \e[1;101;37m0x%08x\e[0m\n", ri->pc);
@@ -114,8 +114,6 @@ int reginfo_dump(struct reginfo *ri, FILE *f)
}
fprintf(f, "\n");
-
- return !ferror(f);
}
void reginfo_dump_mismatch(struct reginfo *m, struct reginfo *a, FILE *f)
diff --git a/risu_reginfo_ppc64.c b/risu_reginfo_ppc64.c
index 486bbf9..fc69805 100644
--- a/risu_reginfo_ppc64.c
+++ b/risu_reginfo_ppc64.c
@@ -103,8 +103,8 @@ int reginfo_is_eq(struct reginfo *m, struct reginfo *a)
return 1;
}
-/* reginfo_dump: print state to a stream, returns nonzero on success */
-int reginfo_dump(struct reginfo *ri, FILE * f)
+/* reginfo_dump: print state to a stream */
+void reginfo_dump(struct reginfo *ri, FILE * f)
{
int i;
@@ -143,8 +143,6 @@ int reginfo_dump(struct reginfo *ri, FILE * f)
ri->vrregs.vrregs[i][0], ri->vrregs.vrregs[i][1],
ri->vrregs.vrregs[i][2], ri->vrregs.vrregs[i][3]);
}
-
- return !ferror(f);
}
void reginfo_dump_mismatch(struct reginfo *m, struct reginfo *a, FILE *f)
diff --git a/risu_reginfo_s390x.c b/risu_reginfo_s390x.c
index 9c8fcfd..cbf168e 100644
--- a/risu_reginfo_s390x.c
+++ b/risu_reginfo_s390x.c
@@ -82,8 +82,8 @@ int reginfo_is_eq(struct reginfo *m, struct reginfo *a)
memcmp(&m->fprs, &a->fprs, sizeof(m->fprs)) == 0;
}
-/* reginfo_dump: print state to a stream, returns nonzero on success */
-int reginfo_dump(struct reginfo *ri, FILE * f)
+/* reginfo_dump: print state to a stream */
+void reginfo_dump(struct reginfo *ri, FILE * f)
{
int i;
@@ -103,8 +103,6 @@ int reginfo_dump(struct reginfo *ri, FILE * f)
i + 8, *(uint64_t *)&ri->fprs[i + 8]);
}
fprintf(f, "\tFPC: %8x\n\n", ri->fpc);
-
- return !ferror(f);
}
void reginfo_dump_mismatch(struct reginfo *m, struct reginfo *a, FILE *f)
--
2.34.1
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH 06/17] ppc64: Clean register values in reginfo_init
2024-05-11 11:53 [PATCH 00/17] RISU misc updates Richard Henderson
` (4 preceding siblings ...)
2024-05-11 11:53 ` [PATCH 05/17] Remove return value from reginfo_dump Richard Henderson
@ 2024-05-11 11:53 ` Richard Henderson
2024-05-21 12:22 ` Peter Maydell
2024-05-11 11:53 ` [PATCH 07/17] ppc64: Compare all bits of CCR Richard Henderson
` (11 subsequent siblings)
17 siblings, 1 reply; 38+ messages in thread
From: Richard Henderson @ 2024-05-11 11:53 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
Smash the stack and thread pointers to deadbeef, as is common
for the other architectures. This allows us to drop these
special cases within reginfo_is_eq and reginfo_dump_mismatch.
Do not copy the unused special registers that are packed into gregs[].
Most of these are related to system instructions and thus are not
manipulable via the user-mode instructions targeted by RISU. LNK and
CTR are not initialized by risugen, and since in general we cannot
test branches with risugen these can be ignored. This leaves only
XER and CCR as the only special registers to be copied.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
risu_reginfo_ppc64.c | 17 +++++------------
1 file changed, 5 insertions(+), 12 deletions(-)
diff --git a/risu_reginfo_ppc64.c b/risu_reginfo_ppc64.c
index fc69805..67ea3ce 100644
--- a/risu_reginfo_ppc64.c
+++ b/risu_reginfo_ppc64.c
@@ -44,16 +44,16 @@ int reginfo_size(struct reginfo *ri)
/* reginfo_init: initialize with a ucontext */
void reginfo_init(struct reginfo *ri, ucontext_t *uc, void *siaddr)
{
- int i;
-
memset(ri, 0, sizeof(*ri));
ri->faulting_insn = *((uint32_t *) uc->uc_mcontext.regs->nip);
ri->nip = uc->uc_mcontext.regs->nip - image_start_address;
- for (i = 0; i < NGREG; i++) {
- ri->gregs[i] = uc->uc_mcontext.gp_regs[i];
- }
+ memcpy(ri->gregs, uc->uc_mcontext.gp_regs, 32 * sizeof(ri->gregs[0]));
+ ri->gregs[1] = 0xdeadbeefdeadbeef; /* sp */
+ ri->gregs[13] = 0xdeadbeefdeadbeef; /* tp */
+ ri->gregs[XER] = uc->uc_mcontext.gp_regs[XER];
+ ri->gregs[CCR] = uc->uc_mcontext.gp_regs[CCR];
memcpy(ri->fpregs, uc->uc_mcontext.fp_regs, 32 * sizeof(double));
ri->fpscr = uc->uc_mcontext.fp_regs[32];
@@ -69,10 +69,6 @@ int reginfo_is_eq(struct reginfo *m, struct reginfo *a)
{
int i;
for (i = 0; i < 32; i++) {
- if (i == 1 || i == 13) {
- continue;
- }
-
if (m->gregs[i] != a->gregs[i]) {
return 0;
}
@@ -150,9 +146,6 @@ void reginfo_dump_mismatch(struct reginfo *m, struct reginfo *a, FILE *f)
int i;
for (i = 0; i < 32; i++) {
- if (i == 1 || i == 13) {
- continue;
- }
if (m->gregs[i] != a->gregs[i]) {
fprintf(f, "%*s%d: %016lx vs %016lx\n",
6 - (1 < 10 ? 1 : 2), "r", i,
--
2.34.1
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH 07/17] ppc64: Compare all bits of CCR
2024-05-11 11:53 [PATCH 00/17] RISU misc updates Richard Henderson
` (5 preceding siblings ...)
2024-05-11 11:53 ` [PATCH 06/17] ppc64: Clean register values in reginfo_init Richard Henderson
@ 2024-05-11 11:53 ` Richard Henderson
2024-05-15 12:54 ` Philippe Mathieu-Daudé
2024-05-11 11:53 ` [PATCH 08/17] ppc64: Simplify reginfo_is_eq Richard Henderson
` (10 subsequent siblings)
17 siblings, 1 reply; 38+ messages in thread
From: Richard Henderson @ 2024-05-11 11:53 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
There are 32 bits in this register, and they are all valid
comparision destinations.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
risu_reginfo_ppc64.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/risu_reginfo_ppc64.c b/risu_reginfo_ppc64.c
index 67ea3ce..109b87b 100644
--- a/risu_reginfo_ppc64.c
+++ b/risu_reginfo_ppc64.c
@@ -78,7 +78,7 @@ int reginfo_is_eq(struct reginfo *m, struct reginfo *a)
return 0;
}
- if ((m->gregs[CCR] & 0x10) != (a->gregs[CCR] & 0x10)) {
+ if (m->gregs[CCR] != a->gregs[CCR]) {
return 0;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH 08/17] ppc64: Simplify reginfo_is_eq
2024-05-11 11:53 [PATCH 00/17] RISU misc updates Richard Henderson
` (6 preceding siblings ...)
2024-05-11 11:53 ` [PATCH 07/17] ppc64: Compare all bits of CCR Richard Henderson
@ 2024-05-11 11:53 ` Richard Henderson
2024-05-21 12:23 ` Peter Maydell
2024-05-11 11:53 ` [PATCH 09/17] ppc64: Clean up reginfo_dump Richard Henderson
` (9 subsequent siblings)
17 siblings, 1 reply; 38+ messages in thread
From: Richard Henderson @ 2024-05-11 11:53 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
Since we now only copy into reginfo exactly what we want to compare,
and since we zero all unused padding and reserved space, we need not
enumerate each field for comparison, but defer to memcmp.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
risu_reginfo_ppc64.c | 31 +------------------------------
1 file changed, 1 insertion(+), 30 deletions(-)
diff --git a/risu_reginfo_ppc64.c b/risu_reginfo_ppc64.c
index 109b87b..e0c650b 100644
--- a/risu_reginfo_ppc64.c
+++ b/risu_reginfo_ppc64.c
@@ -67,36 +67,7 @@ void reginfo_init(struct reginfo *ri, ucontext_t *uc, void *siaddr)
/* reginfo_is_eq: compare the reginfo structs, returns nonzero if equal */
int reginfo_is_eq(struct reginfo *m, struct reginfo *a)
{
- int i;
- for (i = 0; i < 32; i++) {
- if (m->gregs[i] != a->gregs[i]) {
- return 0;
- }
- }
-
- if (m->gregs[XER] != a->gregs[XER]) {
- return 0;
- }
-
- if (m->gregs[CCR] != a->gregs[CCR]) {
- return 0;
- }
-
- for (i = 0; i < 32; i++) {
- if (m->fpregs[i] != a->fpregs[i]) {
- return 0;
- }
- }
-
- for (i = 0; i < 32; i++) {
- if (m->vrregs.vrregs[i][0] != a->vrregs.vrregs[i][0] ||
- m->vrregs.vrregs[i][1] != a->vrregs.vrregs[i][1] ||
- m->vrregs.vrregs[i][2] != a->vrregs.vrregs[i][2] ||
- m->vrregs.vrregs[i][3] != a->vrregs.vrregs[i][3]) {
- return 0;
- }
- }
- return 1;
+ return memcmp(m, a, sizeof(*m)) == 0;
}
/* reginfo_dump: print state to a stream */
--
2.34.1
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH 09/17] ppc64: Clean up reginfo_dump
2024-05-11 11:53 [PATCH 00/17] RISU misc updates Richard Henderson
` (7 preceding siblings ...)
2024-05-11 11:53 ` [PATCH 08/17] ppc64: Simplify reginfo_is_eq Richard Henderson
@ 2024-05-11 11:53 ` Richard Henderson
2024-05-21 12:25 ` Peter Maydell
2024-05-11 11:53 ` [PATCH 10/17] aarch64: Tidy reginfo dumping ahead of ZA state Richard Henderson
` (8 subsequent siblings)
17 siblings, 1 reply; 38+ messages in thread
From: Richard Henderson @ 2024-05-11 11:53 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
Dump only the registers that we copied in reginfo_init.
Improve the formatting and layout of what we do dump.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
risu_reginfo_ppc64.c | 51 ++++++++++++++++++--------------------------
1 file changed, 21 insertions(+), 30 deletions(-)
diff --git a/risu_reginfo_ppc64.c b/risu_reginfo_ppc64.c
index e0c650b..730a565 100644
--- a/risu_reginfo_ppc64.c
+++ b/risu_reginfo_ppc64.c
@@ -75,38 +75,29 @@ void reginfo_dump(struct reginfo *ri, FILE * f)
{
int i;
- fprintf(f, " faulting insn 0x%x\n", ri->faulting_insn);
- fprintf(f, " prev insn 0x%x\n", ri->prev_insn);
- fprintf(f, " prev addr 0x%" PRIx64 "\n\n", ri->nip);
-
- for (i = 0; i < 16; i++) {
- fprintf(f, "\tr%2d: %16lx\tr%2d: %16lx\n", i, ri->gregs[i],
- i + 16, ri->gregs[i + 16]);
- }
-
- fprintf(f, "\n");
- fprintf(f, "\tnip : %16lx\n", ri->gregs[32]);
- fprintf(f, "\tmsr : %16lx\n", ri->gregs[33]);
- fprintf(f, "\torig r3: %16lx\n", ri->gregs[34]);
- fprintf(f, "\tctr : %16lx\n", ri->gregs[35]);
- fprintf(f, "\tlnk : %16lx\n", ri->gregs[36]);
- fprintf(f, "\txer : %16lx\n", ri->gregs[37]);
- fprintf(f, "\tccr : %16lx\n", ri->gregs[38]);
- fprintf(f, "\tmq : %16lx\n", ri->gregs[39]);
- fprintf(f, "\ttrap : %16lx\n", ri->gregs[40]);
- fprintf(f, "\tdar : %16lx\n", ri->gregs[41]);
- fprintf(f, "\tdsisr : %16lx\n", ri->gregs[42]);
- fprintf(f, "\tresult : %16lx\n", ri->gregs[43]);
- fprintf(f, "\tdscr : %16lx\n\n", ri->gregs[44]);
-
- for (i = 0; i < 16; i++) {
- fprintf(f, "\tf%2d: %016lx\tf%2d: %016lx\n", i, ri->fpregs[i],
- i + 16, ri->fpregs[i + 16]);
- }
- fprintf(f, "\tfpscr: %016lx\n\n", ri->fpscr);
+ fprintf(f, "%6s: %08x\n", "insn", ri->faulting_insn);
+ fprintf(f, "%6s: %016lx\n", "pc", ri->nip);
for (i = 0; i < 32; i++) {
- fprintf(f, "vr%02d: %8x, %8x, %8x, %8x\n", i,
+ fprintf(f, "%*s%d: %016lx%s",
+ 6 - (i < 10 ? 1 : 2), "r", i, ri->gregs[i],
+ i & 1 ? "\n" : " ");
+ }
+
+ fprintf(f, "%6s: %016lx %6s: %016lx\n",
+ "xer", ri->gregs[XER],
+ "ccr", ri->gregs[CCR]);
+
+ for (i = 0; i < 32; i++) {
+ fprintf(f, "%*s%d: %016lx%s",
+ 6 - (i < 10 ? 1 : 2), "f", i, ri->fpregs[i],
+ i & 1 ? "\n" : " ");
+ }
+ fprintf(f, "%6s: %016lx\n", "fpscr", ri->fpscr);
+
+ for (i = 0; i < 32; i++) {
+ fprintf(f, "%*s%d: %08x %08x %08x %08x\n",
+ 6 - (i < 10 ? 1 : 2), "vr", i,
ri->vrregs.vrregs[i][0], ri->vrregs.vrregs[i][1],
ri->vrregs.vrregs[i][2], ri->vrregs.vrregs[i][3]);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH 10/17] aarch64: Tidy reginfo dumping ahead of ZA state
2024-05-11 11:53 [PATCH 00/17] RISU misc updates Richard Henderson
` (8 preceding siblings ...)
2024-05-11 11:53 ` [PATCH 09/17] ppc64: Clean up reginfo_dump Richard Henderson
@ 2024-05-11 11:53 ` Richard Henderson
2024-05-15 12:55 ` Philippe Mathieu-Daudé
2024-05-11 11:53 ` [PATCH 11/17] aarch64: Add support for ZA storage Richard Henderson
` (7 subsequent siblings)
17 siblings, 1 reply; 38+ messages in thread
From: Richard Henderson @ 2024-05-11 11:53 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
A misalignment for sve_vl, plus add a bit more space
on the left for the ZA[n] field name.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
risu_reginfo_aarch64.c | 29 ++++++++++++++++++-----------
1 file changed, 18 insertions(+), 11 deletions(-)
diff --git a/risu_reginfo_aarch64.c b/risu_reginfo_aarch64.c
index 0161044..86e70ab 100644
--- a/risu_reginfo_aarch64.c
+++ b/risu_reginfo_aarch64.c
@@ -183,6 +183,18 @@ static int sve_preg_is_eq(int vq, const void *p1, const void *p2)
return memcmp(p1, p2, vq * 2) == 0;
}
+static void sve_dump_zreg(FILE *f, int vq, const uint64_t *z)
+{
+ const char *pad = "";
+ int q;
+
+ for (q = 0; q < vq; q++) {
+ fprintf(f, "%s[%-2d] %016" PRIx64 "%016" PRIx64 "\n",
+ pad, q, z[2 * q + 1], z[2 * q]);
+ pad = " "; /* 11 spaces */
+ }
+}
+
static void sve_dump_preg(FILE *f, int vq, const uint16_t *p)
{
int q;
@@ -211,10 +223,10 @@ static void sve_dump_zreg_diff(FILE *f, int vq, const uint64_t *za,
uint64_t zb0 = zb[2 * q], zb1 = zb[2 * q + 1];
if (za0 != zb0 || za1 != zb1) {
- fprintf(f, "%sq%-2d: %016" PRIx64 "%016" PRIx64
+ fprintf(f, "%s[%-2d]: %016" PRIx64 "%016" PRIx64
" vs %016" PRIx64 "%016" PRIx64"\n",
pad, q, za1, za0, zb1, zb0);
- pad = " ";
+ pad = " "; /* 11 spaces */
}
}
}
@@ -237,19 +249,14 @@ void reginfo_dump(struct reginfo *ri, FILE * f)
if (ri->sve_vl) {
int vq = sve_vq_from_vl(ri->sve_vl);
- int q;
fprintf(f, " vl : %d\n", ri->sve_vl);
for (i = 0; i < SVE_NUM_ZREGS; i++) {
uint64_t *z = reginfo_zreg(ri, vq, i);
- fprintf(f, " Z%-2d q%-2d: %016" PRIx64 "%016" PRIx64 "\n",
- i, 0, z[1], z[0]);
- for (q = 1; q < vq; ++q) {
- fprintf(f, " q%-2d: %016" PRIx64 "%016" PRIx64 "\n",
- q, z[q * 2 + 1], z[q * 2]);
- }
+ fprintf(f, " Z%-2d : ", i);
+ sve_dump_zreg(f, vq, z);
}
for (i = 0; i < SVE_NUM_PREGS + 1; i++) {
@@ -312,7 +319,7 @@ void reginfo_dump_mismatch(struct reginfo *m, struct reginfo *a, FILE * f)
}
if (m->sve_vl != a->sve_vl) {
- fprintf(f, " vl : %d vs %d\n", m->sve_vl, a->sve_vl);
+ fprintf(f, " vl : %d vs %d\n", m->sve_vl, a->sve_vl);
}
if (m->sve_vl) {
@@ -323,7 +330,7 @@ void reginfo_dump_mismatch(struct reginfo *m, struct reginfo *a, FILE * f)
uint64_t *za = reginfo_zreg(a, vq, i);
if (!sve_zreg_is_eq(vq, zm, za)) {
- fprintf(f, " Z%-2d ", i);
+ fprintf(f, " Z%-2d : ", i);
sve_dump_zreg_diff(f, vq, zm, za);
}
}
--
2.34.1
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH 11/17] aarch64: Add support for ZA storage
2024-05-11 11:53 [PATCH 00/17] RISU misc updates Richard Henderson
` (9 preceding siblings ...)
2024-05-11 11:53 ` [PATCH 10/17] aarch64: Tidy reginfo dumping ahead of ZA state Richard Henderson
@ 2024-05-11 11:53 ` Richard Henderson
2024-05-11 11:53 ` [PATCH 12/17] aarch64: Trivial SME test Richard Henderson
` (6 subsequent siblings)
17 siblings, 0 replies; 38+ messages in thread
From: Richard Henderson @ 2024-05-11 11:53 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
Require NVL == SVL on startup, to make it easier to manage reginfo.
Most of the time PSTATE.SM would be active with PSTATE.ZA anyway,
for any non-trivial SME testing.
Extend saved storage only when PSTATE.ZA is active.
Use a carefully reserved uint16_t for saving SVCR.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
risu_reginfo_aarch64.h | 52 ++++++++++++-
risu_reginfo_aarch64.c | 161 ++++++++++++++++++++++++++++++++++++-----
2 files changed, 191 insertions(+), 22 deletions(-)
diff --git a/risu_reginfo_aarch64.h b/risu_reginfo_aarch64.h
index 536c12b..097b7ad 100644
--- a/risu_reginfo_aarch64.h
+++ b/risu_reginfo_aarch64.h
@@ -21,6 +21,43 @@
#define SVE_VQ_MAX 16
#define ROUND_UP(SIZE, POW2) (((SIZE) + (POW2) - 1) & -(POW2))
+
+#ifdef ZA_MAGIC
+/* System headers have all Streaming SVE definitions. */
+typedef struct sve_context risu_sve_context;
+typedef struct za_context risu_za_context;
+#else
+#define ZA_MAGIC 0x54366345
+#define SVE_SIG_FLAG_SM 1
+
+/* System headers missing flags field. */
+typedef struct {
+ struct _aarch64_ctx head;
+ uint16_t vl;
+ uint16_t flags;
+ uint16_t reserved[2];
+} risu_sve_context;
+
+typedef struct {
+ struct _aarch64_ctx head;
+ uint16_t vl;
+ uint16_t reserved[3];
+} risu_za_context;
+
+#define ZA_SIG_REGS_OFFSET \
+ ROUND_UP(sizeof(risu_za_context), SVE_VQ_BYTES)
+
+#define ZA_SIG_REGS_SIZE(vq) \
+ ((vq) * (vq) * SVE_VQ_BYTES * SVE_VQ_BYTES)
+
+#define ZA_SIG_ZAV_OFFSET(vq, n) \
+ (ZA_SIG_REGS_OFFSET + (SVE_SIG_ZREG_SIZE(vq) * n))
+
+#define ZA_SIG_CONTEXT_SIZE(vq) \
+ (ZA_SIG_REGS_OFFSET + ZA_SIG_REGS_SIZE(vq))
+
+#endif /* ZA_MAGIC */
+
#define RISU_SVE_REGS_SIZE(VQ) ROUND_UP(SVE_SIG_REGS_SIZE(VQ), 16)
#define RISU_SIMD_REGS_SIZE (32 * 16)
@@ -36,12 +73,16 @@ struct reginfo {
uint32_t fpsr;
uint32_t fpcr;
uint16_t sve_vl;
- uint16_t reserved;
+ uint16_t svcr;
- char extra[RISU_SVE_REGS_SIZE(SVE_VQ_MAX)]
+ char extra[RISU_SVE_REGS_SIZE(SVE_VQ_MAX) +
+ ZA_SIG_REGS_SIZE(SVE_VQ_MAX)]
__attribute__((aligned(16)));
};
+#define SVCR_SM 1
+#define SVCR_ZA 2
+
static inline uint64_t *reginfo_vreg(struct reginfo *ri, int i)
{
return (uint64_t *)&ri->extra[i * 16];
@@ -59,4 +100,11 @@ static inline uint16_t *reginfo_preg(struct reginfo *ri, int vq, int i)
SVE_SIG_REGS_OFFSET];
}
+static inline uint64_t *reginfo_zav(struct reginfo *ri, int vq, int i)
+{
+ return (uint64_t *)&ri->extra[RISU_SVE_REGS_SIZE(vq) +
+ ZA_SIG_ZAV_OFFSET(vq, i) -
+ ZA_SIG_REGS_OFFSET];
+}
+
#endif /* RISU_REGINFO_AARCH64_H */
diff --git a/risu_reginfo_aarch64.c b/risu_reginfo_aarch64.c
index 86e70ab..67a2999 100644
--- a/risu_reginfo_aarch64.c
+++ b/risu_reginfo_aarch64.c
@@ -25,25 +25,44 @@
#include "risu.h"
#include "risu_reginfo_aarch64.h"
+#ifndef PR_SME_SET_VL
+#define PR_SME_SET_VL 63
+#endif
+
/* Should we test SVE register state */
static int test_sve;
+static int test_za;
static const struct option extra_opts[] = {
{"test-sve", required_argument, NULL, FIRST_ARCH_OPT },
+ {"test-za", required_argument, NULL, FIRST_ARCH_OPT + 1 },
{0, 0, 0, 0}
};
const struct option * const arch_long_opts = &extra_opts[0];
const char * const arch_extra_help
- = " --test-sve=<vq> Compare SVE registers with VQ\n";
+ = " --test-sve=<vq> Compare SVE registers with VQ\n"
+ " --test-za=<vq> Compare ZA storage with VQ\n";
void process_arch_opt(int opt, const char *arg)
{
- assert(opt == FIRST_ARCH_OPT);
- test_sve = strtol(arg, 0, 10);
-
- if (test_sve <= 0 || test_sve > SVE_VQ_MAX) {
- fprintf(stderr, "Invalid value for VQ (1-%d)\n", SVE_VQ_MAX);
- exit(EXIT_FAILURE);
+ switch (opt) {
+ case FIRST_ARCH_OPT:
+ test_sve = strtol(arg, 0, 10);
+ if (test_sve <= 0 || test_sve > SVE_VQ_MAX) {
+ fprintf(stderr, "Invalid value for SVE VQ (1-%d)\n", SVE_VQ_MAX);
+ exit(EXIT_FAILURE);
+ }
+ break;
+ case FIRST_ARCH_OPT + 1:
+ test_za = strtol(arg, 0, 10);
+ if (test_za <= 0 || test_za > SVE_VQ_MAX
+ || (test_za & (test_za - 1))) {
+ fprintf(stderr, "Invalid value for ZA VQ (1-%d)\n", SVE_VQ_MAX);
+ exit(EXIT_FAILURE);
+ }
+ break;
+ default:
+ abort();
}
}
@@ -51,6 +70,31 @@ void arch_init(void)
{
long want, got;
+ if (test_za) {
+ /*
+ * For now, reginfo requires NVL == SVL.
+ * There doesn't seem to be much advantage to differing.
+ */
+ if (test_sve && test_sve != test_za) {
+ fprintf(stderr, "Mismatched values for SVE and ZA VQ\n");
+ exit(EXIT_FAILURE);
+ }
+
+ want = sve_vl_from_vq(test_za);
+ got = prctl(PR_SME_SET_VL, want);
+ if (want != got) {
+ if (got >= 0) {
+ fprintf(stderr, "Unsupported VQ for ZA (%d != %d)\n",
+ test_za, (int)sve_vq_from_vl(got));
+ } else if (errno == EINVAL) {
+ fprintf(stderr, "System does not support SME\n");
+ } else {
+ perror("prctl PR_SME_SET_VL");
+ }
+ exit(EXIT_FAILURE);
+ }
+ }
+
if (test_sve) {
want = sve_vl_from_vq(test_sve);
got = prctl(PR_SVE_SET_VL, want);
@@ -75,6 +119,9 @@ int reginfo_size(struct reginfo *ri)
if (ri->sve_vl) {
int vq = sve_vq_from_vl(ri->sve_vl);
size += RISU_SVE_REGS_SIZE(vq);
+ if (ri->svcr & SVCR_ZA) {
+ size += ZA_SIG_REGS_SIZE(vq);
+ }
} else {
size += RISU_SIMD_REGS_SIZE;
}
@@ -84,10 +131,11 @@ int reginfo_size(struct reginfo *ri)
/* reginfo_init: initialize with a ucontext */
void reginfo_init(struct reginfo *ri, ucontext_t *uc, void *siaddr)
{
- int i;
+ int i, vq;
struct _aarch64_ctx *ctx, *extra = NULL;
struct fpsimd_context *fp = NULL;
- struct sve_context *sve = NULL;
+ risu_sve_context *sve = NULL;
+ risu_za_context *za = NULL;
/* necessary to be able to compare with memcmp later */
memset(ri, 0, sizeof(*ri));
@@ -112,6 +160,9 @@ void reginfo_init(struct reginfo *ri, ucontext_t *uc, void *siaddr)
case SVE_MAGIC:
sve = (void *)ctx;
break;
+ case ZA_MAGIC:
+ za = (void *)ctx;
+ break;
case EXTRA_MAGIC:
extra = (void *)((struct extra_context *)(ctx))->datap;
break;
@@ -134,21 +185,55 @@ void reginfo_init(struct reginfo *ri, ucontext_t *uc, void *siaddr)
ri->fpsr = fp->fpsr;
ri->fpcr = fp->fpcr;
- if (test_sve) {
- int vq = test_sve;
+ /*
+ * Note that arch_init required NVL==SVL, so test_sve and test_za
+ * are equal when non-zero. We will verify this matches below.
+ */
+ vq = test_sve | test_za;
+ ri->sve_vl = sve_vl_from_vq(vq);
- if (sve == NULL) {
- fprintf(stderr, "risu_reginfo_aarch64: failed to get SVE state\n");
+ if (test_za) {
+ if (za == NULL) {
+ /* ZA_MAGIC is supposed to be present, even if empty. */
+ fprintf(stderr, "risu_reginfo_aarch64: missing ZA state\n");
return;
}
+ assert(za->head.size >= ZA_SIG_CONTEXT_SIZE(0));
- if (sve->vl != sve_vl_from_vq(vq)) {
+ if (za->vl != ri->sve_vl) {
fprintf(stderr, "risu_reginfo_aarch64: "
- "unexpected SVE state: %d != %d\n",
- sve->vl, sve_vl_from_vq(vq));
+ "unexpected ZA VQ: %d != %d\n",
+ za->vl, ri->sve_vl);
+ return;
+ }
+ if (za->head.size == ZA_SIG_CONTEXT_SIZE(0)) {
+ /* ZA storage is disabled. */
+ } else if (za->head.size < ZA_SIG_CONTEXT_SIZE(vq)) {
+ fprintf(stderr, "risu_reginfo_aarch64: "
+ "failed to get complete ZA state\n");
+ return;
+ } else {
+ ri->svcr |= SVCR_ZA;
+ memcpy(reginfo_zav(ri, vq, 0), (char *)za + ZA_SIG_REGS_OFFSET,
+ ZA_SIG_CONTEXT_SIZE(vq) - ZA_SIG_REGS_OFFSET);
+ }
+ }
+
+ if (test_sve) {
+ if (sve == NULL) {
+ /* SVE_MAGIC is supposed to be present, even if empty. */
+ fprintf(stderr, "risu_reginfo_aarch64: missing SVE state\n");
return;
}
+ if (sve->vl != ri->sve_vl) {
+ fprintf(stderr, "risu_reginfo_aarch64: "
+ "unexpected SVE VQ: %d != %d\n",
+ sve->vl, ri->sve_vl);
+ return;
+ }
+
+ ri->svcr |= sve->flags & SVE_SIG_FLAG_SM;
if (sve->head.size <= SVE_SIG_CONTEXT_SIZE(0)) {
/* Only AdvSIMD state is present. */
} else if (sve->head.size < SVE_SIG_CONTEXT_SIZE(vq)) {
@@ -156,7 +241,6 @@ void reginfo_init(struct reginfo *ri, ucontext_t *uc, void *siaddr)
"failed to get complete SVE state\n");
return;
} else {
- ri->sve_vl = sve->vl;
memcpy(reginfo_zreg(ri, vq, 0),
(char *)sve + SVE_SIG_REGS_OFFSET,
SVE_SIG_REGS_SIZE(vq));
@@ -164,7 +248,18 @@ void reginfo_init(struct reginfo *ri, ucontext_t *uc, void *siaddr)
}
}
- memcpy(reginfo_vreg(ri, 0), fp->vregs, RISU_SIMD_REGS_SIZE);
+ /*
+ * Be prepared for ZA state present but SVE state absent (VQ != 0).
+ * In which case, copy AdvSIMD vregs into the low portion of zregs;
+ * pregs remain all zero.
+ */
+ if (vq == 0) {
+ memcpy(reginfo_vreg(ri, 0), fp->vregs, RISU_SIMD_REGS_SIZE);
+ } else {
+ for (i = 0; i < 32; ++i) {
+ memcpy(reginfo_zreg(ri, vq, i), &fp->vregs[i], 16);
+ }
+ }
}
/* reginfo_is_eq: compare the reginfo structs, returns nonzero if equal */
@@ -248,9 +343,11 @@ void reginfo_dump(struct reginfo *ri, FILE * f)
fprintf(f, " fpcr : %08x\n", ri->fpcr);
if (ri->sve_vl) {
- int vq = sve_vq_from_vl(ri->sve_vl);
+ int vl = ri->sve_vl;
+ int vq = sve_vq_from_vl(vl);
- fprintf(f, " vl : %d\n", ri->sve_vl);
+ fprintf(f, " vl : %d\n", vl);
+ fprintf(f, " svcr : %d\n", ri->svcr);
for (i = 0; i < SVE_NUM_ZREGS; i++) {
uint64_t *z = reginfo_zreg(ri, vq, i);
@@ -270,6 +367,14 @@ void reginfo_dump(struct reginfo *ri, FILE * f)
sve_dump_preg(f, vq, p);
fprintf(f, "\n");
}
+
+ if (ri->svcr & SVCR_ZA) {
+ for (i = 0; i < vl; ++i) {
+ uint64_t *z = reginfo_zav(ri, vq, i);
+ fprintf(f, " ZA[%-3d]: ", i);
+ sve_dump_zreg(f, vq, z);
+ }
+ }
return;
}
@@ -322,6 +427,10 @@ void reginfo_dump_mismatch(struct reginfo *m, struct reginfo *a, FILE * f)
fprintf(f, " vl : %d vs %d\n", m->sve_vl, a->sve_vl);
}
+ if (m->svcr != a->svcr) {
+ fprintf(f, " svcr : %d vs %d\n", m->svcr, a->svcr);
+ }
+
if (m->sve_vl) {
int vq = sve_vq_from_vl(m->sve_vl);
@@ -347,6 +456,18 @@ void reginfo_dump_mismatch(struct reginfo *m, struct reginfo *a, FILE * f)
sve_dump_preg_diff(f, vq, pm, pa);
}
}
+
+ if (m->svcr & a->svcr & SVCR_ZA) {
+ for (i = 0; i < vq * 16; i++) {
+ uint64_t *zm = reginfo_zav(m, vq, i);
+ uint64_t *za = reginfo_zav(a, vq, i);
+
+ if (!sve_zreg_is_eq(vq, zm, za)) {
+ fprintf(f, " ZA[%-3d]: ", i);
+ sve_dump_zreg_diff(f, vq, zm, za);
+ }
+ }
+ }
return;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH 12/17] aarch64: Trivial SME test
2024-05-11 11:53 [PATCH 00/17] RISU misc updates Richard Henderson
` (10 preceding siblings ...)
2024-05-11 11:53 ` [PATCH 11/17] aarch64: Add support for ZA storage Richard Henderson
@ 2024-05-11 11:53 ` Richard Henderson
2024-05-21 12:27 ` Peter Maydell
2024-05-11 11:53 ` [PATCH 13/17] Use bool for reginfo_is_eq Richard Henderson
` (5 subsequent siblings)
17 siblings, 1 reply; 38+ messages in thread
From: Richard Henderson @ 2024-05-11 11:53 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
test_sme_aarch64.s | 63 ++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 63 insertions(+)
create mode 100644 test_sme_aarch64.s
diff --git a/test_sme_aarch64.s b/test_sme_aarch64.s
new file mode 100644
index 0000000..acd08d4
--- /dev/null
+++ b/test_sme_aarch64.s
@@ -0,0 +1,63 @@
+/*****************************************************************************
+ * Copyright (c) 2022 Linaro Limited
+ * All rights reserved. This program and the accompanying materials
+ * are made available under the terms of the Eclipse Public License v1.0
+ * which accompanies this distribution, and is available at
+ * http://www.eclipse.org/legal/epl-v10.html
+ *****************************************************************************/
+
+ .arch_extension sme
+
+ mov w0, #0
+ mov w1, #0
+ mov w2, #0
+ mov w3, #0
+ mov w4, #0
+ mov w5, #0
+ mov w6, #0
+ mov w7, #0
+ mov w8, #0
+ mov w9, #0
+ mov w10, #0
+ mov w11, #0
+ mov w12, #0
+ mov w13, #0
+ mov w14, #0
+ mov w15, #0
+ mov w16, #0
+ mov w17, #0
+ mov w18, #0
+ mov w19, #0
+ mov w20, #0
+ mov w21, #0
+ mov w22, #0
+ mov w23, #0
+ mov w24, #0
+ mov w25, #0
+ mov w26, #0
+ mov w27, #0
+ mov w28, #0
+ mov w29, #0
+ mov w30, #0
+
+ smstart
+
+ ptrue p0.b
+ rdsvl x12, #1
+
+0: subs w12, w12, #1
+ lsl w13, w12, #4
+ index z0.b, w13, #1
+ mova za0h.b[w12, #0], p0/m, z0.b
+ b.ne 0b
+
+ .inst 0x00005af0 /* compare */
+
+ rdsvl x12, #1
+0: subs w12, w12, #1
+ lsl w13, w12, #4
+ index z0.b, w13, #1
+ mova za0v.b[w12, #0], p0/m, z0.b
+ b.ne 0b
+
+ .inst 0x00005af1 /* exit */
--
2.34.1
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH 13/17] Use bool for reginfo_is_eq
2024-05-11 11:53 [PATCH 00/17] RISU misc updates Richard Henderson
` (11 preceding siblings ...)
2024-05-11 11:53 ` [PATCH 12/17] aarch64: Trivial SME test Richard Henderson
@ 2024-05-11 11:53 ` Richard Henderson
2024-05-15 12:56 ` Philippe Mathieu-Daudé
2024-05-11 11:53 ` [PATCH 14/17] aarch64: Use bool for sve_{z,p}reg_is_eq Richard Henderson
` (4 subsequent siblings)
17 siblings, 1 reply; 38+ messages in thread
From: Richard Henderson @ 2024-05-11 11:53 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
The function result is more naturally boolean.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
risu.h | 4 ++--
risu_reginfo_aarch64.c | 4 ++--
risu_reginfo_arm.c | 4 ++--
risu_reginfo_i386.c | 4 ++--
risu_reginfo_loongarch64.c | 4 ++--
risu_reginfo_m68k.c | 16 ++++++++--------
risu_reginfo_ppc64.c | 4 ++--
risu_reginfo_s390x.c | 4 ++--
8 files changed, 22 insertions(+), 22 deletions(-)
diff --git a/risu.h b/risu.h
index aa8cc22..4203178 100644
--- a/risu.h
+++ b/risu.h
@@ -117,8 +117,8 @@ uintptr_t get_pc(struct reginfo *ri);
/* initialize structure from a ucontext */
void reginfo_init(struct reginfo *ri, ucontext_t *uc, void *siaddr);
-/* return 1 if structs are equal, 0 otherwise. */
-int reginfo_is_eq(struct reginfo *r1, struct reginfo *r2);
+/* return true if structs are equal, false otherwise. */
+bool reginfo_is_eq(struct reginfo *r1, struct reginfo *r2);
/* print reginfo state to a stream */
void reginfo_dump(struct reginfo *ri, FILE *f);
diff --git a/risu_reginfo_aarch64.c b/risu_reginfo_aarch64.c
index 67a2999..55a9ef6 100644
--- a/risu_reginfo_aarch64.c
+++ b/risu_reginfo_aarch64.c
@@ -262,8 +262,8 @@ void reginfo_init(struct reginfo *ri, ucontext_t *uc, void *siaddr)
}
}
-/* reginfo_is_eq: compare the reginfo structs, returns nonzero if equal */
-int reginfo_is_eq(struct reginfo *r1, struct reginfo *r2)
+/* reginfo_is_eq: compare the reginfo structs, returns true if equal */
+bool reginfo_is_eq(struct reginfo *r1, struct reginfo *r2)
{
return memcmp(r1, r2, reginfo_size(r1)) == 0;
}
diff --git a/risu_reginfo_arm.c b/risu_reginfo_arm.c
index 0e179be..d11e666 100644
--- a/risu_reginfo_arm.c
+++ b/risu_reginfo_arm.c
@@ -155,8 +155,8 @@ void reginfo_init(struct reginfo *ri, ucontext_t *uc, void *siaddr)
reginfo_init_vfp(ri, uc);
}
-/* reginfo_is_eq: compare the reginfo structs, returns nonzero if equal */
-int reginfo_is_eq(struct reginfo *r1, struct reginfo *r2)
+/* reginfo_is_eq: compare the reginfo structs, returns true if equal */
+bool reginfo_is_eq(struct reginfo *r1, struct reginfo *r2)
{
return memcmp(r1, r2, sizeof(*r1)) == 0; /* ok since we memset 0 */
}
diff --git a/risu_reginfo_i386.c b/risu_reginfo_i386.c
index f4cf9a3..1c579fa 100644
--- a/risu_reginfo_i386.c
+++ b/risu_reginfo_i386.c
@@ -234,8 +234,8 @@ void reginfo_init(struct reginfo *ri, ucontext_t *uc, void *siaddr)
#endif
}
-/* reginfo_is_eq: compare the reginfo structs, returns nonzero if equal */
-int reginfo_is_eq(struct reginfo *m, struct reginfo *a)
+/* reginfo_is_eq: compare the reginfo structs, returns true if equal */
+bool reginfo_is_eq(struct reginfo *m, struct reginfo *a)
{
return !memcmp(m, a, sizeof(*m));
}
diff --git a/risu_reginfo_loongarch64.c b/risu_reginfo_loongarch64.c
index 060715f..6150a40 100644
--- a/risu_reginfo_loongarch64.c
+++ b/risu_reginfo_loongarch64.c
@@ -153,8 +153,8 @@ void reginfo_init(struct reginfo *ri, ucontext_t *context, void *siaddr)
}
}
-/* reginfo_is_eq: compare the reginfo structs, returns nonzero if equal */
-int reginfo_is_eq(struct reginfo *r1, struct reginfo *r2)
+/* reginfo_is_eq: compare the reginfo structs */
+bool reginfo_is_eq(struct reginfo *r1, struct reginfo *r2)
{
return !memcmp(r1, r2, sizeof(*r1));
}
diff --git a/risu_reginfo_m68k.c b/risu_reginfo_m68k.c
index a53244d..7335195 100644
--- a/risu_reginfo_m68k.c
+++ b/risu_reginfo_m68k.c
@@ -55,13 +55,13 @@ void reginfo_init(struct reginfo *ri, ucontext_t *uc, void *siaddr)
}
}
-/* reginfo_is_eq: compare the reginfo structs, returns nonzero if equal */
-int reginfo_is_eq(struct reginfo *m, struct reginfo *a)
+/* reginfo_is_eq: compare the reginfo structs, returns true if equal */
+bool reginfo_is_eq(struct reginfo *m, struct reginfo *a)
{
int i;
if (m->gregs[R_PS] != a->gregs[R_PS]) {
- return 0;
+ return false;
}
for (i = 0; i < 16; i++) {
@@ -69,27 +69,27 @@ int reginfo_is_eq(struct reginfo *m, struct reginfo *a)
continue;
}
if (m->gregs[i] != a->gregs[i]) {
- return 0;
+ return false;
}
}
if (m->fpregs.f_pcr != a->fpregs.f_pcr) {
- return 0;
+ return false;
}
if (m->fpregs.f_psr != a->fpregs.f_psr) {
- return 0;
+ return false;
}
for (i = 0; i < 8; i++) {
if (m->fpregs.f_fpregs[i][0] != a->fpregs.f_fpregs[i][0] ||
m->fpregs.f_fpregs[i][1] != a->fpregs.f_fpregs[i][1] ||
m->fpregs.f_fpregs[i][2] != a->fpregs.f_fpregs[i][2]) {
- return 0;
+ return false;
}
}
- return 1;
+ return true;
}
/* reginfo_dump: print state to a stream */
diff --git a/risu_reginfo_ppc64.c b/risu_reginfo_ppc64.c
index 730a565..a8e5935 100644
--- a/risu_reginfo_ppc64.c
+++ b/risu_reginfo_ppc64.c
@@ -64,8 +64,8 @@ void reginfo_init(struct reginfo *ri, ucontext_t *uc, void *siaddr)
ri->vrregs.vrsave = uc->uc_mcontext.v_regs->vrsave;
}
-/* reginfo_is_eq: compare the reginfo structs, returns nonzero if equal */
-int reginfo_is_eq(struct reginfo *m, struct reginfo *a)
+/* reginfo_is_eq: compare the reginfo structs, returns true if equal */
+bool reginfo_is_eq(struct reginfo *m, struct reginfo *a)
{
return memcmp(m, a, sizeof(*m)) == 0;
}
diff --git a/risu_reginfo_s390x.c b/risu_reginfo_s390x.c
index cbf168e..d18b94f 100644
--- a/risu_reginfo_s390x.c
+++ b/risu_reginfo_s390x.c
@@ -73,8 +73,8 @@ void reginfo_init(struct reginfo *ri, ucontext_t *uc, void *siaddr)
memcpy(ri->fprs, &uc->uc_mcontext.fpregs.fprs, sizeof(ri->fprs));
}
-/* reginfo_is_eq: compare the reginfo structs, returns nonzero if equal */
-int reginfo_is_eq(struct reginfo *m, struct reginfo *a)
+/* reginfo_is_eq: compare the reginfo structs */
+bool reginfo_is_eq(struct reginfo *m, struct reginfo *a)
{
return m->pc_offset == a->pc_offset &&
m->fpc == a->fpc &&
--
2.34.1
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH 14/17] aarch64: Use bool for sve_{z,p}reg_is_eq
2024-05-11 11:53 [PATCH 00/17] RISU misc updates Richard Henderson
` (12 preceding siblings ...)
2024-05-11 11:53 ` [PATCH 13/17] Use bool for reginfo_is_eq Richard Henderson
@ 2024-05-11 11:53 ` Richard Henderson
2024-05-15 12:56 ` Philippe Mathieu-Daudé
2024-05-11 11:53 ` [PATCH 15/17] risu: Allow use of ELF test files Richard Henderson
` (3 subsequent siblings)
17 siblings, 1 reply; 38+ messages in thread
From: Richard Henderson @ 2024-05-11 11:53 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
The functions results are more naturally boolean.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
risu_reginfo_aarch64.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/risu_reginfo_aarch64.c b/risu_reginfo_aarch64.c
index 55a9ef6..6323eef 100644
--- a/risu_reginfo_aarch64.c
+++ b/risu_reginfo_aarch64.c
@@ -268,12 +268,12 @@ bool reginfo_is_eq(struct reginfo *r1, struct reginfo *r2)
return memcmp(r1, r2, reginfo_size(r1)) == 0;
}
-static int sve_zreg_is_eq(int vq, const void *z1, const void *z2)
+static bool sve_zreg_is_eq(int vq, const void *z1, const void *z2)
{
return memcmp(z1, z2, vq * 16) == 0;
}
-static int sve_preg_is_eq(int vq, const void *p1, const void *p2)
+static bool sve_preg_is_eq(int vq, const void *p1, const void *p2)
{
return memcmp(p1, p2, vq * 2) == 0;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH 15/17] risu: Allow use of ELF test files
2024-05-11 11:53 [PATCH 00/17] RISU misc updates Richard Henderson
` (13 preceding siblings ...)
2024-05-11 11:53 ` [PATCH 14/17] aarch64: Use bool for sve_{z,p}reg_is_eq Richard Henderson
@ 2024-05-11 11:53 ` Richard Henderson
2024-05-15 13:03 ` Philippe Mathieu-Daudé
2024-05-11 11:53 ` [PATCH 16/17] configure: Enable loongarch64 Richard Henderson
` (2 subsequent siblings)
17 siblings, 1 reply; 38+ messages in thread
From: Richard Henderson @ 2024-05-11 11:53 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
By using elf files, we make it easier to disassemble
the test file, to match comparison failures to code.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
risu.c | 53 +++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 53 insertions(+)
diff --git a/risu.c b/risu.c
index c28b4a5..e3845f6 100644
--- a/risu.c
+++ b/risu.c
@@ -24,6 +24,8 @@
#include <sys/mman.h>
#include <fcntl.h>
#include <string.h>
+#include <elf.h>
+#include <endian.h>
#include "config.h"
#include "risu.h"
@@ -371,6 +373,57 @@ static void load_image(const char *imgfile)
close(fd);
image_start = addr;
image_start_address = (uintptr_t) addr;
+
+ /*
+ * TODO: More complete parsing of ELF file, verify assumtion, namely:
+ * Single PT_LOAD covering the ELF header, code and data.
+ * For now, simply update image_start from the elf header.
+ */
+ if (memcmp(addr, ELFMAG, SELFMAG) == 0) {
+ const unsigned char *e_ident = addr;
+ bool swap, is_64;
+
+ switch (e_ident[EI_DATA]) {
+ case ELFDATA2LSB:
+ swap = __BYTE_ORDER != __LITTLE_ENDIAN;
+ break;
+ case ELFDATA2MSB:
+ swap = __BYTE_ORDER == __LITTLE_ENDIAN;
+ break;
+ default:
+ fprintf(stderr, "%s: Bad elf header: EI_DATA = %x\n",
+ imgfile, e_ident[EI_DATA]);
+ exit(1);
+ }
+ switch (e_ident[EI_CLASS]) {
+ case ELFCLASS32:
+ is_64 = false;
+ break;
+ case ELFCLASS64:
+ is_64 = true;
+ break;
+ default:
+ fprintf(stderr, "%s: Bad elf header: EI_CLASS = %x\n",
+ imgfile, e_ident[EI_CLASS]);
+ exit(1);
+ }
+
+ if (is_64) {
+ const Elf64_Ehdr *h64 = addr;
+ Elf64_Addr e64 = h64->e_entry;
+ if (swap) {
+ e64 = __builtin_bswap64(e64);
+ }
+ image_start = addr + e64;
+ } else {
+ const Elf32_Ehdr *h32 = addr;
+ Elf32_Addr e32 = h32->e_entry;
+ if (swap) {
+ e32 = __builtin_bswap32(e32);
+ }
+ image_start = addr + e32;
+ }
+ }
}
static int master(void)
--
2.34.1
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH 16/17] configure: Enable loongarch64
2024-05-11 11:53 [PATCH 00/17] RISU misc updates Richard Henderson
` (14 preceding siblings ...)
2024-05-11 11:53 ` [PATCH 15/17] risu: Allow use of ELF test files Richard Henderson
@ 2024-05-11 11:53 ` Richard Henderson
2024-05-15 13:06 ` Philippe Mathieu-Daudé
2024-05-15 13:08 ` Philippe Mathieu-Daudé
2024-05-11 11:54 ` [PATCH 17/17] Build elf test cases instead of raw binaries Richard Henderson
2024-05-21 12:46 ` [PATCH 00/17] RISU misc updates Peter Maydell
17 siblings, 2 replies; 38+ messages in thread
From: Richard Henderson @ 2024-05-11 11:53 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
configure | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/configure b/configure
index 2f7c580..39275a2 100755
--- a/configure
+++ b/configure
@@ -54,6 +54,8 @@ guess_arch() {
ARCH="arm"
elif check_define __i386__ || check_define __x86_64__ ; then
ARCH="i386"
+ elif check_define __loongarch__ ; then
+ ARCH="loongarch64"
elif check_define __m68k__ ; then
ARCH="m68k"
elif check_define __powerpc64__ ; then
@@ -141,7 +143,7 @@ Some influential environment variables:
prefixed with the given string.
ARCH force target architecture instead of trying to detect it.
- Valid values=[arm|aarch64|m68k|ppc64|ppc64le|s390x]
+ Valid values=[arm|aarch64|loongarch64|m68k|ppc64|ppc64le|s390x]
CC C compiler command
CFLAGS C compiler flags
--
2.34.1
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH 17/17] Build elf test cases instead of raw binaries
2024-05-11 11:53 [PATCH 00/17] RISU misc updates Richard Henderson
` (15 preceding siblings ...)
2024-05-11 11:53 ` [PATCH 16/17] configure: Enable loongarch64 Richard Henderson
@ 2024-05-11 11:54 ` Richard Henderson
2024-05-15 13:08 ` Philippe Mathieu-Daudé
2024-05-21 12:46 ` [PATCH 00/17] RISU misc updates Peter Maydell
17 siblings, 1 reply; 38+ messages in thread
From: Richard Henderson @ 2024-05-11 11:54 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
Makefile | 19 ++++++++++---------
test.ld | 12 ++++++++++++
test_aarch64.s | 4 ++--
test_arm.s | 16 +++++++++++-----
test_i386.S | 4 +++-
5 files changed, 38 insertions(+), 17 deletions(-)
create mode 100644 test.ld
diff --git a/Makefile b/Makefile
index ad7f879..2bd08aa 100644
--- a/Makefile
+++ b/Makefile
@@ -22,7 +22,8 @@ ALL_CFLAGS = -Wall -D_GNU_SOURCE -DARCH=$(ARCH) -U$(ARCH) $(BUILD_INC) $(CFLAGS)
PROG=risu
SRCS=risu.c comms.c risu_$(ARCH).c risu_reginfo_$(ARCH).c
HDRS=risu.h risu_reginfo_$(ARCH).h
-BINS=test_$(ARCH).bin
+BINO=test_$(ARCH).o
+BINE=test_$(ARCH).elf
# For dumping test patterns
RISU_BINS=$(wildcard *.risu.bin)
@@ -30,7 +31,7 @@ RISU_ASMS=$(patsubst %.bin,%.asm,$(RISU_BINS))
OBJS=$(SRCS:.c=.o)
-all: $(PROG) $(BINS)
+all: $(PROG) $(BINE)
dump: $(RISU_ASMS)
@@ -43,17 +44,17 @@ $(PROG): $(OBJS)
%.o: %.c $(HDRS)
$(CC) $(CPPFLAGS) $(ALL_CFLAGS) -o $@ -c $<
-%_$(ARCH).bin: %_$(ARCH).elf
- $(OBJCOPY) -O binary $< $@
+%_$(ARCH).o: %_$(ARCH).s
+ $(CC) -o $@ -c $<
-%_$(ARCH).elf: %_$(ARCH).s
- $(AS) -o $@ $<
-
-%_$(ARCH).elf: %_$(ARCH).S
+%_$(ARCH).o: %_$(ARCH).S
$(CC) $(CPPFLAGS) -o $@ -c $<
+%_$(ARCH).elf: test.ld %_$(ARCH).o
+ $(LD) -o $@ -T $^
+
clean:
- rm -f $(PROG) $(OBJS) $(BINS)
+ rm -f $(PROG) $(OBJS) $(BINO) $(BINE)
distclean: clean
rm -f config.h Makefile.in
diff --git a/test.ld b/test.ld
new file mode 100644
index 0000000..eb0a76a
--- /dev/null
+++ b/test.ld
@@ -0,0 +1,12 @@
+ENTRY(start)
+
+PHDRS {
+ text PT_LOAD FILEHDR PHDRS;
+}
+
+SECTIONS {
+ . = SIZEOF_HEADERS;
+ PROVIDE(start = .);
+ .text : { *(.text) } :text
+ .data : { *(.data) } :text
+}
diff --git a/test_aarch64.s b/test_aarch64.s
index f75d588..88902c6 100644
--- a/test_aarch64.s
+++ b/test_aarch64.s
@@ -80,6 +80,6 @@ fmov d31, #31.0
/* do compare.
* The manual says instr with bits (28,27) == 0 0 are UNALLOCATED
*/
-.int 0x00005af0
+.inst 0x00005af0
/* exit test */
-.int 0x00005af1
+.inst 0x00005af1
diff --git a/test_arm.s b/test_arm.s
index 49552f2..62582e7 100644
--- a/test_arm.s
+++ b/test_arm.s
@@ -9,20 +9,26 @@
* Peter Maydell (Linaro) - initial implementation
*******************************************************************************/
+.text
+
/* magic instruction to force ARM mode whether we were in ARM or Thumb before */
-.int 0xe0004778
+.inst 0xe0004778
+
/* Initialise the gp regs */
add r0, pc, #4
ldmia r0, {r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r14}
-b next
+b 1f
+
.int 0,1,2,3,4,5,6,7,8,9,10,11,12,14
-next:
+
+1:
msr CPSR_fs, #0
+
/* do compare.
* The space 0xE7F___F_ is guaranteed to always UNDEF
* and not to be allocated for insns in future architecture
* revisions.
*/
-.int 0xe7fe5af0
+.inst 0xe7fe5af0
/* exit test */
-.int 0xe7fe5af1
+.inst 0xe7fe5af1
diff --git a/test_i386.S b/test_i386.S
index 05344d7..2e2b090 100644
--- a/test_i386.S
+++ b/test_i386.S
@@ -13,6 +13,7 @@
/* Initialise the registers to avoid spurious mismatches */
+.text
#ifdef __x86_64__
#define BASE %rax
lea 2f(%rip), BASE
@@ -71,7 +72,8 @@
/* exit test */
ud1 %ecx, %eax
- .p2align 16
+.data
+ .balign 16
2:
.set i, 0
.rept 256
--
2.34.1
^ permalink raw reply related [flat|nested] 38+ messages in thread
* Re: [PATCH 02/17] Fix load_image error check for mmap
2024-05-11 11:53 ` [PATCH 02/17] Fix load_image error check for mmap Richard Henderson
@ 2024-05-15 12:51 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 38+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-05-15 12:51 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: peter.maydell
On 11/5/24 13:53, Richard Henderson wrote:
> mmap does not return null on failure, but MAP_FAILED.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> risu.c | 7 +++----
> 1 file changed, 3 insertions(+), 4 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 05/17] Remove return value from reginfo_dump
2024-05-11 11:53 ` [PATCH 05/17] Remove return value from reginfo_dump Richard Henderson
@ 2024-05-15 12:52 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 38+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-05-15 12:52 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: peter.maydell
On 11/5/24 13:53, Richard Henderson wrote:
> No uses actually checked the error indication. Even if we wanted
> to check ferror on the stream, we should do that generically rather
> than per arch.
>
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> risu.h | 4 ++--
> risu_reginfo_aarch64.c | 8 +++-----
> risu_reginfo_arm.c | 6 ++----
> risu_reginfo_i386.c | 6 ++----
> risu_reginfo_loongarch64.c | 6 ++----
> risu_reginfo_m68k.c | 6 ++----
> risu_reginfo_ppc64.c | 6 ++----
> risu_reginfo_s390x.c | 6 ++----
> 8 files changed, 17 insertions(+), 31 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 07/17] ppc64: Compare all bits of CCR
2024-05-11 11:53 ` [PATCH 07/17] ppc64: Compare all bits of CCR Richard Henderson
@ 2024-05-15 12:54 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 38+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-05-15 12:54 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: peter.maydell
On 11/5/24 13:53, Richard Henderson wrote:
> There are 32 bits in this register, and they are all valid
> comparision destinations.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> risu_reginfo_ppc64.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 10/17] aarch64: Tidy reginfo dumping ahead of ZA state
2024-05-11 11:53 ` [PATCH 10/17] aarch64: Tidy reginfo dumping ahead of ZA state Richard Henderson
@ 2024-05-15 12:55 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 38+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-05-15 12:55 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: peter.maydell
On 11/5/24 13:53, Richard Henderson wrote:
> A misalignment for sve_vl, plus add a bit more space
> on the left for the ZA[n] field name.
>
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> risu_reginfo_aarch64.c | 29 ++++++++++++++++++-----------
> 1 file changed, 18 insertions(+), 11 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 13/17] Use bool for reginfo_is_eq
2024-05-11 11:53 ` [PATCH 13/17] Use bool for reginfo_is_eq Richard Henderson
@ 2024-05-15 12:56 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 38+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-05-15 12:56 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: peter.maydell
On 11/5/24 13:53, Richard Henderson wrote:
> The function result is more naturally boolean.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> risu.h | 4 ++--
> risu_reginfo_aarch64.c | 4 ++--
> risu_reginfo_arm.c | 4 ++--
> risu_reginfo_i386.c | 4 ++--
> risu_reginfo_loongarch64.c | 4 ++--
> risu_reginfo_m68k.c | 16 ++++++++--------
> risu_reginfo_ppc64.c | 4 ++--
> risu_reginfo_s390x.c | 4 ++--
> 8 files changed, 22 insertions(+), 22 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 14/17] aarch64: Use bool for sve_{z,p}reg_is_eq
2024-05-11 11:53 ` [PATCH 14/17] aarch64: Use bool for sve_{z,p}reg_is_eq Richard Henderson
@ 2024-05-15 12:56 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 38+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-05-15 12:56 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: peter.maydell
On 11/5/24 13:53, Richard Henderson wrote:
> The functions results are more naturally boolean.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> risu_reginfo_aarch64.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 15/17] risu: Allow use of ELF test files
2024-05-11 11:53 ` [PATCH 15/17] risu: Allow use of ELF test files Richard Henderson
@ 2024-05-15 13:03 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 38+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-05-15 13:03 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: peter.maydell
On 11/5/24 13:53, Richard Henderson wrote:
> By using elf files, we make it easier to disassemble
> the test file, to match comparison failures to code.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> risu.c | 53 +++++++++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 53 insertions(+)
>
> diff --git a/risu.c b/risu.c
> index c28b4a5..e3845f6 100644
> --- a/risu.c
> +++ b/risu.c
> @@ -24,6 +24,8 @@
> #include <sys/mman.h>
> #include <fcntl.h>
> #include <string.h>
> +#include <elf.h>
> +#include <endian.h>
>
> #include "config.h"
> #include "risu.h"
> @@ -371,6 +373,57 @@ static void load_image(const char *imgfile)
> close(fd);
Maybe move the code here, doing 'addr = e32 | e64;', ...
> image_start = addr;
> image_start_address = (uintptr_t) addr;
> +
> + /*
> + * TODO: More complete parsing of ELF file, verify assumtion, namely:
> + * Single PT_LOAD covering the ELF header, code and data.
> + * For now, simply update image_start from the elf header.
> + */
> + if (memcmp(addr, ELFMAG, SELFMAG) == 0) {
> + const unsigned char *e_ident = addr;
> + bool swap, is_64;
> +
> + switch (e_ident[EI_DATA]) {
> + case ELFDATA2LSB:
> + swap = __BYTE_ORDER != __LITTLE_ENDIAN;
> + break;
> + case ELFDATA2MSB:
> + swap = __BYTE_ORDER == __LITTLE_ENDIAN;
> + break;
> + default:
> + fprintf(stderr, "%s: Bad elf header: EI_DATA = %x\n",
> + imgfile, e_ident[EI_DATA]);
> + exit(1);
> + }
> + switch (e_ident[EI_CLASS]) {
> + case ELFCLASS32:
> + is_64 = false;
> + break;
> + case ELFCLASS64:
> + is_64 = true;
> + break;
> + default:
> + fprintf(stderr, "%s: Bad elf header: EI_CLASS = %x\n",
> + imgfile, e_ident[EI_CLASS]);
> + exit(1);
> + }
> +
> + if (is_64) {
> + const Elf64_Ehdr *h64 = addr;
> + Elf64_Addr e64 = h64->e_entry;
> + if (swap) {
> + e64 = __builtin_bswap64(e64);
> + }
> + image_start = addr + e64;
> + } else {
> + const Elf32_Ehdr *h32 = addr;
> + Elf32_Addr e32 = h32->e_entry;
> + if (swap) {
> + e32 = __builtin_bswap32(e32);
> + }
> + image_start = addr + e32;
> + }
> + }
... otherwise image_start_address == &e_ident.
> }
>
> static int master(void)
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 16/17] configure: Enable loongarch64
2024-05-11 11:53 ` [PATCH 16/17] configure: Enable loongarch64 Richard Henderson
@ 2024-05-15 13:06 ` Philippe Mathieu-Daudé
2024-05-15 13:08 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 38+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-05-15 13:06 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: peter.maydell
On 11/5/24 13:53, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> configure | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 17/17] Build elf test cases instead of raw binaries
2024-05-11 11:54 ` [PATCH 17/17] Build elf test cases instead of raw binaries Richard Henderson
@ 2024-05-15 13:08 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 38+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-05-15 13:08 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: peter.maydell
On 11/5/24 13:54, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> Makefile | 19 ++++++++++---------
> test.ld | 12 ++++++++++++
> test_aarch64.s | 4 ++--
> test_arm.s | 16 +++++++++++-----
> test_i386.S | 4 +++-
Maybe briefly mention why the .S changes.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> 5 files changed, 38 insertions(+), 17 deletions(-)
> create mode 100644 test.ld
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 16/17] configure: Enable loongarch64
2024-05-11 11:53 ` [PATCH 16/17] configure: Enable loongarch64 Richard Henderson
2024-05-15 13:06 ` Philippe Mathieu-Daudé
@ 2024-05-15 13:08 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 38+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-05-15 13:08 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: peter.maydell, Song Gao
On 11/5/24 13:53, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> configure | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/configure b/configure
> index 2f7c580..39275a2 100755
> --- a/configure
> +++ b/configure
> @@ -54,6 +54,8 @@ guess_arch() {
> ARCH="arm"
> elif check_define __i386__ || check_define __x86_64__ ; then
> ARCH="i386"
> + elif check_define __loongarch__ ; then
> + ARCH="loongarch64"
> elif check_define __m68k__ ; then
> ARCH="m68k"
> elif check_define __powerpc64__ ; then
> @@ -141,7 +143,7 @@ Some influential environment variables:
> prefixed with the given string.
>
> ARCH force target architecture instead of trying to detect it.
> - Valid values=[arm|aarch64|m68k|ppc64|ppc64le|s390x]
> + Valid values=[arm|aarch64|loongarch64|m68k|ppc64|ppc64le|s390x]
>
> CC C compiler command
> CFLAGS C compiler flags
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 01/17] ppc64: Fix <sys/user.h> include order
2024-05-11 11:53 ` [PATCH 01/17] ppc64: Fix <sys/user.h> include order Richard Henderson
@ 2024-05-15 13:11 ` Philippe Mathieu-Daudé
2024-05-15 13:53 ` Richard Henderson
0 siblings, 1 reply; 38+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-05-15 13:11 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: peter.maydell
Hi Richard,
On 11/5/24 13:53, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> risu_ppc64.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/risu_ppc64.c b/risu_ppc64.c
> index 9df8d58..62cf6aa 100644
> --- a/risu_ppc64.c
> +++ b/risu_ppc64.c
> @@ -11,9 +11,8 @@
> * based on Peter Maydell's risu_arm.c
> *****************************************************************************/
>
> -#include <sys/user.h>
> -
> #include "risu.h"
> +#include <sys/user.h>
What is fixed exactly?
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 01/17] ppc64: Fix <sys/user.h> include order
2024-05-15 13:11 ` Philippe Mathieu-Daudé
@ 2024-05-15 13:53 ` Richard Henderson
2024-05-15 16:55 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 38+ messages in thread
From: Richard Henderson @ 2024-05-15 13:53 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel; +Cc: peter.maydell
On 5/15/24 15:11, Philippe Mathieu-Daudé wrote:
> Hi Richard,
>
> On 11/5/24 13:53, Richard Henderson wrote:
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>> risu_ppc64.c | 3 +--
>> 1 file changed, 1 insertion(+), 2 deletions(-)
>>
>> diff --git a/risu_ppc64.c b/risu_ppc64.c
>> index 9df8d58..62cf6aa 100644
>> --- a/risu_ppc64.c
>> +++ b/risu_ppc64.c
>> @@ -11,9 +11,8 @@
>> * based on Peter Maydell's risu_arm.c
>> *****************************************************************************/
>> -#include <sys/user.h>
>> -
>> #include "risu.h"
>> +#include <sys/user.h>
>
> What is fixed exactly?
I don't remember (patch dated in 2022).
It is probably a #define namespace issue with cfarm hosts running Centos 7.9?
I suppose I should investigate, and drop it if irrelevant.
r~
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 01/17] ppc64: Fix <sys/user.h> include order
2024-05-15 13:53 ` Richard Henderson
@ 2024-05-15 16:55 ` Philippe Mathieu-Daudé
2024-05-16 13:32 ` Richard Henderson
0 siblings, 1 reply; 38+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-05-15 16:55 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: peter.maydell
On 15/5/24 15:53, Richard Henderson wrote:
> On 5/15/24 15:11, Philippe Mathieu-Daudé wrote:
>> Hi Richard,
>>
>> On 11/5/24 13:53, Richard Henderson wrote:
>>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>>> ---
>>> risu_ppc64.c | 3 +--
>>> 1 file changed, 1 insertion(+), 2 deletions(-)
>>>
>>> diff --git a/risu_ppc64.c b/risu_ppc64.c
>>> index 9df8d58..62cf6aa 100644
>>> --- a/risu_ppc64.c
>>> +++ b/risu_ppc64.c
>>> @@ -11,9 +11,8 @@
>>> * based on Peter Maydell's risu_arm.c
>>>
>>> *****************************************************************************/
>>> -#include <sys/user.h>
>>> -
>>> #include "risu.h"
>>> +#include <sys/user.h>
>>
>> What is fixed exactly?
>
> I don't remember (patch dated in 2022).
> It is probably a #define namespace issue with cfarm hosts running Centos
> 7.9?
> I suppose I should investigate, and drop it if irrelevant.
It was just out of curiosity (I had a quick look at the headers
and couldn't see anything obvious, and other headers also include
system headers before "risu.h").
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 01/17] ppc64: Fix <sys/user.h> include order
2024-05-15 16:55 ` Philippe Mathieu-Daudé
@ 2024-05-16 13:32 ` Richard Henderson
0 siblings, 0 replies; 38+ messages in thread
From: Richard Henderson @ 2024-05-16 13:32 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel; +Cc: peter.maydell
On 5/15/24 18:55, Philippe Mathieu-Daudé wrote:
> On 15/5/24 15:53, Richard Henderson wrote:
>> On 5/15/24 15:11, Philippe Mathieu-Daudé wrote:
>>> Hi Richard,
>>>
>>> On 11/5/24 13:53, Richard Henderson wrote:
>>>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>>>> ---
>>>> risu_ppc64.c | 3 +--
>>>> 1 file changed, 1 insertion(+), 2 deletions(-)
>>>>
>>>> diff --git a/risu_ppc64.c b/risu_ppc64.c
>>>> index 9df8d58..62cf6aa 100644
>>>> --- a/risu_ppc64.c
>>>> +++ b/risu_ppc64.c
>>>> @@ -11,9 +11,8 @@
>>>> * based on Peter Maydell's risu_arm.c
>>>> *****************************************************************************/
>>>> -#include <sys/user.h>
>>>> -
>>>> #include "risu.h"
>>>> +#include <sys/user.h>
>>>
>>> What is fixed exactly?
>>
>> I don't remember (patch dated in 2022).
>> It is probably a #define namespace issue with cfarm hosts running Centos 7.9?
>> I suppose I should investigate, and drop it if irrelevant.
>
> It was just out of curiosity (I had a quick look at the headers
> and couldn't see anything obvious, and other headers also include
> system headers before "risu.h").
Root cause: <sys/user.h> is not self-contained on centos 7.7:
In file included from risu_ppc64.c:14:
/usr/include/sys/user.h:27:9: error: unknown type name ‘size_t’
27 | size_t u_tsize; /* text size (pages) */
| ^~~~~~
I'll update the commit message.
r~
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 03/17] Standardize reginfo_dump_mismatch printing
2024-05-11 11:53 ` [PATCH 03/17] Standardize reginfo_dump_mismatch printing Richard Henderson
@ 2024-05-21 12:20 ` Peter Maydell
0 siblings, 0 replies; 38+ messages in thread
From: Peter Maydell @ 2024-05-21 12:20 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel
On Sat, 11 May 2024 at 12:54, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Hoist the "master vs apprentice" label to apprentice(), since
> we will want different labels for dumping. Remove all of the
> "mismatch" text from reginfo_dump_mismatch -- just print "vs".
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> risu.h | 4 ++--
> risu.c | 1 +
> risu_reginfo_aarch64.c | 12 +++++-------
> risu_reginfo_arm.c | 18 +++++++++---------
> risu_reginfo_i386.c | 6 +-----
> risu_reginfo_loongarch64.c | 11 ++++-------
> risu_reginfo_m68k.c | 23 +++++++----------------
> risu_reginfo_ppc64.c | 25 ++++++++++++-------------
> risu_reginfo_s390x.c | 18 +++++++-----------
> 9 files changed, 48 insertions(+), 70 deletions(-)
>
> diff --git a/risu.h b/risu.h
> index 2c43384..1b87af2 100644
> --- a/risu.h
> +++ b/risu.h
> @@ -123,8 +123,8 @@ int reginfo_is_eq(struct reginfo *r1, struct reginfo *r2);
> /* print reginfo state to a stream, returns 1 on success, 0 on failure */
> int reginfo_dump(struct reginfo *ri, FILE * f);
>
> -/* reginfo_dump_mismatch: print mismatch details to a stream, ret nonzero=ok */
> -int reginfo_dump_mismatch(struct reginfo *m, struct reginfo *a, FILE *f);
> +/* reginfo_dump_mismatch: print mismatch details to a stream */
> +void reginfo_dump_mismatch(struct reginfo *m, struct reginfo *a, FILE *f);
This commit is also changing the return type of the function,
which the commit message doesn't say anything about. Since this
is only risu, not QEMU proper, I don't think we strictly need
to disentangle this into two commits, but we should describe
both changes in the commit message.
(Since the only callsite doesn't check the return value and
in any case if it cared it could call ferror() itself,
switching to 'void' is fine.)
thanks
-- PMM
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 06/17] ppc64: Clean register values in reginfo_init
2024-05-11 11:53 ` [PATCH 06/17] ppc64: Clean register values in reginfo_init Richard Henderson
@ 2024-05-21 12:22 ` Peter Maydell
0 siblings, 0 replies; 38+ messages in thread
From: Peter Maydell @ 2024-05-21 12:22 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel
On Sat, 11 May 2024 at 12:54, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Smash the stack and thread pointers to deadbeef, as is common
> for the other architectures. This allows us to drop these
> special cases within reginfo_is_eq and reginfo_dump_mismatch.
>
> Do not copy the unused special registers that are packed into gregs[].
> Most of these are related to system instructions and thus are not
> manipulable via the user-mode instructions targeted by RISU. LNK and
> CTR are not initialized by risugen, and since in general we cannot
> test branches with risugen these can be ignored. This leaves only
> XER and CCR as the only special registers to be copied.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 08/17] ppc64: Simplify reginfo_is_eq
2024-05-11 11:53 ` [PATCH 08/17] ppc64: Simplify reginfo_is_eq Richard Henderson
@ 2024-05-21 12:23 ` Peter Maydell
0 siblings, 0 replies; 38+ messages in thread
From: Peter Maydell @ 2024-05-21 12:23 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel
On Sat, 11 May 2024 at 12:54, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Since we now only copy into reginfo exactly what we want to compare,
> and since we zero all unused padding and reserved space, we need not
> enumerate each field for comparison, but defer to memcmp.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 09/17] ppc64: Clean up reginfo_dump
2024-05-11 11:53 ` [PATCH 09/17] ppc64: Clean up reginfo_dump Richard Henderson
@ 2024-05-21 12:25 ` Peter Maydell
0 siblings, 0 replies; 38+ messages in thread
From: Peter Maydell @ 2024-05-21 12:25 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel
On Sat, 11 May 2024 at 12:54, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Dump only the registers that we copied in reginfo_init.
> Improve the formatting and layout of what we do dump
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>> ---
> risu_reginfo_ppc64.c | 51 ++++++++++++++++++--------------------------
> 1 file changed, 21 insertions(+), 30 deletions(-)
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 12/17] aarch64: Trivial SME test
2024-05-11 11:53 ` [PATCH 12/17] aarch64: Trivial SME test Richard Henderson
@ 2024-05-21 12:27 ` Peter Maydell
0 siblings, 0 replies; 38+ messages in thread
From: Peter Maydell @ 2024-05-21 12:27 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel
On Sat, 11 May 2024 at 12:54, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> test_sme_aarch64.s | 63 ++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 63 insertions(+)
> create mode 100644 test_sme_aarch64.s
Looks like we don't have makefile infrastructure for building
any of these "trivial test" test_foo.s files, so this is fine.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 00/17] RISU misc updates
2024-05-11 11:53 [PATCH 00/17] RISU misc updates Richard Henderson
` (16 preceding siblings ...)
2024-05-11 11:54 ` [PATCH 17/17] Build elf test cases instead of raw binaries Richard Henderson
@ 2024-05-21 12:46 ` Peter Maydell
17 siblings, 0 replies; 38+ messages in thread
From: Peter Maydell @ 2024-05-21 12:46 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel
On Sat, 11 May 2024 at 12:54, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Some of these have been sitting on a branch for a couple of years.
> Except perhaps the first, which I assume to be some sort of odd
> build error from the time, they still seem reasonable.
>
> There are some updates for SME1, but not yet the ZT register for SME2.
> I'll get to that later after I've done the qemu linux-user work.
>
> Finally, let's start phasing out raw binary test cases. We can
> make it much easier for ourselves if we package test cases in ELF,
> which "objdump -d" can parse directly, without having to be given
> all sorts of "-b binary -m some-arch-flags" etc.
>
> For future work, I plan to make changes to risugen so that it writes
> out asm files and invokes the assembler and linker to produce the
> final output file.
Commits 1-14 and 16 applied to the risu git repo (with the
commit message nits for patches 1 and 3 fixed).
(This isn't a "nope" for the elf related stuff, just to be clear:
I saw Philippe had a comment on patch 15 and figured it would be
best to take all the easy cleanup patches immediately so any
respin is just elf bits.)
thanks
-- PMM
^ permalink raw reply [flat|nested] 38+ messages in thread
end of thread, other threads:[~2024-05-21 12:47 UTC | newest]
Thread overview: 38+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-05-11 11:53 [PATCH 00/17] RISU misc updates Richard Henderson
2024-05-11 11:53 ` [PATCH 01/17] ppc64: Fix <sys/user.h> include order Richard Henderson
2024-05-15 13:11 ` Philippe Mathieu-Daudé
2024-05-15 13:53 ` Richard Henderson
2024-05-15 16:55 ` Philippe Mathieu-Daudé
2024-05-16 13:32 ` Richard Henderson
2024-05-11 11:53 ` [PATCH 02/17] Fix load_image error check for mmap Richard Henderson
2024-05-15 12:51 ` Philippe Mathieu-Daudé
2024-05-11 11:53 ` [PATCH 03/17] Standardize reginfo_dump_mismatch printing Richard Henderson
2024-05-21 12:20 ` Peter Maydell
2024-05-11 11:53 ` [PATCH 04/17] Add --fulldump and --diffdup options Richard Henderson
2024-05-11 11:53 ` [PATCH 05/17] Remove return value from reginfo_dump Richard Henderson
2024-05-15 12:52 ` Philippe Mathieu-Daudé
2024-05-11 11:53 ` [PATCH 06/17] ppc64: Clean register values in reginfo_init Richard Henderson
2024-05-21 12:22 ` Peter Maydell
2024-05-11 11:53 ` [PATCH 07/17] ppc64: Compare all bits of CCR Richard Henderson
2024-05-15 12:54 ` Philippe Mathieu-Daudé
2024-05-11 11:53 ` [PATCH 08/17] ppc64: Simplify reginfo_is_eq Richard Henderson
2024-05-21 12:23 ` Peter Maydell
2024-05-11 11:53 ` [PATCH 09/17] ppc64: Clean up reginfo_dump Richard Henderson
2024-05-21 12:25 ` Peter Maydell
2024-05-11 11:53 ` [PATCH 10/17] aarch64: Tidy reginfo dumping ahead of ZA state Richard Henderson
2024-05-15 12:55 ` Philippe Mathieu-Daudé
2024-05-11 11:53 ` [PATCH 11/17] aarch64: Add support for ZA storage Richard Henderson
2024-05-11 11:53 ` [PATCH 12/17] aarch64: Trivial SME test Richard Henderson
2024-05-21 12:27 ` Peter Maydell
2024-05-11 11:53 ` [PATCH 13/17] Use bool for reginfo_is_eq Richard Henderson
2024-05-15 12:56 ` Philippe Mathieu-Daudé
2024-05-11 11:53 ` [PATCH 14/17] aarch64: Use bool for sve_{z,p}reg_is_eq Richard Henderson
2024-05-15 12:56 ` Philippe Mathieu-Daudé
2024-05-11 11:53 ` [PATCH 15/17] risu: Allow use of ELF test files Richard Henderson
2024-05-15 13:03 ` Philippe Mathieu-Daudé
2024-05-11 11:53 ` [PATCH 16/17] configure: Enable loongarch64 Richard Henderson
2024-05-15 13:06 ` Philippe Mathieu-Daudé
2024-05-15 13:08 ` Philippe Mathieu-Daudé
2024-05-11 11:54 ` [PATCH 17/17] Build elf test cases instead of raw binaries Richard Henderson
2024-05-15 13:08 ` Philippe Mathieu-Daudé
2024-05-21 12:46 ` [PATCH 00/17] RISU misc updates Peter Maydell
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).