Re: [PATCH v2] target/arm: Disable cryptographic instructions when neon is disabled

[Richard Henderson <richard.henderson@linaro.org>]

On 4/27/22 02:01, Damien Hedde wrote:
> As of now, cryptographic instructions ISAR fields are never cleared so
> we can end up with a cpu with cryptographic instructions but no
> floating-point/neon instructions which is not a possible configuration
> according to ARM specifications.
> 
> In QEMU, we have 3 kinds of cpus regarding cryptographic instructions:
> + no support
> + cortex-a57/a72: cryptographic extension is optional,
>    floating-point/neon is not.
> + cortex-a53: crytographic extension is optional as well as
>    floationg-point/neon. But cryptographic requires
>    floating-point/neon support.
> 
> Therefore we can safely clear the ISAR fields when neon is disabled.
> 
> Note that other arm cpus seem to follow this. For example cortex-a55 is
> like cortex-a53 and cortex-a76/cortex-a710 are like cortex-a57/a72.
> 
> Signed-off-by: Damien Hedde<damien.hedde@greensocs.com>
> ---
> 
> v2: also clear SHA3 / SM3 / SM4 (Richard)
> ---
>   target/arm/cpu.c | 9 +++++++++
>   1 file changed, 9 insertions(+)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~