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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id i11sm3029224pjg.0.2020.02.28.08.57.34 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 28 Feb 2020 08:57:35 -0800 (PST) Subject: Re: [PATCH v4 1/7] target/arm: Improve masking of HCR RES0 bits To: Peter Maydell References: <20200225180831.26078-1-richard.henderson@linaro.org> <20200225180831.26078-2-richard.henderson@linaro.org> From: Richard Henderson Message-ID: Date: Fri, 28 Feb 2020 08:57:33 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm , QEMU Developers Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 2/28/20 8:22 AM, Peter Maydell wrote: >> + if (ri->state == ARM_CP_STATE_AA32) { >> + /* >> + * Writes from aarch32 mode have more RES0 bits. >> + * This includes TDZ, RW, E2H, and more. >> + */ >> + valid_mask &= ~0xff80ff8c90000000ull; >> + } > > Isn't bit HCR2 bit 16 (aka bit 32+16==48 here) also RES0 from AArch32 ? Yes, and it's set in the above. > I'm not really a fan of the hex-number here either, given we > have HCR_* constants. While plenty of those bits have names, many don't. Shall I simply name all of the ones that have names, and that differ from the aa64 masking? r~