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([2602:47:d490:6901:9454:a46f:1c22:a7c6]) by smtp.gmail.com with ESMTPSA id em5-20020a17090b014500b002680b2d2ab6sm5942129pjb.19.2023.08.05.10.58.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 05 Aug 2023 10:58:25 -0700 (PDT) Message-ID: Date: Sat, 5 Aug 2023 10:58:23 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.13.0 Subject: Re: [RFC][PATCH] Reduce generated code by 3% by increasing MMU indices Content-Language: en-US To: Helge Deller Cc: qemu-devel@nongnu.org References: <53a2d13f-b508-0dba-5f0a-1b158372d1a4@linaro.org> From: Richard Henderson In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x536.google.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.089, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 8/5/23 10:43, Helge Deller wrote: >> If there were a way to change no more than two lines of code, that would be >> fine. But otherwise I don't see this as being worth making the rest of the >> code base any more complex. > > Ok. What about that 6-line patch below for x86? > It's trivial and all what's needed for x86. > Btw, any index which is >= 9 will use the shorter code sequence. > > Helge > > diff --git a/target/i386/cpu.h b/target/i386/cpu.h > index e0771a1043..3e71e666db 100644 > --- a/target/i386/cpu.h > +++ b/target/i386/cpu.h > @@ -2251,11 +2251,11 @@ uint64_t cpu_get_tsc(CPUX86State *env); > #define cpu_list x86_cpu_list > > /* MMU modes definitions */ > -#define MMU_KSMAP_IDX 0 > -#define MMU_USER_IDX 1 > -#define MMU_KNOSMAP_IDX 2 > -#define MMU_NESTED_IDX 3 > -#define MMU_PHYS_IDX 4 > +#define MMU_KSMAP_IDX 11 > +#define MMU_USER_IDX 12 > +#define MMU_KNOSMAP_IDX 13 > +#define MMU_NESTED_IDX 14 > +#define MMU_PHYS_IDX 15 No. The small patch would need to apply to all guests. Perhaps something to handle indexing of CPUTLBDescFast, e.g. static inline CPUTLBDescFast cputlb_fast(CPUTLB *tlb, unsigned idx) { return &tlb->f[NB_MMU_MODES - 1 - idx]; } There's already tlb_mask_table_ofs, which handles all tcg backends; you just need to adjust that and cputlb.c. Introduce cputlb_fast with normal indexing in one patch, and then the second patch to invert the indexing may well be exactly two lines. :-) r~