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References: <20181207085635.4291-1-mark.cave-ayland@ilande.co.uk>
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From: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <e4de9517-e90f-076a-a358-eec1e1d2de64@linaro.org>
Date: Mon, 10 Dec 2018 12:49:15 -0600
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Subject: Re: [Qemu-devel] [RFC PATCH 2/6] target/ppc: introduce get_avr64()
 and set_avr64() helpers for VMX register access
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To: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>, qemu-devel@nongnu.org, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au

On 12/7/18 2:56 AM, Mark Cave-Ayland wrote:
> +    avr = tcg_temp_new_i64();                                                 \
>      EA = tcg_temp_new();                                                      \
>      gen_addr_reg_index(ctx, EA);                                              \
>      tcg_gen_andi_tl(EA, EA, ~0xf);                                            \
>      /* We only need to swap high and low halves. gen_qemu_ld64_i64 does       \
>         necessary 64-bit byteswap already. */                                  \
>      if (ctx->le_mode) {                                                       \
> -        gen_qemu_ld64_i64(ctx, cpu_avrl[rD(ctx->opcode)], EA);                \
> +        gen_qemu_ld64_i64(ctx, avr, EA);                                      \
> +        set_avr64(rD(ctx->opcode), avr, false);                               \
>          tcg_gen_addi_tl(EA, EA, 8);                                           \
> -        gen_qemu_ld64_i64(ctx, cpu_avrh[rD(ctx->opcode)], EA);                \
> +        gen_qemu_ld64_i64(ctx, avr, EA);                                      \
> +        set_avr64(rD(ctx->opcode), avr, true);  

An accurate conversion, but I'm going to call this an existing bug:

The writeback to both avr{l,h} should be delayed until all exceptions have been
raised.  Thus you should perform the two gen_qemu_ld64_i64 into two temporaries
and only then write them both back via set_avr64.

Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~