[Qemu-devel] [PATCH v2 00/14] Make Q35 devices closer to Qemu object model.

[Qemu-devel] [PATCH v2 00/14] Make Q35 devices closer to Qemu object model.

[Efimov Vasily]

The patch series makes several devices closer to Qemu object model.

I am developing a tool that automatize creation of device and machine models.

Recently, I've take part in development of several models. And I noticed that
a significant part of code is same. The examples are:
- Each device represented by a header and a source.
- The device or machine class is described by a set of callbacks containing in
TypeInfo structure.
- Each TypeInfo structure is accounted by a register function.
- A register function is sheduled by a type_init macro.
- Class and state structures of an inherited type are prepended by ones of the
parent type.
- A device must have VM state description.
- A device or a machine can have properties.
- A device can use internal APIs such as: timer, chardev, blockdev, IRQ,
system bys memory and port mapping, PCI BARs, PCI MSI(X), etc.
- A machine consists of devices and memory tree. Devices are linked by IRQs and
buses and assigned property values.
- All of the above should follow the Qemu coding style.

For every listed item can be generated a stub code. All stubs can be generated
with respect to each other forming compileable device (or machine). Ideally,
a programmer have to implement custom device/machine logic and to assign
meaningful names to variables, functions, macroses etc. using a refactoring
tool.

Of cource, a device/machine description for the tool has to be significantly
smaller than the code the tool produced. A GUI constructor is preferred too.

I've chosed Q35 machine to test the tool. The Q35 is one of the most 
complex boards. I have implemented 64-bit CPU, soft MMU, 1GB RAM, 1 HDD,
PCI, USB machine variant. Most of devices is instantiated using the object
model. Some logic (I/O port 80, I/O port F0, A20 line) is dedicated to new
devices. The stubs for thay is also generated by the tool.

In course of implementing Q35 I've noticed that some device models does not
follow Qemu object model close enough. The patch series is desined to make them
closer.

Change log:

v1 -> v2:
A patch was added after 11-th one. The patch introduces function
isa_connect_gpio_out needed by new version of consequent patch.

 01: Git global option diff.renames was set true to generate the patch avoiding
checkpatch.pl issues.

 02, 05: qdev_prop_allow_set_link_before_realize is used instead of
object_property_allow_set_link.

 07, 08: Named GPIO was used for a20 line.

 10, 11: The patches were rebased against the patch series
https://lists.gnu.org/archive/html/qemu-devel/2016-06/msg05619.html

 10: Named GPIO is used for gsi. The name is "gsi" with alias ICH9_GPIO_GSI.

 12: It's a new patch. The patch introduces function isa_connect_gpio_out.

 13 (previously 12): Use isa_connect_gpio_out instead of isa_init_irq.


Efimov Vasily (14):
  ide: move headers to include folder
  pcspk: convert "pit" property type from ptr to link
  vmport: identify vmport type by macro TYPE_VMPORT
  pflash: make TYPE_CFI_PFLASH0{1,2} macros public
  Q35: implement property interfece to several parameters
  pc_q35: configure Q35 instance using properties
  pckbd: handle A20 IRQ as GPIO
  port92: handle A20 IRQ as GPIO
  ICH9 SMB: make TYPE_ICH9_SMB_DEVICE macro public
  ICH9 LPC: handle GSI as qdev GPIO
  ICH9 LPC: move call of isa_bus_irqs to 'realize' method
  isa: introduce wrapper isa_connect_gpio_out
  MC146818 RTC: add GPIO access to output IRQ
  ICH9 LPC: configure PCI IRQs routing internally

 hw/audio/pcspk.c                  |  9 +++++++--
 hw/block/pflash_cfi01.c           |  1 -
 hw/block/pflash_cfi02.c           |  1 -
 hw/i2c/smbus_ich9.c               |  1 -
 hw/i386/pc.c                      | 10 +++++-----
 hw/i386/pc_q35.c                  | 30 +++++++++++++++++-------------
 hw/ide/ahci.c                     |  2 +-
 hw/input/pckbd.c                  | 21 +++++++--------------
 hw/isa/isa-bus.c                  |  7 +++++++
 hw/isa/lpc_ich9.c                 | 15 ++++++++++++---
 hw/misc/vmport.c                  |  1 -
 hw/pci-host/q35.c                 | 20 ++++++++++++++++++++
 hw/timer/mc146818rtc.c            |  6 ++++--
 include/hw/audio/pcspk.h          |  2 +-
 include/hw/block/flash.h          |  3 +++
 include/hw/i386/ich9.h            |  9 +++++----
 include/hw/i386/pc.h              |  8 +++++++-
 {hw => include/hw}/ide/ahci.h     |  0
 {hw => include/hw}/ide/internal.h |  0
 {hw => include/hw}/ide/pci.h      |  0
 include/hw/isa/isa.h              |  1 +
 include/hw/pci-host/q35.h         |  5 +++++
 22 files changed, 102 insertions(+), 50 deletions(-)
 rename {hw => include/hw}/ide/ahci.h (100%)
 rename {hw => include/hw}/ide/internal.h (100%)
 rename {hw => include/hw}/ide/pci.h (100%)

-- 
2.7.4

[Qemu-devel] [PATCH v2 01/14] ide: move headers to include folder

[Efimov Vasily]

The patch moves "hw/ide/achi.h", "hw/ide/pci.h" and "hw/ide/internal.h" headers
to corresponding folders inside "include" folder alike other Qemu headers.

Signed-off-by: Efimov Vasily <real@ispras.ru>
---
 hw/ide/ahci.c                     | 2 +-
 {hw => include/hw}/ide/ahci.h     | 0
 {hw => include/hw}/ide/internal.h | 0
 {hw => include/hw}/ide/pci.h      | 0
 4 files changed, 1 insertion(+), 1 deletion(-)
 rename {hw => include/hw}/ide/ahci.h (100%)
 rename {hw => include/hw}/ide/internal.h (100%)
 rename {hw => include/hw}/ide/pci.h (100%)

diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
index 502d4f1..b1a7b65 100644
--- a/hw/ide/ahci.c
+++ b/hw/ide/ahci.c
@@ -30,7 +30,7 @@
 #include "qemu/error-report.h"
 #include "sysemu/block-backend.h"
 #include "sysemu/dma.h"
-#include "internal.h"
+#include <hw/ide/internal.h>
 #include <hw/ide/pci.h>
 #include <hw/ide/ahci.h>
 
diff --git a/hw/ide/ahci.h b/include/hw/ide/ahci.h
similarity index 100%
rename from hw/ide/ahci.h
rename to include/hw/ide/ahci.h
diff --git a/hw/ide/internal.h b/include/hw/ide/internal.h
similarity index 100%
rename from hw/ide/internal.h
rename to include/hw/ide/internal.h
diff --git a/hw/ide/pci.h b/include/hw/ide/pci.h
similarity index 100%
rename from hw/ide/pci.h
rename to include/hw/ide/pci.h
-- 
2.7.4

[Qemu-devel] [PATCH v2 02/14] pcspk: convert "pit" property type from ptr to link

[Efimov Vasily]

The speaker device needs pointer to ISA PIT device to operate. But according to
qdev-properties.h, properties of pointer type should be avoided. It seems a
link type property is a good substitution.

Signed-off-by: Efimov Vasily <real@ispras.ru>
---
 hw/audio/pcspk.c         | 9 +++++++--
 include/hw/audio/pcspk.h | 2 +-
 2 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/hw/audio/pcspk.c b/hw/audio/pcspk.c
index d259960..a7aa4e9 100644
--- a/hw/audio/pcspk.c
+++ b/hw/audio/pcspk.c
@@ -31,6 +31,7 @@
 #include "qemu/timer.h"
 #include "hw/timer/i8254.h"
 #include "hw/audio/pcspk.h"
+#include "qapi/error.h"
 
 #define PCSPK_BUF_LEN 1792
 #define PCSPK_SAMPLE_RATE 32000
@@ -169,6 +170,11 @@ static void pcspk_initfn(Object *obj)
     PCSpkState *s = PC_SPEAKER(obj);
 
     memory_region_init_io(&s->ioport, OBJECT(s), &pcspk_io_ops, s, "pcspk", 1);
+
+    object_property_add_link(obj, "pit", TYPE_I8254,
+                             (Object **)&s->pit,
+                             qdev_prop_allow_set_link_before_realize,
+                             0, &error_abort);
 }
 
 static void pcspk_realizefn(DeviceState *dev, Error **errp)
@@ -183,7 +189,6 @@ static void pcspk_realizefn(DeviceState *dev, Error **errp)
 
 static Property pcspk_properties[] = {
     DEFINE_PROP_UINT32("iobase", PCSpkState, iobase,  -1),
-    DEFINE_PROP_PTR("pit", PCSpkState, pit),
     DEFINE_PROP_END_OF_LIST(),
 };
 
@@ -194,7 +199,7 @@ static void pcspk_class_initfn(ObjectClass *klass, void *data)
     dc->realize = pcspk_realizefn;
     set_bit(DEVICE_CATEGORY_SOUND, dc->categories);
     dc->props = pcspk_properties;
-    /* Reason: pointer property "pit", realize sets global pcspk_state */
+    /* Reason: realize sets global pcspk_state */
     dc->cannot_instantiate_with_device_add_yet = true;
 }
 
diff --git a/include/hw/audio/pcspk.h b/include/hw/audio/pcspk.h
index ef95dd1..33e46a5 100644
--- a/include/hw/audio/pcspk.h
+++ b/include/hw/audio/pcspk.h
@@ -38,7 +38,7 @@ static inline ISADevice *pcspk_init(ISABus *bus, ISADevice *pit)
     isadev = isa_create(bus, TYPE_PC_SPEAKER);
     dev = DEVICE(isadev);
     qdev_prop_set_uint32(dev, "iobase", 0x61);
-    qdev_prop_set_ptr(dev, "pit", pit);
+    object_property_set_link(OBJECT(dev), OBJECT(pit), "pit", NULL);
     qdev_init_nofail(dev);
 
     return isadev;
-- 
2.7.4

[Qemu-devel] [PATCH v2 03/14] vmport: identify vmport type by macro TYPE_VMPORT

[Efimov Vasily]

Currently vmport device is identified by the string literal. Using a
preprocessor alias instead is preferable.

Signed-off-by: Efimov Vasily <real@ispras.ru>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
---
 hw/misc/vmport.c     | 1 -
 include/hw/i386/pc.h | 3 ++-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/misc/vmport.c b/hw/misc/vmport.c
index 6896789..c763811 100644
--- a/hw/misc/vmport.c
+++ b/hw/misc/vmport.c
@@ -36,7 +36,6 @@
 #define VMPORT_ENTRIES 0x2c
 #define VMPORT_MAGIC   0x564D5868
 
-#define TYPE_VMPORT "vmport"
 #define VMPORT(obj) OBJECT_CHECK(VMPortState, (obj), TYPE_VMPORT)
 
 typedef struct VMPortState
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 49566c8..dc7503d 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -199,11 +199,12 @@ typedef struct GSIState {
 void gsi_handler(void *opaque, int n, int level);
 
 /* vmport.c */
+#define TYPE_VMPORT "vmport"
 typedef uint32_t (VMPortReadFunc)(void *opaque, uint32_t address);
 
 static inline void vmport_init(ISABus *bus)
 {
-    isa_create_simple(bus, "vmport");
+    isa_create_simple(bus, TYPE_VMPORT);
 }
 
 void vmport_register(unsigned char command, VMPortReadFunc *func, void *opaque);
-- 
2.7.4

[Qemu-devel] [PATCH v2 04/14] pflash: make TYPE_CFI_PFLASH0{1, 2} macros public

[Efimov Vasily]

qdev API can be used to create CFI pflash devices despite existance of helper
functions. The type name is needed in course of such creation. Using the
preprocessor alias instead of the string literal itself is preferable.

The patch makes the aliases accessible through the header.

Signed-off-by: Efimov Vasily <real@ispras.ru>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
---
 hw/block/pflash_cfi01.c  | 1 -
 hw/block/pflash_cfi02.c  | 1 -
 include/hw/block/flash.h | 3 +++
 3 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/hw/block/pflash_cfi01.c b/hw/block/pflash_cfi01.c
index 31585e3..62d7a56 100644
--- a/hw/block/pflash_cfi01.c
+++ b/hw/block/pflash_cfi01.c
@@ -65,7 +65,6 @@ do {                                                        \
 #define DPRINTF(fmt, ...) do { } while (0)
 #endif
 
-#define TYPE_CFI_PFLASH01 "cfi.pflash01"
 #define CFI_PFLASH01(obj) OBJECT_CHECK(pflash_t, (obj), TYPE_CFI_PFLASH01)
 
 #define PFLASH_BE          0
diff --git a/hw/block/pflash_cfi02.c b/hw/block/pflash_cfi02.c
index 5f10610..4f6105c 100644
--- a/hw/block/pflash_cfi02.c
+++ b/hw/block/pflash_cfi02.c
@@ -57,7 +57,6 @@ do {                                                       \
 
 #define PFLASH_LAZY_ROMD_THRESHOLD 42
 
-#define TYPE_CFI_PFLASH02 "cfi.pflash02"
 #define CFI_PFLASH02(obj) OBJECT_CHECK(pflash_t, (obj), TYPE_CFI_PFLASH02)
 
 struct pflash_t {
diff --git a/include/hw/block/flash.h b/include/hw/block/flash.h
index 50ccbbc..a088baa 100644
--- a/include/hw/block/flash.h
+++ b/include/hw/block/flash.h
@@ -5,6 +5,9 @@
 
 #include "exec/memory.h"
 
+#define TYPE_CFI_PFLASH01 "cfi.pflash01"
+#define TYPE_CFI_PFLASH02 "cfi.pflash02"
+
 typedef struct pflash_t pflash_t;
 
 /* pflash_cfi01.c */
-- 
2.7.4

[Qemu-devel] [PATCH v2 05/14] Q35: implement property interfece to several parameters

[Efimov Vasily]

During creation of Q35 instance several parameters are set using direct access.
It violates Qemu device model. Correctly, the parameters should be handled as
object properties.

The patch adds four link type properties for fields:
mch.ram_memory
mch.pci_address_space
mch.system_memory
mch.address_space_io
And, it adds two size type properties for fields:
mch.below_4g_mem_size
mch.above_4g_mem_size

Signed-off-by: Efimov Vasily <real@ispras.ru>
---
 hw/pci-host/q35.c         | 20 ++++++++++++++++++++
 include/hw/i386/pc.h      |  2 ++
 include/hw/pci-host/q35.h |  5 +++++
 3 files changed, 27 insertions(+)

diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c
index 70f897e..03be05d 100644
--- a/hw/pci-host/q35.c
+++ b/hw/pci-host/q35.c
@@ -127,6 +127,10 @@ static Property mch_props[] = {
     DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, Q35PCIHost,
                      mch.pci_hole64_size, DEFAULT_PCI_HOLE64_SIZE),
     DEFINE_PROP_UINT32("short_root_bus", Q35PCIHost, mch.short_root_bus, 0),
+    DEFINE_PROP_SIZE(PCI_HOST_BELOW_4G_MEM_SIZE, Q35PCIHost,
+                     mch.below_4g_mem_size, 0),
+    DEFINE_PROP_SIZE(PCI_HOST_ABOVE_4G_MEM_SIZE, Q35PCIHost,
+                     mch.above_4g_mem_size, 0),
     DEFINE_PROP_END_OF_LIST(),
 };
 
@@ -177,6 +181,22 @@ static void q35_host_initfn(Object *obj)
                         q35_host_get_mmcfg_size,
                         NULL, NULL, NULL, NULL);
 
+    object_property_add_link(obj, MCH_HOST_PROP_RAM_MEM, TYPE_MEMORY_REGION,
+                             (Object **) &s->mch.ram_memory,
+                             qdev_prop_allow_set_link_before_realize, 0, NULL);
+
+    object_property_add_link(obj, MCH_HOST_PROP_PCI_MEM, TYPE_MEMORY_REGION,
+                             (Object **) &s->mch.pci_address_space,
+                             qdev_prop_allow_set_link_before_realize, 0, NULL);
+
+    object_property_add_link(obj, MCH_HOST_PROP_SYSTEM_MEM, TYPE_MEMORY_REGION,
+                             (Object **) &s->mch.system_memory,
+                             qdev_prop_allow_set_link_before_realize, 0, NULL);
+
+    object_property_add_link(obj, MCH_HOST_PROP_IO_MEM, TYPE_MEMORY_REGION,
+                             (Object **) &s->mch.address_space_io,
+                             qdev_prop_allow_set_link_before_realize, 0, NULL);
+
     /* Leave enough space for the biggest MCFG BAR */
     /* TODO: this matches current bios behaviour, but
      * it's not a power of two, which means an MTRR
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index dc7503d..1e4e383 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -238,6 +238,8 @@ void pc_guest_info_init(PCMachineState *pcms);
 #define PCI_HOST_PROP_PCI_HOLE64_START "pci-hole64-start"
 #define PCI_HOST_PROP_PCI_HOLE64_END   "pci-hole64-end"
 #define PCI_HOST_PROP_PCI_HOLE64_SIZE  "pci-hole64-size"
+#define PCI_HOST_BELOW_4G_MEM_SIZE     "below-4g-mem-size"
+#define PCI_HOST_ABOVE_4G_MEM_SIZE     "above-4g-mem-size"
 #define DEFAULT_PCI_HOLE64_SIZE (~0x0ULL)
 
 
diff --git a/include/hw/pci-host/q35.h b/include/hw/pci-host/q35.h
index c5c073d..8b4bde3 100644
--- a/include/hw/pci-host/q35.h
+++ b/include/hw/pci-host/q35.h
@@ -78,6 +78,11 @@ typedef struct Q35PCIHost {
  * gmch part
  */
 
+#define MCH_HOST_PROP_RAM_MEM "ram-mem"
+#define MCH_HOST_PROP_PCI_MEM "pci-mem"
+#define MCH_HOST_PROP_SYSTEM_MEM "system-mem"
+#define MCH_HOST_PROP_IO_MEM "io-mem"
+
 /* PCI configuration */
 #define MCH_HOST_BRIDGE                        "MCH"
 
-- 
2.7.4

[Qemu-devel] [PATCH v2 06/14] pc_q35: configure Q35 instance using properties

[Efimov Vasily]

Currently, Q35 instance is configured using direct access to structure fields.
The patch uses property interface to set the fields.

Signed-off-by: Efimov Vasily <real@ispras.ru>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
---
 hw/i386/pc_q35.c | 18 ++++++++++++------
 1 file changed, 12 insertions(+), 6 deletions(-)

diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index 78afd4f..67bcede 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -159,12 +159,18 @@ static void pc_q35_init(MachineState *machine)
     q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE));
 
     object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host), NULL);
-    q35_host->mch.ram_memory = ram_memory;
-    q35_host->mch.pci_address_space = pci_memory;
-    q35_host->mch.system_memory = get_system_memory();
-    q35_host->mch.address_space_io = system_io;
-    q35_host->mch.below_4g_mem_size = pcms->below_4g_mem_size;
-    q35_host->mch.above_4g_mem_size = pcms->above_4g_mem_size;
+    object_property_set_link(OBJECT(q35_host), OBJECT(ram_memory),
+                             MCH_HOST_PROP_RAM_MEM, NULL);
+    object_property_set_link(OBJECT(q35_host), OBJECT(pci_memory),
+                             MCH_HOST_PROP_PCI_MEM, NULL);
+    object_property_set_link(OBJECT(q35_host), OBJECT(get_system_memory()),
+                             MCH_HOST_PROP_SYSTEM_MEM, NULL);
+    object_property_set_link(OBJECT(q35_host), OBJECT(system_io),
+                             MCH_HOST_PROP_IO_MEM, NULL);
+    object_property_set_int(OBJECT(q35_host), pcms->below_4g_mem_size,
+                            PCI_HOST_BELOW_4G_MEM_SIZE, NULL);
+    object_property_set_int(OBJECT(q35_host), pcms->above_4g_mem_size,
+                            PCI_HOST_ABOVE_4G_MEM_SIZE, NULL);
     /* pci */
     qdev_init_nofail(DEVICE(q35_host));
     phb = PCI_HOST_BRIDGE(q35_host);
-- 
2.7.4

[Qemu-devel] [PATCH v2 07/14] pckbd: handle A20 IRQ as GPIO

[Efimov Vasily]

The i8042 device has outgouing IRQ line A20. Currently the IRQ is referenced
by a pointer which normally is set during machine initialization. The pointer
is never changed at runtime. So common GPIO model can be applied to A20 IRQ
line. Note that checking for IRQ to be connected as in previous version
of code is not required because qemu_set_irq will do it.

Signed-off-by: Efimov Vasily <real@ispras.ru>
---
 hw/input/pckbd.c     | 21 +++++++--------------
 include/hw/i386/pc.h |  1 +
 2 files changed, 8 insertions(+), 14 deletions(-)

diff --git a/hw/input/pckbd.c b/hw/input/pckbd.c
index 1d932ec..dc57e2c 100644
--- a/hw/input/pckbd.c
+++ b/hw/input/pckbd.c
@@ -146,7 +146,7 @@ typedef struct KBDState {
 
     qemu_irq irq_kbd;
     qemu_irq irq_mouse;
-    qemu_irq *a20_out;
+    qemu_irq a20_out;
     hwaddr mask;
 } KBDState;
 
@@ -224,9 +224,7 @@ static void outport_write(KBDState *s, uint32_t val)
 {
     DPRINTF("kbd: write outport=0x%02x\n", val);
     s->outport = val;
-    if (s->a20_out) {
-        qemu_set_irq(*s->a20_out, (val >> 1) & 1);
-    }
+    qemu_set_irq(s->a20_out, (val >> 1) & 1);
     if (!(val & 1)) {
         qemu_system_reset_request();
     }
@@ -295,15 +293,11 @@ static void kbd_write_command(void *opaque, hwaddr addr,
         kbd_queue(s, s->outport, 0);
         break;
     case KBD_CCMD_ENABLE_A20:
-        if (s->a20_out) {
-            qemu_irq_raise(*s->a20_out);
-        }
+        qemu_irq_raise(s->a20_out);
         s->outport |= KBD_OUT_A20;
         break;
     case KBD_CCMD_DISABLE_A20:
-        if (s->a20_out) {
-            qemu_irq_lower(*s->a20_out);
-        }
+        qemu_irq_lower(s->a20_out);
         s->outport &= ~KBD_OUT_A20;
         break;
     case KBD_CCMD_RESET:
@@ -507,10 +501,7 @@ void i8042_isa_mouse_fake_event(void *opaque)
 
 void i8042_setup_a20_line(ISADevice *dev, qemu_irq *a20_out)
 {
-    ISAKBDState *isa = I8042(dev);
-    KBDState *s = &isa->kbd;
-
-    s->a20_out = a20_out;
+    qdev_connect_gpio_out_named(DEVICE(dev), I8042_A20_LINE, 0, *a20_out);
 }
 
 static const VMStateDescription vmstate_kbd_isa = {
@@ -552,6 +543,8 @@ static void i8042_initfn(Object *obj)
                           "i8042-data", 1);
     memory_region_init_io(isa_s->io + 1, obj, &i8042_cmd_ops, s,
                           "i8042-cmd", 1);
+
+    qdev_init_gpio_out_named(DEVICE(obj), &s->a20_out, I8042_A20_LINE, 1);
 }
 
 static void i8042_realizefn(DeviceState *dev, Error **errp)
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 1e4e383..d615727 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -212,6 +212,7 @@ void vmmouse_get_data(uint32_t *data);
 void vmmouse_set_data(const uint32_t *data);
 
 /* pckbd.c */
+#define I8042_A20_LINE "a20"
 
 void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
 void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
-- 
2.7.4

[Qemu-devel] [PATCH v2 08/14] port92: handle A20 IRQ as GPIO

[Efimov Vasily]

The port92 device has outgouing IRQ line A20. Currently the IRQ is referenced
by a pointer which normally is set during machine initialization. The
pointer is never changed at runtime. Hence, common GPIO model can be applied
to A20 IRQ line. Note that checking for IRQ to be connected as in
previous version of code is not required qemu_set_irq will do it.

Signed-off-by: Efimov Vasily <real@ispras.ru>
---
 hw/i386/pc.c         | 10 +++++-----
 include/hw/i386/pc.h |  2 ++
 2 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 7198ed5..2cd89a9 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -505,7 +505,7 @@ typedef struct Port92State {
 
     MemoryRegion io;
     uint8_t outport;
-    qemu_irq *a20_out;
+    qemu_irq a20_out;
 } Port92State;
 
 static void port92_write(void *opaque, hwaddr addr, uint64_t val,
@@ -516,7 +516,7 @@ static void port92_write(void *opaque, hwaddr addr, uint64_t val,
 
     DPRINTF("port92: write 0x%02" PRIx64 "\n", val);
     s->outport = val;
-    qemu_set_irq(*s->a20_out, (val >> 1) & 1);
+    qemu_set_irq(s->a20_out, (val >> 1) & 1);
     if ((val & 1) && !(oldval & 1)) {
         qemu_system_reset_request();
     }
@@ -535,9 +535,7 @@ static uint64_t port92_read(void *opaque, hwaddr addr,
 
 static void port92_init(ISADevice *dev, qemu_irq *a20_out)
 {
-    Port92State *s = PORT92(dev);
-
-    s->a20_out = a20_out;
+    qdev_connect_gpio_out_named(DEVICE(dev), PORT92_A20_LINE, 0, *a20_out);
 }
 
 static const VMStateDescription vmstate_port92_isa = {
@@ -574,6 +572,8 @@ static void port92_initfn(Object *obj)
     memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1);
 
     s->outport = 0;
+
+    qdev_init_gpio_out_named(DEVICE(obj), &s->a20_out, PORT92_A20_LINE, 1);
 }
 
 static void port92_realizefn(DeviceState *dev, Error **errp)
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index d615727..6a991d9 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -275,6 +275,8 @@ int cmos_get_fd_drive_type(FloppyDriveType fd0);
 
 #define FW_CFG_IO_BASE     0x510
 
+#define PORT92_A20_LINE "a20"
+
 /* acpi_piix.c */
 
 I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
-- 
2.7.4

[Qemu-devel] [PATCH v2 09/14] ICH9 SMB: make TYPE_ICH9_SMB_DEVICE macro public

[Efimov Vasily]

ICH9 SMB bridge can be created using qdev API despite existence of helper
function. The type name is needed for such creation. Using a preprocessor
alias instead the string type name itself is preferable.

The patch makes the alias accessible through the header.

Signed-off-by: Efimov Vasily <real@ispras.ru>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
---
 hw/i2c/smbus_ich9.c    | 1 -
 include/hw/i386/ich9.h | 2 ++
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/hw/i2c/smbus_ich9.c b/hw/i2c/smbus_ich9.c
index 498f03e..48fab22 100644
--- a/hw/i2c/smbus_ich9.c
+++ b/hw/i2c/smbus_ich9.c
@@ -35,7 +35,6 @@
 
 #include "hw/i386/ich9.h"
 
-#define TYPE_ICH9_SMB_DEVICE "ICH9 SMB"
 #define ICH9_SMB_DEVICE(obj) \
      OBJECT_CHECK(ICH9SMBState, (obj), TYPE_ICH9_SMB_DEVICE)
 
diff --git a/include/hw/i386/ich9.h b/include/hw/i386/ich9.h
index 11243e5..a09a445 100644
--- a/include/hw/i386/ich9.h
+++ b/include/hw/i386/ich9.h
@@ -207,6 +207,8 @@ Object *ich9_lpc_find(void);
 
 
 /* D31:F3 SMBus controller */
+#define TYPE_ICH9_SMB_DEVICE "ICH9 SMB"
+
 #define ICH9_A2_SMB_REVISION                    0x02
 #define ICH9_SMB_PI                             0x00
 
-- 
2.7.4

[Qemu-devel] [PATCH v2 10/14] ICH9 LPC: handle GSI as qdev GPIO

[Efimov Vasily]

The ICH9 LPC bridge has 24 output IRQs connected to GSI. Currently the IRQs are
referenced by pointers. The pointers are initialized at startup by direct access
to the structure fields. This violates Qemu device model.

The patch makes the IRQs handling to use GPIO model.

Signed-off-by: Efimov Vasily <real@ispras.ru>
---
 hw/i386/pc_q35.c       | 6 +++++-
 hw/isa/lpc_ich9.c      | 3 +++
 include/hw/i386/ich9.h | 4 +++-
 3 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index 67bcede..d3213fd 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -60,6 +60,7 @@ static void pc_q35_init(MachineState *machine)
     PCIHostState *phb;
     PCIBus *host_bus;
     PCIDevice *lpc;
+    DeviceState *lpc_dev;
     BusState *idebus[MAX_SATA_PORTS];
     ISADevice *rtc_state;
     MemoryRegion *system_io = get_system_io();
@@ -190,7 +191,10 @@ static void pc_q35_init(MachineState *machine)
                              PC_MACHINE_ACPI_DEVICE_PROP, &error_abort);
 
     ich9_lpc = ICH9_LPC_DEVICE(lpc);
-    ich9_lpc->gsi = gsi;
+    lpc_dev = DEVICE(lpc);
+    for (i = 0; i < GSI_NUM_PINS; i++) {
+        qdev_connect_gpio_out_named(lpc_dev, ICH9_GPIO_GSI, i, gsi[i]);
+    }
     pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc,
                  ICH9_LPC_NB_PIRQS);
     pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq);
diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c
index 7703357..36506ec 100644
--- a/hw/isa/lpc_ich9.c
+++ b/hw/isa/lpc_ich9.c
@@ -598,6 +598,7 @@ static void ich9_lpc_initfn(Object *obj)
 static void ich9_lpc_realize(PCIDevice *d, Error **errp)
 {
     ICH9LPCState *lpc = ICH9_LPC_DEVICE(d);
+    DeviceState *dev = DEVICE(d);
     ISABus *isa_bus;
 
     isa_bus = isa_bus_new(DEVICE(d), get_system_memory(), get_system_io(),
@@ -625,6 +626,8 @@ static void ich9_lpc_realize(PCIDevice *d, Error **errp)
     memory_region_add_subregion_overlap(pci_address_space_io(d),
                                         ICH9_RST_CNT_IOPORT, &lpc->rst_cnt_mem,
                                         1);
+
+    qdev_init_gpio_out_named(dev, lpc->gsi, ICH9_GPIO_GSI, GSI_NUM_PINS);
 }
 
 static bool ich9_rst_cnt_needed(void *opaque)
diff --git a/include/hw/i386/ich9.h b/include/hw/i386/ich9.h
index a09a445..c14490b 100644
--- a/include/hw/i386/ich9.h
+++ b/include/hw/i386/ich9.h
@@ -68,7 +68,7 @@ typedef struct ICH9LPCState {
     MemoryRegion rcrb_mem; /* root complex register block */
     Notifier machine_ready;
 
-    qemu_irq *gsi;
+    qemu_irq gsi[GSI_NUM_PINS];
 } ICH9LPCState;
 
 Object *ich9_lpc_find(void);
@@ -176,6 +176,8 @@ Object *ich9_lpc_find(void);
 #define ICH9_LPC_PIC_NUM_PINS                   16
 #define ICH9_LPC_IOAPIC_NUM_PINS                24
 
+#define ICH9_GPIO_GSI "gsi"
+
 /* D31:F2 SATA Controller #1 */
 #define ICH9_SATA1_DEV                          31
 #define ICH9_SATA1_FUNC                         2
-- 
2.7.4

[Qemu-devel] [PATCH v2 11/14] ICH9 LPC: move call of isa_bus_irqs to 'realize' method

[Efimov Vasily]

The isa_bus_irqs function initializes ISA bus IRQ array pointer with specified
value.

Previously the ICH9 LPC bridge model did not have its own IRQs but
only IRQ pointer cache. And same GSI were used for ISA bus and other sources
behind the bridge (PCI, SCI). Hence, the pc_q35_init was only possible place to
setup both ISA bus IRQs and the bridge IRQ cache.

As a result, the call of isa_bus_irqs was made from pc_q35_init.

Now the ICH9 LPC bridge has its own output IRQs which are connected to GSI. The
output IRQs are already used to route IRQs from PCI and SCI.

The patch makes the ICH9 LPC bridge output IRQs to used for ISA bus too.

Signed-off-by: Efimov Vasily <real@ispras.ru>
---
 hw/i386/pc_q35.c  | 3 ---
 hw/isa/lpc_ich9.c | 2 ++
 2 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index d3213fd..0f04c13 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -200,9 +200,6 @@ static void pc_q35_init(MachineState *machine)
     pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq);
     isa_bus = ich9_lpc->isa_bus;
 
-    /*end early*/
-    isa_bus_irqs(isa_bus, gsi);
-
     if (kvm_pic_in_kernel()) {
         i8259 = kvm_i8259_init(isa_bus);
     } else if (xen_enabled()) {
diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c
index 36506ec..c351351 100644
--- a/hw/isa/lpc_ich9.c
+++ b/hw/isa/lpc_ich9.c
@@ -628,6 +628,8 @@ static void ich9_lpc_realize(PCIDevice *d, Error **errp)
                                         1);
 
     qdev_init_gpio_out_named(dev, lpc->gsi, ICH9_GPIO_GSI, GSI_NUM_PINS);
+
+    isa_bus_irqs(isa_bus, lpc->gsi);
 }
 
 static bool ich9_rst_cnt_needed(void *opaque)
-- 
2.7.4

[Qemu-devel] [PATCH v2 12/14] isa: introduce wrapper isa_connect_gpio_out

[Efimov Vasily]

Currently a direct access to the device structure field is used to connect ISA
device IRQ to the bus. GPIO access should be used instead if possible.

The patch adds wrapper isa_connect_gpio_out. The function connects specified
output GPIO to specified ISA IRQ.

Signed-off-by: Efimov Vasily <real@ispras.ru>
---
 hw/isa/isa-bus.c     | 7 +++++++
 include/hw/isa/isa.h | 1 +
 2 files changed, 8 insertions(+)

diff --git a/hw/isa/isa-bus.c b/hw/isa/isa-bus.c
index 7aa115c..ce74db2 100644
--- a/hw/isa/isa-bus.c
+++ b/hw/isa/isa-bus.c
@@ -97,6 +97,13 @@ void isa_init_irq(ISADevice *dev, qemu_irq *p, int isairq)
     dev->nirqs++;
 }
 
+void isa_connect_gpio_out(ISADevice *isadev, int gpioirq, int isairq)
+{
+    qemu_irq irq;
+    isa_init_irq(isadev, &irq, isairq);
+    qdev_connect_gpio_out(DEVICE(isadev), gpioirq, irq);
+}
+
 void isa_bus_dma(ISABus *bus, IsaDma *dma8, IsaDma *dma16)
 {
     assert(bus && dma8 && dma16);
diff --git a/include/hw/isa/isa.h b/include/hw/isa/isa.h
index c87fbad..7693ac5 100644
--- a/include/hw/isa/isa.h
+++ b/include/hw/isa/isa.h
@@ -102,6 +102,7 @@ ISABus *isa_bus_new(DeviceState *dev, MemoryRegion *address_space,
 void isa_bus_irqs(ISABus *bus, qemu_irq *irqs);
 qemu_irq isa_get_irq(ISADevice *dev, int isairq);
 void isa_init_irq(ISADevice *dev, qemu_irq *p, int isairq);
+void isa_connect_gpio_out(ISADevice *isadev, int gpioirq, int isairq);
 void isa_bus_dma(ISABus *bus, IsaDma *dma8, IsaDma *dma16);
 IsaDma *isa_get_dma(ISABus *bus, int nchan);
 MemoryRegion *isa_address_space(ISADevice *dev);
-- 
2.7.4

[Qemu-devel] [PATCH v2 13/14] MC146818 RTC: add GPIO access to output IRQ

[Efimov Vasily]

The MC146818 RTC device has output IRQ line. Currently the corresponding field
is only accessible through direct access. Such access violates Qemu model.

The patch makes the field accessible through GPIO. It also updates the setting
of the IRQ during initialization.

Signed-off-by: Efimov Vasily <real@ispras.ru>
---
 hw/timer/mc146818rtc.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/hw/timer/mc146818rtc.c b/hw/timer/mc146818rtc.c
index f4e333e..ea625f2 100644
--- a/hw/timer/mc146818rtc.c
+++ b/hw/timer/mc146818rtc.c
@@ -906,6 +906,8 @@ static void rtc_realizefn(DeviceState *dev, Error **errp)
 
     object_property_add_alias(qdev_get_machine(), "rtc-time",
                               OBJECT(s), "date", NULL);
+
+    qdev_init_gpio_out(dev, &s->irq, 1);
 }
 
 ISADevice *rtc_init(ISABus *bus, int base_year, qemu_irq intercept_irq)
@@ -920,9 +922,9 @@ ISADevice *rtc_init(ISABus *bus, int base_year, qemu_irq intercept_irq)
     qdev_prop_set_int32(dev, "base_year", base_year);
     qdev_init_nofail(dev);
     if (intercept_irq) {
-        s->irq = intercept_irq;
+        qdev_connect_gpio_out(dev, 0, intercept_irq);
     } else {
-        isa_init_irq(isadev, &s->irq, RTC_ISA_IRQ);
+        isa_connect_gpio_out(isadev, 0, RTC_ISA_IRQ);
     }
     QLIST_INSERT_HEAD(&rtc_devices, s, link);
 
-- 
2.7.4

[Qemu-devel] [PATCH v2 14/14] ICH9 LPC: configure PCI IRQs routing internally

[Efimov Vasily]

ICH9 LPC bridge is used to route PCI IRQs to GSI. The root PCI bus reference is
required to setup the routing. According to specification, the bridge is
connected to root bus. Hence, there is no reason to setup the routing
externally.

The patch moves the setup code to 'realize' method. Also several related
functions are made static because they are no needed outside the bridge
implementation any more.

Signed-off-by: Efimov Vasily <real@ispras.ru>
---
 hw/i386/pc_q35.c       |  3 ---
 hw/isa/lpc_ich9.c      | 10 +++++++---
 include/hw/i386/ich9.h |  3 ---
 3 files changed, 7 insertions(+), 9 deletions(-)

diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index 0f04c13..eca33b3 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -195,9 +195,6 @@ static void pc_q35_init(MachineState *machine)
     for (i = 0; i < GSI_NUM_PINS; i++) {
         qdev_connect_gpio_out_named(lpc_dev, ICH9_GPIO_GSI, i, gsi[i]);
     }
-    pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc,
-                 ICH9_LPC_NB_PIRQS);
-    pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq);
     isa_bus = ich9_lpc->isa_bus;
 
     if (kvm_pic_in_kernel()) {
diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c
index c351351..7a0a0b0 100644
--- a/hw/isa/lpc_ich9.c
+++ b/hw/isa/lpc_ich9.c
@@ -253,7 +253,7 @@ static void ich9_lpc_update_apic(ICH9LPCState *lpc, int gsi)
     qemu_set_irq(lpc->gsi[gsi], level);
 }
 
-void ich9_lpc_set_irq(void *opaque, int pirq, int level)
+static void ich9_lpc_set_irq(void *opaque, int pirq, int level)
 {
     ICH9LPCState *lpc = opaque;
     int pic_irq, pic_dis;
@@ -269,7 +269,7 @@ void ich9_lpc_set_irq(void *opaque, int pirq, int level)
 /* return the pirq number (PIRQ[A-H]:0-7) corresponding to
  * a given device irq pin.
  */
-int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx)
+static int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx)
 {
     BusState *bus = qdev_get_parent_bus(&pci_dev->qdev);
     PCIBus *pci_bus = PCI_BUS(bus);
@@ -280,7 +280,7 @@ int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx)
     return lpc->irr[PCI_SLOT(pci_dev->devfn)][intx];
 }
 
-PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin)
+static PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin)
 {
     ICH9LPCState *lpc = opaque;
     PCIINTxRoute route;
@@ -630,6 +630,10 @@ static void ich9_lpc_realize(PCIDevice *d, Error **errp)
     qdev_init_gpio_out_named(dev, lpc->gsi, ICH9_GPIO_GSI, GSI_NUM_PINS);
 
     isa_bus_irqs(isa_bus, lpc->gsi);
+
+    pci_bus_irqs(lpc->d.bus, ich9_lpc_set_irq, ich9_lpc_map_irq, lpc,
+                 ICH9_LPC_NB_PIRQS);
+    pci_bus_set_route_irq_fn(lpc->d.bus, ich9_route_intx_pin_to_irq);
 }
 
 static bool ich9_rst_cnt_needed(void *opaque)
diff --git a/include/hw/i386/ich9.h b/include/hw/i386/ich9.h
index c14490b..cd96841 100644
--- a/include/hw/i386/ich9.h
+++ b/include/hw/i386/ich9.h
@@ -14,9 +14,6 @@
 #include "hw/acpi/ich9.h"
 #include "hw/pci/pci_bus.h"
 
-void ich9_lpc_set_irq(void *opaque, int irq_num, int level);
-int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx);
-PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin);
 void ich9_lpc_pm_init(PCIDevice *pci_lpc, bool smm_enabled);
 I2CBus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base);
 
-- 
2.7.4

Re: [Qemu-devel] [PATCH v2 00/14] Make Q35 devices closer to Qemu object model.

[Paolo Bonzini]

On 22/06/2016 14:24, Efimov Vasily wrote:
> The patch series makes several devices closer to Qemu object model.
> 
> I am developing a tool that automatize creation of device and machine models.
> 
> Recently, I've take part in development of several models. And I noticed that
> a significant part of code is same. The examples are:
> - Each device represented by a header and a source.
> - The device or machine class is described by a set of callbacks containing in
> TypeInfo structure.
> - Each TypeInfo structure is accounted by a register function.
> - A register function is sheduled by a type_init macro.
> - Class and state structures of an inherited type are prepended by ones of the
> parent type.
> - A device must have VM state description.
> - A device or a machine can have properties.
> - A device can use internal APIs such as: timer, chardev, blockdev, IRQ,
> system bys memory and port mapping, PCI BARs, PCI MSI(X), etc.
> - A machine consists of devices and memory tree. Devices are linked by IRQs and
> buses and assigned property values.
> - All of the above should follow the Qemu coding style.
> 
> For every listed item can be generated a stub code. All stubs can be generated
> with respect to each other forming compileable device (or machine). Ideally,
> a programmer have to implement custom device/machine logic and to assign
> meaningful names to variables, functions, macroses etc. using a refactoring
> tool.
> 
> Of cource, a device/machine description for the tool has to be significantly
> smaller than the code the tool produced. A GUI constructor is preferred too.
> 
> I've chosed Q35 machine to test the tool. The Q35 is one of the most 
> complex boards. I have implemented 64-bit CPU, soft MMU, 1GB RAM, 1 HDD,
> PCI, USB machine variant. Most of devices is instantiated using the object
> model. Some logic (I/O port 80, I/O port F0, A20 line) is dedicated to new
> devices. The stubs for thay is also generated by the tool.
> 
> In course of implementing Q35 I've noticed that some device models does not
> follow Qemu object model close enough. The patch series is desined to make them
> closer.
> 
> Change log:
> 
> v1 -> v2:
> A patch was added after 11-th one. The patch introduces function
> isa_connect_gpio_out needed by new version of consequent patch.
> 
>  01: Git global option diff.renames was set true to generate the patch avoiding
> checkpatch.pl issues.
> 
>  02, 05: qdev_prop_allow_set_link_before_realize is used instead of
> object_property_allow_set_link.
> 
>  07, 08: Named GPIO was used for a20 line.
> 
>  10, 11: The patches were rebased against the patch series
> https://lists.gnu.org/archive/html/qemu-devel/2016-06/msg05619.html
> 
>  10: Named GPIO is used for gsi. The name is "gsi" with alias ICH9_GPIO_GSI.
> 
>  12: It's a new patch. The patch introduces function isa_connect_gpio_out.
> 
>  13 (previously 12): Use isa_connect_gpio_out instead of isa_init_irq.

I have queued patches 1-13, as said before I'm not sure of patch 14 and
I want to think about it some more. :)

Paolo

Re: [Qemu-devel] [PATCH v2 00/14] Make Q35 devices closer to Qemu object model.

[Michael S. Tsirkin]

On Wed, Jun 22, 2016 at 03:24:33PM +0200, Paolo Bonzini wrote:
> 
> 
> On 22/06/2016 14:24, Efimov Vasily wrote:
> > The patch series makes several devices closer to Qemu object model.
> > 
> > I am developing a tool that automatize creation of device and machine models.
> > 
> > Recently, I've take part in development of several models. And I noticed that
> > a significant part of code is same. The examples are:
> > - Each device represented by a header and a source.
> > - The device or machine class is described by a set of callbacks containing in
> > TypeInfo structure.
> > - Each TypeInfo structure is accounted by a register function.
> > - A register function is sheduled by a type_init macro.
> > - Class and state structures of an inherited type are prepended by ones of the
> > parent type.
> > - A device must have VM state description.
> > - A device or a machine can have properties.
> > - A device can use internal APIs such as: timer, chardev, blockdev, IRQ,
> > system bys memory and port mapping, PCI BARs, PCI MSI(X), etc.
> > - A machine consists of devices and memory tree. Devices are linked by IRQs and
> > buses and assigned property values.
> > - All of the above should follow the Qemu coding style.
> > 
> > For every listed item can be generated a stub code. All stubs can be generated
> > with respect to each other forming compileable device (or machine). Ideally,
> > a programmer have to implement custom device/machine logic and to assign
> > meaningful names to variables, functions, macroses etc. using a refactoring
> > tool.
> > 
> > Of cource, a device/machine description for the tool has to be significantly
> > smaller than the code the tool produced. A GUI constructor is preferred too.
> > 
> > I've chosed Q35 machine to test the tool. The Q35 is one of the most 
> > complex boards. I have implemented 64-bit CPU, soft MMU, 1GB RAM, 1 HDD,
> > PCI, USB machine variant. Most of devices is instantiated using the object
> > model. Some logic (I/O port 80, I/O port F0, A20 line) is dedicated to new
> > devices. The stubs for thay is also generated by the tool.
> > 
> > In course of implementing Q35 I've noticed that some device models does not
> > follow Qemu object model close enough. The patch series is desined to make them
> > closer.
> > 
> > Change log:
> > 
> > v1 -> v2:
> > A patch was added after 11-th one. The patch introduces function
> > isa_connect_gpio_out needed by new version of consequent patch.
> > 
> >  01: Git global option diff.renames was set true to generate the patch avoiding
> > checkpatch.pl issues.
> > 
> >  02, 05: qdev_prop_allow_set_link_before_realize is used instead of
> > object_property_allow_set_link.
> > 
> >  07, 08: Named GPIO was used for a20 line.
> > 
> >  10, 11: The patches were rebased against the patch series
> > https://lists.gnu.org/archive/html/qemu-devel/2016-06/msg05619.html
> > 
> >  10: Named GPIO is used for gsi. The name is "gsi" with alias ICH9_GPIO_GSI.
> > 
> >  12: It's a new patch. The patch introduces function isa_connect_gpio_out.
> > 
> >  13 (previously 12): Use isa_connect_gpio_out instead of isa_init_irq.
> 
> I have queued patches 1-13, as said before I'm not sure of patch 14 and
> I want to think about it some more. :)
> 
> Paolo

You can add my
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
if you wish.

I'll comment on 14 separately.

-- 
MST