From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1I4HQQ-0005WT-Qh for qemu-devel@nongnu.org; Fri, 29 Jun 2007 10:26:18 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1I4HQM-0005Vz-M2 for qemu-devel@nongnu.org; Fri, 29 Jun 2007 10:26:17 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1I4HQM-0005Vw-JJ for qemu-devel@nongnu.org; Fri, 29 Jun 2007 10:26:14 -0400 Received: from ug-out-1314.google.com ([66.249.92.171]) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1I4HQL-0000M8-Mx for qemu-devel@nongnu.org; Fri, 29 Jun 2007 10:26:14 -0400 Received: by ug-out-1314.google.com with SMTP id m2so546632uge for ; Fri, 29 Jun 2007 07:26:11 -0700 (PDT) Message-ID: Date: Fri, 29 Jun 2007 16:26:10 +0200 From: "Gwenole Beauchesne" Subject: Re: [Qemu-devel] [PATCH, RFC] More than 2G of memory on 64-bit hosts In-Reply-To: MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: quoted-printable Content-Disposition: inline References: <200706252226.50773.michal.schulz@gmx.de> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Hi, 2007/6/26, Karl Magdsick : > With proper support from the compiler, it's theoretically possible on > x86-64 systems to use 32-bit pointers in long mode (16 general purpose > 64-bit registers). (There's an instruction prefix that will cause the > CPU to perform 32-bit pointer calculations in the 64-bit address > space.) I'm not aware of any systems that use this, however. IIRC, there used to be an ILP32 programming model in long mode for older AMD64 prototypes, i.e. with access to full 64-bit registers. However, nobody was interested in it at that time so this was dropped. There is still however, as you mention, an override prefix to do 32-bit pointer calculation (0x67). Please note documents around the Intel Core processor mention a 5 cycle penalty when you use this prefix. This doesn't seem to be a penalty for AMD processors though. In practise, the impact on the generated code performance of my JIT was measurably marginal (well, I only tested against my Core 2 and Athlon 64 CPUs). BTW, before I switched to using the address override prefix, I used to implement a so-called 33-bit addressing mode in BasiliskII. That is, the emulated address space is doubled to cope with the excess bits during calculation. A shared segment is shm_open()'ed and then mmap()'ed to BASE and BASE+(1L<<32). --=20 Gwenol=E9