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Tue, 13 Aug 2024 20:09:02 -0700 (PDT) Message-ID: Date: Wed, 14 Aug 2024 13:08:53 +1000 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 03/15] tcg: Fix register allocation constraints To: LIU Zhiwei , qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, bmeng.cn@gmail.com, TANG Tiancheng References: <20240813113436.831-1-zhiwei_liu@linux.alibaba.com> <20240813113436.831-4-zhiwei_liu@linux.alibaba.com> <2efe353a-4700-4632-b919-e43cb039c2c0@linaro.org> <1e61235e-1cb8-4bc1-9983-6e8dc0c3b406@linux.alibaba.com> <149df4e8-f51c-4925-8c65-e8e10fed85a3@linaro.org> <5f1f74de-3403-4371-97eb-f376e65b7ae5@linux.alibaba.com> Content-Language: en-US From: Richard Henderson In-Reply-To: <5f1f74de-3403-4371-97eb-f376e65b7ae5@linux.alibaba.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 8/14/24 12:27, LIU Zhiwei wrote: > > On 2024/8/14 10:04, Richard Henderson wrote: >> On 8/14/24 10:58, LIU Zhiwei wrote: >>> Thus if we want to use all registers of vectors, we have to add a dynamic constraint on >>> register allocation based on IR types. >> >> My comment vs patch 4 is that you can't do that, at least not without large changes to TCG. >> >> In addition, I said that the register pressure on vector regs is not high enough to >> justify such changes.  There is, so far, little benefit in having more than 4 or 5 >> vector registers, much less 32.  Thus 7 (lmul 4, omitting v0) is sufficient. > > At least on QEMU, SVE can support 2048 bit vector length with 'sve-default-vector- > length=256'.  Software optimized with SVE, such as X264 can benefit with long SVE length > in less dynamic A64 instructions. > > We want to expose all host vector ability. Thus the largest TCG_TYPE_V256 is not enough, > as 128-bit RVV can give 8*128=1024 width operation. We have expand TCG_TYPE_V512/1024/2048 > types(not in this patch set, but intend to upstream later). > With large TCG_TYPE_V1024/2048, we get better performance on RISC-V board with much less > translated RISC-V vector instructions. We can give a more detailed experiment result if > needed. > > However, we will only have 3 vector register when support TCG_TYPE_V1024.  And even less > for TCG_TYPE_V2048.  Current approach will give more vectors TCG_TYPE_V128 even with > support TCG_TYPE_V1024, which will relax some guest NEON register pressure. Then you will have to teach TCG about one operand consuming and clobbering N hard registers, so that you get the spills and fills done correctly. But you haven't done that in this patch set, so will currently generate incorrect code. I think you should make longer vector operations a longer term project, and start with something simpler. r~