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[216.71.219.44]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3494f596877sm2444342a91.9.2025.12.04.10.36.31 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 04 Dec 2025 10:36:32 -0800 (PST) Message-ID: Date: Thu, 4 Dec 2025 10:36:31 -0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC RESEND v5 2/4] hw/misc: Introduce iommu-testdev for bare-metal IOMMU testing Content-Language: en-US To: Tao Tang , Paolo Bonzini , Fabiano Rosas , Laurent Vivier , Eric Auger , Peter Maydell , =?UTF-8?Q?Alex_Benn=C3=A9e?= Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, Chen Baozi , =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= , Jean-Philippe Brucker , Mostafa Saleh , CLEMENT MATHIEU--DRIF References: <20251126154547.1300748-1-tangtao1634@phytium.com.cn> <20251126154547.1300748-3-tangtao1634@phytium.com.cn> From: Pierrick Bouvier In-Reply-To: <20251126154547.1300748-3-tangtao1634@phytium.com.cn> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=pierrick.bouvier@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 11/26/25 7:45 AM, Tao Tang wrote: > Add a minimal PCI test device designed to exercise IOMMU translation > (such as ARM SMMUv3) without requiring guest firmware or OS. The device > provides MMIO registers to configure and trigger DMA operations with > controllable attributes (security state, address space), enabling > deterministic IOMMU testing. > > Key features: > - Bare-metal IOMMU testing via simple MMIO interface > - Configurable DMA attributes for security states and address spaces > - Write-then-read verification pattern with automatic result checking > > The device performs a deterministic DMA test pattern: write a known > value (0x88888888) to a configured IOVA, read it back, and verify data > integrity. Results are reported through a dedicated result register, > eliminating the need for complex interrupt handling or driver > infrastructure in tests. > > This is purely a test device and not intended for production use or > machine realism. It complements existing test infrastructure like > pci-testdev but focuses specifically on IOMMU translation path > validation. > > Signed-off-by: Tao Tang > --- > docs/specs/index.rst | 1 + > docs/specs/iommu-testdev.rst | 109 +++++++++++++ > hw/misc/Kconfig | 5 + > hw/misc/iommu-testdev.c | 278 ++++++++++++++++++++++++++++++++ > hw/misc/meson.build | 1 + > hw/misc/trace-events | 10 ++ > include/hw/misc/iommu-testdev.h | 70 ++++++++ > 7 files changed, 474 insertions(+) > create mode 100644 docs/specs/iommu-testdev.rst > create mode 100644 hw/misc/iommu-testdev.c > create mode 100644 include/hw/misc/iommu-testdev.h Overall, the test device looks sane and has a clear interface, that can be used for several iommu implementations, beyond Arm smmu. Reviewed-by: Pierrick Bouvier