From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CE8DAC46CD2 for ; Wed, 24 Jan 2024 06:52:48 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rSX7a-00067G-Fn; Wed, 24 Jan 2024 01:52:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rSX7W-00066f-R9; Wed, 24 Jan 2024 01:52:22 -0500 Received: from gandalf.ozlabs.org ([150.107.74.76]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rSX7T-0003vS-RT; Wed, 24 Jan 2024 01:52:21 -0500 Received: from gandalf.ozlabs.org (gandalf.ozlabs.org [150.107.74.76]) by gandalf.ozlabs.org (Postfix) with ESMTP id 4TKZQ933Vkz4x2S; Wed, 24 Jan 2024 17:52:17 +1100 (AEDT) Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4TKZQ72pVvz4wd4; Wed, 24 Jan 2024 17:52:15 +1100 (AEDT) Message-ID: Date: Wed, 24 Jan 2024 07:52:13 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/5] hw/arm/aspeed: Set default CPU count using aspeed_soc_num_cpus() Content-Language: en-US To: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= , qemu-devel@nongnu.org Cc: Peter Maydell , qemu-arm@nongnu.org, Joel Stanley , Andrew Jeffery References: <20240123224842.18485-1-philmd@linaro.org> <20240123224842.18485-3-philmd@linaro.org> From: =?UTF-8?Q?C=C3=A9dric_Le_Goater?= In-Reply-To: <20240123224842.18485-3-philmd@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=150.107.74.76; envelope-from=SRS0=rIgd=JC=kaod.org=clg@ozlabs.org; helo=gandalf.ozlabs.org X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 1/23/24 23:48, Philippe Mathieu-Daudé wrote: > Since commit b7f1a0cb76 ("arm/aspeed: Compute the number > of CPUs from the SoC definition") Aspeed machines use the > aspeed_soc_num_cpus() helper to set the number of CPUs. > > Use it for the ast1030-evb (commit 356b230ed1 "aspeed/soc: > Add AST1030 support") and supermicrox11-bmc (commit 40a38df55e > "hw/arm/aspeed: Add board model for Supermicro X11 BMC") machines. > > Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Cédric Le Goater Thanks, C. > --- > hw/arm/aspeed.c | 5 ++++- > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c > index 4bc292ff84..5b01a4dd28 100644 > --- a/hw/arm/aspeed.c > +++ b/hw/arm/aspeed.c > @@ -1212,6 +1212,8 @@ static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc, > amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; > amc->i2c_init = palmetto_bmc_i2c_init; > mc->default_ram_size = 256 * MiB; > + mc->default_cpus = mc->min_cpus = mc->max_cpus = > + aspeed_soc_num_cpus(amc->soc_name); > } > > static void aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass *oc, > @@ -1586,11 +1588,12 @@ static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc, > mc->init = aspeed_minibmc_machine_init; > amc->i2c_init = ast1030_evb_i2c_init; > mc->default_ram_size = 0; > - mc->default_cpus = mc->min_cpus = mc->max_cpus = 1; > amc->fmc_model = "sst25vf032b"; > amc->spi_model = "sst25vf032b"; > amc->num_cs = 2; > amc->macs_mask = 0; > + mc->default_cpus = mc->min_cpus = mc->max_cpus = > + aspeed_soc_num_cpus(amc->soc_name); > } > > static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc,