Re: [PATCH v2 2/3] target/riscv: Add MXLEN check for F/D/Q applies to zama16b

[Richard Henderson <richard.henderson@linaro.org>]

On 8/2/24 16:42, LIU Zhiwei wrote:
> 
> On 2024/8/2 13:47, Richard Henderson wrote:
>> On 8/2/24 13:16, LIU Zhiwei wrote:
>>> Zama16b loads and stores of no more than MXLEN bits defined in the F, D, and Q
>>> extensions.
>>>
>>> Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
>>> ---
>>>   target/riscv/insn_trans/trans_rvd.c.inc | 4 ++--
>>>   1 file changed, 2 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_trans/ 
>>> trans_rvd.c.inc
>>> index 2be037930a..dbe508c7e0 100644
>>> --- a/target/riscv/insn_trans/trans_rvd.c.inc
>>> +++ b/target/riscv/insn_trans/trans_rvd.c.inc
>>> @@ -52,7 +52,7 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a)
>>>        * in the F, D, and Q extensions. Otherwise, it falls through to default
>>>        * MO_ATOM_IFALIGN.
>>>        */
>>> -    if ((ctx->xl >= MXL_RV64) && (ctx->cfg_ptr->ext_zama16b)) {
>>> +    if ((ctx->misa_mxl_max >= MXL_RV64) && ctx->cfg_ptr->ext_zama16b) {
>>>           memop |= MO_ATOM_WITHIN16;
>>>       }
>>>   @@ -72,7 +72,7 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a)
>>>       REQUIRE_FPU;
>>>       REQUIRE_EXT(ctx, RVD);
>>>   -    if (ctx->cfg_ptr->ext_zama16b) {
>>> +    if ((ctx->misa_mxl_max >= MXL_RV64) && ctx->cfg_ptr->ext_zama16b) {
>>>           memop |= MO_ATOM_WITHIN16;
>>>       }
>>
>> I guess this is ok, because MXL cannot currently be changed. But since that is a 
>> possible future enhancement, perhaps add a get_mxl(ctx) accessor anyway, for 
>> documentation purposes.
> Can we use the existing get_xl_max(ctx) instead of adding a new get_mxl(ctx).

Yes, that looks fine.
That could be renamed get_mxl.  :-)


r~